Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T16
1	0	Covered	T2,T3,T21
1	1	Covered	T2,T18,T3

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	400261923	4003	0	0
g_div2.Div2Whole_A	400261923	4720	0	0
g_div4.Div4Stepped_A	199267500	3915	0	0
g_div4.Div4Whole_A	199267500	4475	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400261923	4003	0	0
T2	329915	25	0	0
T3	260831	61	0	0
T9	0	12	0	0
T10	0	45	0	0
T12	0	17	0	0
T17	1866	0	0	0
T18	1058	1	0	0
T19	2846	0	0	0
T20	82276	0	0	0
T21	2219	3	0	0
T22	82464	0	0	0
T26	5825	0	0	0
T27	3700	0	0	0
T110	0	1	0	0
T111	0	7	0	0
T112	0	9	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400261923	4720	0	0
T2	329915	27	0	0
T3	260831	62	0	0
T9	0	16	0	0
T10	0	56	0	0
T12	0	21	0	0
T17	1866	0	0	0
T18	1058	1	0	0
T19	2846	0	0	0
T20	82276	0	0	0
T21	2219	5	0	0
T22	82464	0	0	0
T26	5825	0	0	0
T27	3700	0	0	0
T110	0	1	0	0
T111	0	7	0	0
T112	0	9	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199267500	3915	0	0
T2	164504	25	0	0
T3	130393	60	0	0
T9	0	11	0	0
T10	0	44	0	0
T12	0	17	0	0
T17	900	0	0	0
T18	528	1	0	0
T19	1377	0	0	0
T20	41119	0	0	0
T21	1118	2	0	0
T22	41200	0	0	0
T26	2894	0	0	0
T27	1818	0	0	0
T110	0	1	0	0
T111	0	7	0	0
T112	0	9	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199267500	4475	0	0
T2	164504	27	0	0
T3	130393	62	0	0
T9	0	14	0	0
T10	0	54	0	0
T12	0	21	0	0
T17	900	0	0	0
T18	528	1	0	0
T19	1377	0	0	0
T20	41119	0	0	0
T21	1118	5	0	0
T22	41200	0	0	0
T26	2894	0	0	0
T27	1818	0	0	0
T110	0	1	0	0
T111	0	7	0	0
T112	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T16
1	0	Covered	T2,T3,T21
1	1	Covered	T2,T18,T3

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	400261923	4003	0	0
g_div2.Div2Whole_A	400261923	4720	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400261923	4003	0	0
T2	329915	25	0	0
T3	260831	61	0	0
T9	0	12	0	0
T10	0	45	0	0
T12	0	17	0	0
T17	1866	0	0	0
T18	1058	1	0	0
T19	2846	0	0	0
T20	82276	0	0	0
T21	2219	3	0	0
T22	82464	0	0	0
T26	5825	0	0	0
T27	3700	0	0	0
T110	0	1	0	0
T111	0	7	0	0
T112	0	9	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400261923	4720	0	0
T2	329915	27	0	0
T3	260831	62	0	0
T9	0	16	0	0
T10	0	56	0	0
T12	0	21	0	0
T17	1866	0	0	0
T18	1058	1	0	0
T19	2846	0	0	0
T20	82276	0	0	0
T21	2219	5	0	0
T22	82464	0	0	0
T26	5825	0	0	0
T27	3700	0	0	0
T110	0	1	0	0
T111	0	7	0	0
T112	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T16
1	0	Covered	T2,T3,T21
1	1	Covered	T2,T18,T3

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	199267500	3915	0	0
g_div4.Div4Whole_A	199267500	4475	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199267500	3915	0	0
T2	164504	25	0	0
T3	130393	60	0	0
T9	0	11	0	0
T10	0	44	0	0
T12	0	17	0	0
T17	900	0	0	0
T18	528	1	0	0
T19	1377	0	0	0
T20	41119	0	0	0
T21	1118	2	0	0
T22	41200	0	0	0
T26	2894	0	0	0
T27	1818	0	0	0
T110	0	1	0	0
T111	0	7	0	0
T112	0	9	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199267500	4475	0	0
T2	164504	27	0	0
T3	130393	62	0	0
T9	0	14	0	0
T10	0	54	0	0
T12	0	21	0	0
T17	900	0	0	0
T18	528	1	0	0
T19	1377	0	0	0
T20	41119	0	0	0
T21	1118	5	0	0
T22	41200	0	0	0
T26	2894	0	0	0
T27	1818	0	0	0
T110	0	1	0	0
T111	0	7	0	0
T112	0	9	0	0