Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	404071545	394	0	0
StatusRise_A	404071545	394	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404071545	394	0	0
T9	2176029	0	0	0
T10	770022	0	0	0
T22	319824	0	0	0
T27	3129	8	0	0
T28	215097	0	0	0
T29	306504	0	0	0
T30	351645	0	0	0
T31	4119	0	0	0
T36	0	11	0	0
T37	0	10	0	0
T38	0	1	0	0
T86	0	12	0	0
T88	0	14	0	0
T110	4434	0	0	0
T113	4305	0	0	0
T154	0	16	0	0
T155	0	18	0	0
T156	0	6	0	0
T157	0	7	0	0
T158	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404071545	394	0	0
T9	2176029	0	0	0
T10	770022	0	0	0
T22	319824	0	0	0
T27	3129	8	0	0
T28	215097	0	0	0
T29	306504	0	0	0
T30	351645	0	0	0
T31	4119	0	0	0
T36	0	11	0	0
T37	0	10	0	0
T38	0	1	0	0
T86	0	12	0	0
T88	0	14	0	0
T110	4434	0	0	0
T113	4305	0	0	0
T154	0	16	0	0
T155	0	18	0	0
T156	0	6	0	0
T157	0	7	0	0
T158	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	134690515	130	0	0
StatusRise_A	134690515	130	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134690515	130	0	0
T9	725343	0	0	0
T10	256674	0	0	0
T22	106608	0	0	0
T27	1043	2	0	0
T28	71699	0	0	0
T29	102168	0	0	0
T30	117215	0	0	0
T31	1373	0	0	0
T36	0	4	0	0
T37	0	4	0	0
T86	0	4	0	0
T88	0	4	0	0
T110	1478	0	0	0
T113	1435	0	0	0
T154	0	7	0	0
T155	0	5	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134690515	130	0	0
T9	725343	0	0	0
T10	256674	0	0	0
T22	106608	0	0	0
T27	1043	2	0	0
T28	71699	0	0	0
T29	102168	0	0	0
T30	117215	0	0	0
T31	1373	0	0	0
T36	0	4	0	0
T37	0	4	0	0
T86	0	4	0	0
T88	0	4	0	0
T110	1478	0	0	0
T113	1435	0	0	0
T154	0	7	0	0
T155	0	5	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	134690515	131	0	0
StatusRise_A	134690515	131	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134690515	131	0	0
T9	725343	0	0	0
T10	256674	0	0	0
T22	106608	0	0	0
T27	1043	3	0	0
T28	71699	0	0	0
T29	102168	0	0	0
T30	117215	0	0	0
T31	1373	0	0	0
T36	0	4	0	0
T37	0	4	0	0
T86	0	4	0	0
T88	0	4	0	0
T110	1478	0	0	0
T113	1435	0	0	0
T154	0	4	0	0
T155	0	7	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134690515	131	0	0
T9	725343	0	0	0
T10	256674	0	0	0
T22	106608	0	0	0
T27	1043	3	0	0
T28	71699	0	0	0
T29	102168	0	0	0
T30	117215	0	0	0
T31	1373	0	0	0
T36	0	4	0	0
T37	0	4	0	0
T86	0	4	0	0
T88	0	4	0	0
T110	1478	0	0	0
T113	1435	0	0	0
T154	0	4	0	0
T155	0	7	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	134690515	133	0	0
StatusRise_A	134690515	133	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134690515	133	0	0
T9	725343	0	0	0
T10	256674	0	0	0
T22	106608	0	0	0
T27	1043	3	0	0
T28	71699	0	0	0
T29	102168	0	0	0
T30	117215	0	0	0
T31	1373	0	0	0
T36	0	3	0	0
T37	0	2	0	0
T38	0	1	0	0
T86	0	4	0	0
T88	0	6	0	0
T110	1478	0	0	0
T113	1435	0	0	0
T154	0	5	0	0
T155	0	6	0	0
T156	0	2	0	0
T157	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134690515	133	0	0
T9	725343	0	0	0
T10	256674	0	0	0
T22	106608	0	0	0
T27	1043	3	0	0
T28	71699	0	0	0
T29	102168	0	0	0
T30	117215	0	0	0
T31	1373	0	0	0
T36	0	3	0	0
T37	0	2	0	0
T38	0	1	0	0
T86	0	4	0	0
T88	0	6	0	0
T110	1478	0	0	0
T113	1435	0	0	0
T154	0	5	0	0
T155	0	6	0	0
T156	0	2	0	0
T157	0	3	0	0