Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T27
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	44283	0	0
CgEnOn_A	2147483647	34601	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	44283	0	0
T1	710871	3	0	0
T2	2906416	151	0	0
T3	2269849	270	0	0
T4	132975	13	0	0
T5	13872	5	0	0
T9	3308363	0	0	0
T10	2335808	0	0	0
T16	43989	15	0	0
T17	11920	41	0	0
T18	6780	3	0	0
T19	18189	3	0	0
T20	656558	3	0	0
T22	431140	0	0	0
T26	0	6	0	0
T27	18034	17	0	0
T28	287626	0	0	0
T29	421359	0	0	0
T30	468247	0	0	0
T31	6621	0	0	0
T36	0	20	0	0
T37	0	20	0	0
T86	0	20	0	0
T88	0	20	0	0
T110	7137	0	0	0
T113	28794	0	0	0
T154	0	20	0	0
T155	0	35	0	0
T156	0	10	0	0
T157	0	10	0	0
T158	0	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34601	0	0
T1	115410	0	0	0
T2	1671411	133	0	0
T3	1316946	237	0	0
T4	21590	10	0	0
T5	2255	2	0	0
T9	1516323	103	0	0
T10	1077577	309	0	0
T12	0	71	0	0
T16	0	12	0	0
T17	5158	38	0	0
T18	2949	0	0	0
T19	7874	0	0	0
T20	259660	0	0	0
T21	3896	0	0	0
T22	329726	0	0	0
T26	10165	0	0	0
T27	14670	26	0	0
T28	109812	0	0	0
T29	160152	0	0	0
T30	177553	0	0	0
T31	3038	0	0	0
T36	0	32	0	0
T37	0	20	0	0
T86	0	20	0	0
T88	0	20	0	0
T110	3318	0	0	0
T113	13324	4	0	0
T154	0	20	0	0
T155	0	35	0	0
T156	0	10	0	0
T157	0	10	0	0
T158	0	10	0	0
T159	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T27
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	199267078	138	0	0
CgEnOn_A	199267078	138	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199267078	138	0	0
T9	335801	0	0	0
T10	239441	0	0	0
T22	41199	0	0	0
T27	1817	3	0	0
T28	16394	0	0	0
T29	23619	0	0	0
T30	26015	0	0	0
T31	661	0	0	0
T36	0	4	0	0
T37	0	4	0	0
T86	0	4	0	0
T88	0	4	0	0
T110	736	0	0	0
T113	2934	0	0	0
T154	0	4	0	0
T155	0	7	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199267078	138	0	0
T9	335801	0	0	0
T10	239441	0	0	0
T22	41199	0	0	0
T27	1817	3	0	0
T28	16394	0	0	0
T29	23619	0	0	0
T30	26015	0	0	0
T31	661	0	0	0
T36	0	4	0	0
T37	0	4	0	0
T86	0	4	0	0
T88	0	4	0	0
T110	736	0	0	0
T113	2934	0	0	0
T154	0	4	0	0
T155	0	7	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T27
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	99632982	138	0	0
CgEnOn_A	99632982	138	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99632982	138	0	0
T9	167898	0	0	0
T10	119720	0	0	0
T22	20600	0	0	0
T27	909	3	0	0
T28	8196	0	0	0
T29	11808	0	0	0
T30	13005	0	0	0
T31	330	0	0	0
T36	0	4	0	0
T37	0	4	0	0
T86	0	4	0	0
T88	0	4	0	0
T110	368	0	0	0
T113	1467	0	0	0
T154	0	4	0	0
T155	0	7	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99632982	138	0	0
T9	167898	0	0	0
T10	119720	0	0	0
T22	20600	0	0	0
T27	909	3	0	0
T28	8196	0	0	0
T29	11808	0	0	0
T30	13005	0	0	0
T31	330	0	0	0
T36	0	4	0	0
T37	0	4	0	0
T86	0	4	0	0
T88	0	4	0	0
T110	368	0	0	0
T113	1467	0	0	0
T154	0	4	0	0
T155	0	7	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T27
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	99632982	138	0	0
CgEnOn_A	99632982	138	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99632982	138	0	0
T9	167898	0	0	0
T10	119720	0	0	0
T22	20600	0	0	0
T27	909	3	0	0
T28	8196	0	0	0
T29	11808	0	0	0
T30	13005	0	0	0
T31	330	0	0	0
T36	0	4	0	0
T37	0	4	0	0
T86	0	4	0	0
T88	0	4	0	0
T110	368	0	0	0
T113	1467	0	0	0
T154	0	4	0	0
T155	0	7	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99632982	138	0	0
T9	167898	0	0	0
T10	119720	0	0	0
T22	20600	0	0	0
T27	909	3	0	0
T28	8196	0	0	0
T29	11808	0	0	0
T30	13005	0	0	0
T31	330	0	0	0
T36	0	4	0	0
T37	0	4	0	0
T86	0	4	0	0
T88	0	4	0	0
T110	368	0	0	0
T113	1467	0	0	0
T154	0	4	0	0
T155	0	7	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T27
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	99632982	138	0	0
CgEnOn_A	99632982	138	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99632982	138	0	0
T9	167898	0	0	0
T10	119720	0	0	0
T22	20600	0	0	0
T27	909	3	0	0
T28	8196	0	0	0
T29	11808	0	0	0
T30	13005	0	0	0
T31	330	0	0	0
T36	0	4	0	0
T37	0	4	0	0
T86	0	4	0	0
T88	0	4	0	0
T110	368	0	0	0
T113	1467	0	0	0
T154	0	4	0	0
T155	0	7	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99632982	138	0	0
T9	167898	0	0	0
T10	119720	0	0	0
T22	20600	0	0	0
T27	909	3	0	0
T28	8196	0	0	0
T29	11808	0	0	0
T30	13005	0	0	0
T31	330	0	0	0
T36	0	4	0	0
T37	0	4	0	0
T86	0	4	0	0
T88	0	4	0	0
T110	368	0	0	0
T113	1467	0	0	0
T154	0	4	0	0
T155	0	7	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T27
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	400261490	138	0	0
CgEnOn_A	400261490	133	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400261490	138	0	0
T9	676828	0	0	0
T10	478976	0	0	0
T22	82464	0	0	0
T27	3700	3	0	0
T28	68830	0	0	0
T29	101109	0	0	0
T30	112523	0	0	0
T31	1387	0	0	0
T36	0	4	0	0
T37	0	4	0	0
T86	0	4	0	0
T88	0	4	0	0
T110	1478	0	0	0
T113	5989	0	0	0
T154	0	4	0	0
T155	0	7	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400261490	133	0	0
T9	676828	0	0	0
T10	478976	0	0	0
T22	82464	0	0	0
T27	3700	3	0	0
T28	68830	0	0	0
T29	101109	0	0	0
T30	112523	0	0	0
T31	1387	0	0	0
T36	0	4	0	0
T37	0	4	0	0
T86	0	4	0	0
T88	0	4	0	0
T110	1478	0	0	0
T113	5989	0	0	0
T154	0	4	0	0
T155	0	7	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T27
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	426476703	133	0	0
CgEnOn_A	426476703	130	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426476703	133	0	0
T9	723756	0	0	0
T10	507350	0	0	0
T22	97902	0	0	0
T27	3925	2	0	0
T28	71699	0	0	0
T29	105325	0	0	0
T30	117215	0	0	0
T31	1445	0	0	0
T36	0	4	0	0
T37	0	4	0	0
T66	0	1	0	0
T86	0	4	0	0
T88	0	4	0	0
T110	1540	0	0	0
T113	6238	0	0	0
T154	0	7	0	0
T155	0	5	0	0
T156	0	2	0	0
T157	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426476703	130	0	0
T9	723756	0	0	0
T10	507350	0	0	0
T22	97902	0	0	0
T27	3925	2	0	0
T28	71699	0	0	0
T29	105325	0	0	0
T30	117215	0	0	0
T31	1445	0	0	0
T36	0	4	0	0
T37	0	4	0	0
T86	0	4	0	0
T88	0	4	0	0
T110	1540	0	0	0
T113	6238	0	0	0
T154	0	7	0	0
T155	0	5	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T27
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	426476703	133	0	0
CgEnOn_A	426476703	130	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426476703	133	0	0
T9	723756	0	0	0
T10	507350	0	0	0
T22	97902	0	0	0
T27	3925	2	0	0
T28	71699	0	0	0
T29	105325	0	0	0
T30	117215	0	0	0
T31	1445	0	0	0
T36	0	4	0	0
T37	0	4	0	0
T66	0	1	0	0
T86	0	4	0	0
T88	0	4	0	0
T110	1540	0	0	0
T113	6238	0	0	0
T154	0	7	0	0
T155	0	5	0	0
T156	0	2	0	0
T157	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426476703	130	0	0
T9	723756	0	0	0
T10	507350	0	0	0
T22	97902	0	0	0
T27	3925	2	0	0
T28	71699	0	0	0
T29	105325	0	0	0
T30	117215	0	0	0
T31	1445	0	0	0
T36	0	4	0	0
T37	0	4	0	0
T86	0	4	0	0
T88	0	4	0	0
T110	1540	0	0	0
T113	6238	0	0	0
T154	0	7	0	0
T155	0	5	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T27
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	204841768	136	0	0
CgEnOn_A	204841768	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204841768	136	0	0
T9	344528	0	0	0
T10	243531	0	0	0
T15	0	1	0	0
T22	49873	0	0	0
T27	1940	3	0	0
T28	34416	0	0	0
T29	50557	0	0	0
T30	56264	0	0	0
T31	693	0	0	0
T36	0	3	0	0
T37	0	2	0	0
T38	0	1	0	0
T86	0	4	0	0
T88	0	6	0	0
T110	739	0	0	0
T113	2994	0	0	0
T154	0	5	0	0
T155	0	6	0	0
T156	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204841768	135	0	0
T9	344528	0	0	0
T10	243531	0	0	0
T15	0	1	0	0
T22	49873	0	0	0
T27	1940	3	0	0
T28	34416	0	0	0
T29	50557	0	0	0
T30	56264	0	0	0
T31	693	0	0	0
T36	0	3	0	0
T37	0	2	0	0
T38	0	1	0	0
T86	0	4	0	0
T88	0	6	0	0
T110	739	0	0	0
T113	2994	0	0	0
T154	0	5	0	0
T155	0	6	0	0
T156	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T27,T36,T37
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	99632982	7113	0	0
CgEnOn_A	99632982	4701	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99632982	7113	0	0
T1	27681	1	0	0
T2	822520	38	0	0
T3	651966	76	0	0
T4	5175	1	0	0
T5	535	1	0	0
T16	1705	1	0	0
T17	450	14	0	0
T18	264	1	0	0
T19	688	1	0	0
T20	20559	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99632982	4701	0	0
T2	822520	32	0	0
T3	651966	65	0	0
T9	0	28	0	0
T10	0	85	0	0
T12	0	25	0	0
T17	450	13	0	0
T18	264	0	0	0
T19	688	0	0	0
T20	20559	0	0	0
T21	559	0	0	0
T22	20600	0	0	0
T26	1447	0	0	0
T27	909	3	0	0
T36	0	4	0	0
T113	0	1	0	0
T159	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T27,T36,T37
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	199267078	7160	0	0
CgEnOn_A	199267078	4748	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199267078	7160	0	0
T1	55362	1	0	0
T2	164504	40	0	0
T3	130393	74	0	0
T4	10351	1	0	0
T5	1070	1	0	0
T16	3411	1	0	0
T17	900	13	0	0
T18	527	1	0	0
T19	1376	1	0	0
T20	41119	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199267078	4748	0	0
T2	164504	34	0	0
T3	130393	63	0	0
T9	0	31	0	0
T10	0	91	0	0
T12	0	23	0	0
T17	900	12	0	0
T18	527	0	0	0
T19	1376	0	0	0
T20	41119	0	0	0
T21	1118	0	0	0
T22	41199	0	0	0
T26	2893	0	0	0
T27	1817	3	0	0
T36	0	4	0	0
T113	0	1	0	0
T159	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T27,T36,T37
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	400261490	7156	0	0
CgEnOn_A	400261490	4739	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400261490	7156	0	0
T1	110790	1	0	0
T2	329915	40	0	0
T3	260831	71	0	0
T4	20726	1	0	0
T5	2165	1	0	0
T16	6860	1	0	0
T17	1865	14	0	0
T18	1057	1	0	0
T19	2846	1	0	0
T20	82276	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400261490	4739	0	0
T2	329915	34	0	0
T3	260831	60	0	0
T9	0	29	0	0
T10	0	87	0	0
T12	0	23	0	0
T17	1865	13	0	0
T18	1057	0	0	0
T19	2846	0	0	0
T20	82276	0	0	0
T21	2219	0	0	0
T22	82464	0	0	0
T26	5825	0	0	0
T27	3700	3	0	0
T36	0	4	0	0
T113	0	1	0	0
T159	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T27,T36,T38
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	204841768	7130	0	0
CgEnOn_A	204841768	4713	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204841768	7130	0	0
T1	55398	1	0	0
T2	171589	38	0	0
T3	131635	76	0	0
T4	10363	1	0	0
T5	1082	1	0	0
T16	3429	1	0	0
T17	933	15	0	0
T18	528	1	0	0
T19	1423	1	0	0
T20	49780	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204841768	4713	0	0
T2	171589	32	0	0
T3	131635	65	0	0
T9	0	31	0	0
T10	0	88	0	0
T12	0	24	0	0
T17	933	14	0	0
T18	528	0	0	0
T19	1423	0	0	0
T20	49780	0	0	0
T21	1109	0	0	0
T22	49873	0	0	0
T26	2912	0	0	0
T27	1940	3	0	0
T36	0	3	0	0
T113	0	1	0	0
T159	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T27
1	0	Covered	T4,T5,T16
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	426476703	3656	0	0
CgEnOn_A	426476703	3653	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426476703	3656	0	0
T1	115410	0	0	0
T2	354472	33	0	0
T3	273756	49	0	0
T4	21590	10	0	0
T5	2255	2	0	0
T9	0	15	0	0
T10	0	46	0	0
T16	7146	12	0	0
T17	1943	0	0	0
T18	1101	0	0	0
T19	2964	0	0	0
T20	115706	0	0	0
T26	0	6	0	0
T27	0	2	0	0
T113	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426476703	3653	0	0
T1	115410	0	0	0
T2	354472	33	0	0
T3	273756	49	0	0
T4	21590	10	0	0
T5	2255	2	0	0
T9	0	15	0	0
T10	0	46	0	0
T16	7146	12	0	0
T17	1943	0	0	0
T18	1101	0	0	0
T19	2964	0	0	0
T20	115706	0	0	0
T26	0	6	0	0
T27	0	2	0	0
T113	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T27
1	0	Covered	T4,T5,T16
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	426476703	3665	0	0
CgEnOn_A	426476703	3662	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426476703	3665	0	0
T1	115410	0	0	0
T2	354472	34	0	0
T3	273756	50	0	0
T4	21590	6	0	0
T5	2255	3	0	0
T9	0	14	0	0
T10	0	41	0	0
T16	7146	11	0	0
T17	1943	0	0	0
T18	1101	0	0	0
T19	2964	0	0	0
T20	115706	0	0	0
T26	0	2	0	0
T27	0	2	0	0
T113	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426476703	3662	0	0
T1	115410	0	0	0
T2	354472	34	0	0
T3	273756	50	0	0
T4	21590	6	0	0
T5	2255	3	0	0
T9	0	14	0	0
T10	0	41	0	0
T16	7146	11	0	0
T17	1943	0	0	0
T18	1101	0	0	0
T19	2964	0	0	0
T20	115706	0	0	0
T26	0	2	0	0
T27	0	2	0	0
T113	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T27
1	0	Covered	T4,T5,T16
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	426476703	3612	0	0
CgEnOn_A	426476703	3609	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426476703	3612	0	0
T1	115410	0	0	0
T2	354472	30	0	0
T3	273756	53	0	0
T4	21590	9	0	0
T5	2255	4	0	0
T9	0	16	0	0
T10	0	43	0	0
T16	7146	11	0	0
T17	1943	0	0	0
T18	1101	0	0	0
T19	2964	0	0	0
T20	115706	0	0	0
T26	0	5	0	0
T27	0	2	0	0
T113	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426476703	3609	0	0
T1	115410	0	0	0
T2	354472	30	0	0
T3	273756	53	0	0
T4	21590	9	0	0
T5	2255	4	0	0
T9	0	16	0	0
T10	0	43	0	0
T16	7146	11	0	0
T17	1943	0	0	0
T18	1101	0	0	0
T19	2964	0	0	0
T20	115706	0	0	0
T26	0	5	0	0
T27	0	2	0	0
T113	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T27
1	0	Covered	T4,T5,T16
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	426476703	3699	0	0
CgEnOn_A	426476703	3696	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426476703	3699	0	0
T1	115410	0	0	0
T2	354472	37	0	0
T3	273756	51	0	0
T4	21590	7	0	0
T5	2255	4	0	0
T9	0	22	0	0
T10	0	38	0	0
T16	7146	10	0	0
T17	1943	0	0	0
T18	1101	0	0	0
T19	2964	0	0	0
T20	115706	0	0	0
T26	0	5	0	0
T27	0	2	0	0
T113	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426476703	3696	0	0
T1	115410	0	0	0
T2	354472	37	0	0
T3	273756	51	0	0
T4	21590	7	0	0
T5	2255	4	0	0
T9	0	22	0	0
T10	0	38	0	0
T16	7146	10	0	0
T17	1943	0	0	0
T18	1101	0	0	0
T19	2964	0	0	0
T20	115706	0	0	0
T26	0	5	0	0
T27	0	2	0	0
T113	0	1	0	0