Unified Coverage Report :: Group :: dv_base_reg_pkg::mubi_cov#(4,32'h00000006,32'h00000009)::mubi_cg

Group : dv_base_reg_pkg::mubi_cov#(4,32'h00000006,32'h00000009)::mubi_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	93.75	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv

16 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_status.ack	0.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_ctrl.hi_speed_sel	100.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_ctrl.sel	100.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_div2_meas_ctrl_en.en	100.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_div4_meas_ctrl_en.en	100.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_meas_ctrl_en.en	100.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.jitter_enable.val	100.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.main_meas_ctrl_en.en	100.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.usb_meas_ctrl_en.en	100.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_tb.dut.u_all_clk_byp_ack_mubi_cov_if	100.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_tb.dut.u_div_step_down_req_mubi_cov_if	100.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_0_mubi_cov_if	100.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_1_mubi_cov_if	100.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_2_mubi_cov_if	100.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_3_mubi_cov_if	100.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_tb.dut.u_io_clk_byp_ack_mubi_cov_if	100.00	1	100	1	64	64

---

Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_status.ack

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_status.ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	6	0	0.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_status.ack

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	6	0	0.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_ctrl.hi_speed_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_ctrl.hi_speed_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_ctrl.hi_speed_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_ctrl.sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_ctrl.sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_ctrl.sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_div2_meas_ctrl_en.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_div2_meas_ctrl_en.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_div2_meas_ctrl_en.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_div4_meas_ctrl_en.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_div4_meas_ctrl_en.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_div4_meas_ctrl_en.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_meas_ctrl_en.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_meas_ctrl_en.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_meas_ctrl_en.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.jitter_enable.val

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.jitter_enable.val

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.jitter_enable.val

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.main_meas_ctrl_en.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.main_meas_ctrl_en.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.main_meas_ctrl_en.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.usb_meas_ctrl_en.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.usb_meas_ctrl_en.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.usb_meas_ctrl_en.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_all_clk_byp_ack_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_all_clk_byp_ack_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_all_clk_byp_ack_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_div_step_down_req_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_div_step_down_req_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_div_step_down_req_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_0_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_0_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_0_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_1_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_1_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_1_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_2_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_2_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_2_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_3_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_3_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_3_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_io_clk_byp_ack_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_io_clk_byp_ack_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_io_clk_byp_ack_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	6	0	0.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
others[0]	0	1	1
others[1]	0	1	1
others[2]	0	1	1
others[3]	0	1	1
false	0	1	1
true	0	1	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	195	1			T5	2		T6	1		T32	2
others[1]	163	1			T5	1		T6	1		T32	1
others[2]	3725	1			T5	17		T6	20		T16	19
others[3]	252	1			T6	1		T16	5		T32	2
false	854	1			T5	4		T6	3		T16	2
true	2378	1			T5	8		T6	10		T4	15

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	92	1			T35	1		T122	1		T143	1
others[1]	72	1			T6	1		T144	1		T145	2
others[2]	3646	1			T5	17		T6	19		T16	18
others[3]	157	1			T16	2		T121	1		T122	1
false	524	1			T5	4		T6	2		T16	3
true	3076	1			T5	11		T6	14		T4	15

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	521	1			T5	1		T4	5		T11	2
others[1]	578	1			T5	7		T4	1		T10	1
others[2]	563	1			T5	5		T4	1		T10	2
others[3]	888	1			T5	2		T4	3		T11	2
false	3629	1			T5	20		T4	18		T10	9
true	815	1			T5	5		T4	2		T10	6

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	551	1			T5	4		T4	2		T10	3
others[1]	574	1			T5	4		T4	2		T10	2
others[2]	528	1			T5	4		T4	1		T10	3
others[3]	859	1			T5	4		T4	4		T10	1
false	3612	1			T5	20		T4	18		T10	9
true	870	1			T5	4		T4	3		T11	2

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	520	1			T5	5		T4	2		T10	1
others[1]	523	1			T5	4		T4	2		T10	2
others[2]	524	1			T5	2		T4	3		T10	1
others[3]	931	1			T5	3		T4	2		T11	2
false	3622	1			T5	20		T4	19		T10	9
true	874	1			T5	6		T4	2		T10	5

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	2641	1			T146	19		T147	19		T148	38
others[1]	417	1			T146	3		T147	3		T148	6
others[2]	417	1			T146	3		T147	3		T148	6
others[3]	695	1			T146	5		T147	5		T148	10
false	139	1			T146	1		T147	1		T148	2
true	139	1			T146	1		T147	1		T148	2

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	594	1			T5	4		T4	2		T10	4
others[1]	526	1			T5	3		T4	3		T11	2
others[2]	528	1			T5	6		T149	1		T124	2
others[3]	882	1			T5	5		T4	1		T10	2
false	3605	1			T5	20		T4	19		T10	9
true	859	1			T5	2		T4	5		T10	3

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	531	1			T5	2		T4	3		T10	4
others[1]	530	1			T5	3		T4	1		T10	2
others[2]	501	1			T5	4		T4	1		T11	2
others[3]	914	1			T5	7		T4	4		T10	1
false	3616	1			T5	20		T4	20		T10	9
true	902	1			T5	4		T4	1		T10	2

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	1460	1			T5	1		T1	41		T6	4
others[1]	1506	1			T5	3		T1	32		T6	5
others[2]	1539	1			T5	4		T1	37		T6	5
others[3]	2527	1			T5	4		T1	76		T6	3
false	5452	1			T5	11		T1	53		T6	2
true	4060	1			T5	8		T1	114		T6	7

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	1983	1			T5	5		T1	61		T6	3
others[1]	1985	1			T5	6		T1	44		T6	2
others[2]	1828	1			T1	51		T6	3		T2	13
others[3]	3192	1			T5	8		T1	59		T6	7
false	6066	1			T5	10		T1	64		T6	2
true	6657	1			T5	14		T1	170		T6	7

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	764	1			T1	15		T2	15		T3	15
others[1]	116	1			T34	4		T150	5		T151	3
others[2]	98	1			T34	4		T85	2		T150	4
others[3]	138	1			T34	7		T150	5		T151	6
false	10819	1			T5	32		T1	171		T6	4
true	11995	1			T5	38		T1	191		T6	5

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	773	1			T1	15		T2	15		T3	15
others[1]	95	1			T34	2		T85	1		T150	4
others[2]	88	1			T34	4		T150	3		T151	2
others[3]	160	1			T34	5		T150	5		T151	7
false	10858	1			T5	35		T1	170		T6	4
true	12030	1			T5	41		T1	192		T6	4

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	760	1			T1	15		T2	15		T3	15
others[1]	88	1			T34	5		T150	3		T151	2
others[2]	103	1			T34	3		T150	5		T151	2
others[3]	165	1			T34	5		T150	6		T151	8
false	10810	1			T5	32		T1	160		T6	3
true	12007	1			T5	38		T1	182		T6	4

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	769	1			T1	15		T2	15		T3	15
others[1]	104	1			T34	4		T150	3		T151	6
others[2]	97	1			T34	5		T150	2		T151	2
others[3]	146	1			T34	3		T85	1		T150	7
false	10883	1			T5	28		T1	173		T6	3
true	12072	1			T5	34		T1	193		T6	4

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	916	1			T5	2		T1	18		T2	4
others[1]	981	1			T5	2		T1	26		T2	5
others[2]	978	1			T5	3		T1	26		T2	7
others[3]	1567	1			T5	3		T1	41		T2	13
false	5121	1			T5	9		T1	42		T6	1
true	5247	1			T5	13		T1	131		T2	34