Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	609785	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3433150

1

T5

382

T1

87679

T6

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	992347	1			T5	248		T1	24029		T6	18
values[0x0]	1402845	1			T5	318		T1	36193		T6	17
values[0x1]	1647743	1			T5	300		T1	42294		T6	20

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	339415	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3703520

1

T5

485

T1

94386

T6

26

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14975	1			T5	8		T1	455		T2	85
valid_sources[0x01]	15825	1			T5	2		T1	332		T2	132
valid_sources[0x02]	16247	1			T5	3		T1	359		T2	114
valid_sources[0x03]	17109	1			T5	6		T1	432		T2	88
valid_sources[0x04]	16507	1			T5	2		T1	363		T14	1
valid_sources[0x05]	15289	1			T5	3		T1	350		T2	93
valid_sources[0x06]	15251	1			T5	4		T1	493		T14	1
valid_sources[0x07]	15253	1			T5	5		T1	486		T14	1
valid_sources[0x08]	14380	1			T5	5		T1	335		T2	105
valid_sources[0x09]	14501	1			T5	3		T1	380		T2	104
valid_sources[0x0a]	14457	1			T5	2		T1	397		T2	97
valid_sources[0x0b]	14899	1			T5	2		T1	306		T2	103
valid_sources[0x0c]	15482	1			T5	1		T1	413		T2	91
valid_sources[0x0d]	15975	1			T5	3		T1	354		T2	127
valid_sources[0x0e]	14279	1			T1	424		T2	123		T3	359
valid_sources[0x0f]	16412	1			T5	5		T1	378		T6	2
valid_sources[0x10]	14991	1			T5	5		T1	391		T2	89
valid_sources[0x11]	16927	1			T5	7		T1	358		T2	86
valid_sources[0x12]	15345	1			T5	5		T1	347		T14	1
valid_sources[0x13]	15021	1			T5	5		T1	507		T14	2
valid_sources[0x14]	15037	1			T5	2		T1	369		T2	89
valid_sources[0x15]	16700	1			T5	2		T1	433		T14	1
valid_sources[0x16]	16057	1			T5	3		T1	448		T2	96
valid_sources[0x17]	15460	1			T5	5		T1	343		T2	114
valid_sources[0x18]	15831	1			T5	4		T1	447		T2	119
valid_sources[0x19]	16532	1			T5	2		T1	388		T6	7
valid_sources[0x1a]	16463	1			T5	6		T1	371		T14	1
valid_sources[0x1b]	15685	1			T5	3		T1	400		T14	1
valid_sources[0x1c]	15689	1			T1	388		T14	1		T2	80
valid_sources[0x1d]	18030	1			T5	4		T1	461		T2	104
valid_sources[0x1e]	15346	1			T5	6		T1	361		T2	91
valid_sources[0x1f]	15942	1			T5	8		T1	418		T14	1
valid_sources[0x20]	14738	1			T5	4		T1	399		T14	1
valid_sources[0x21]	16096	1			T5	8		T1	432		T2	96
valid_sources[0x22]	16463	1			T5	3		T1	494		T6	3
valid_sources[0x23]	15549	1			T5	6		T1	421		T2	99
valid_sources[0x24]	14633	1			T5	7		T1	349		T6	1
valid_sources[0x25]	17715	1			T5	2		T1	507		T2	119
valid_sources[0x26]	14713	1			T5	6		T1	380		T14	1
valid_sources[0x27]	15391	1			T5	1		T1	418		T14	2
valid_sources[0x28]	14869	1			T5	3		T1	390		T2	107
valid_sources[0x29]	15495	1			T5	1		T1	398		T2	134
valid_sources[0x2a]	15125	1			T5	3		T1	338		T2	126
valid_sources[0x2b]	17351	1			T5	2		T1	442		T2	128
valid_sources[0x2c]	14343	1			T5	5		T1	342		T2	91
valid_sources[0x2d]	15784	1			T5	4		T1	413		T14	2
valid_sources[0x2e]	15036	1			T5	2		T1	382		T2	116
valid_sources[0x2f]	16537	1			T5	3		T1	395		T14	1
valid_sources[0x30]	16140	1			T5	2		T1	421		T2	98
valid_sources[0x31]	15292	1			T5	9		T1	394		T2	104
valid_sources[0x32]	14323	1			T5	4		T1	424		T2	93
valid_sources[0x33]	16199	1			T5	1		T1	408		T14	1
valid_sources[0x34]	17790	1			T5	6		T1	391		T14	1
valid_sources[0x35]	14374	1			T1	501		T2	105		T3	338
valid_sources[0x36]	16603	1			T5	5		T1	461		T14	1
valid_sources[0x37]	15124	1			T5	3		T1	354		T2	94
valid_sources[0x38]	16292	1			T5	2		T1	424		T2	88
valid_sources[0x39]	16357	1			T5	1		T1	398		T2	93
valid_sources[0x3a]	15672	1			T5	1		T1	390		T14	1
valid_sources[0x3b]	14478	1			T5	3		T1	456		T2	114
valid_sources[0x3c]	18206	1			T5	2		T1	369		T14	3
valid_sources[0x3d]	15040	1			T5	2		T1	372		T6	3
valid_sources[0x3e]	17200	1			T5	5		T1	428		T2	94
valid_sources[0x3f]	16314	1			T5	2		T1	443		T14	2
valid_sources[0x40]	15186	1			T5	3		T1	384		T14	1
valid_sources[0x41]	17359	1			T5	3		T1	406		T6	1
valid_sources[0x42]	15850	1			T5	4		T1	367		T2	105
valid_sources[0x43]	14674	1			T5	2		T1	435		T2	104
valid_sources[0x44]	16166	1			T5	2		T1	321		T14	1
valid_sources[0x45]	15999	1			T5	5		T1	400		T14	1
valid_sources[0x46]	15721	1			T5	2		T1	385		T2	100
valid_sources[0x47]	15664	1			T1	350		T2	115		T3	303
valid_sources[0x48]	14447	1			T5	1		T1	424		T2	117
valid_sources[0x49]	14677	1			T5	3		T1	370		T2	83
valid_sources[0x4a]	15425	1			T5	5		T1	380		T2	129
valid_sources[0x4b]	15042	1			T5	3		T1	406		T2	103
valid_sources[0x4c]	14957	1			T5	6		T1	352		T2	85
valid_sources[0x4d]	15661	1			T5	2		T1	304		T2	102
valid_sources[0x4e]	15833	1			T5	4		T1	392		T2	103
valid_sources[0x4f]	16703	1			T5	3		T1	331		T6	2
valid_sources[0x50]	16690	1			T5	2		T1	374		T2	125
valid_sources[0x51]	15853	1			T5	6		T1	459		T2	109
valid_sources[0x52]	16137	1			T5	5		T1	377		T2	112
valid_sources[0x53]	15374	1			T5	2		T1	391		T6	1
valid_sources[0x54]	14780	1			T5	1		T1	396		T6	1
valid_sources[0x55]	14328	1			T5	5		T1	343		T14	1
valid_sources[0x56]	15879	1			T5	6		T1	436		T14	2
valid_sources[0x57]	15628	1			T5	4		T1	415		T2	77
valid_sources[0x58]	15285	1			T5	3		T1	450		T14	2
valid_sources[0x59]	15095	1			T5	3		T1	375		T2	101
valid_sources[0x5a]	14512	1			T5	3		T1	345		T6	3
valid_sources[0x5b]	15042	1			T5	6		T1	411		T14	1
valid_sources[0x5c]	15825	1			T5	5		T1	420		T14	1
valid_sources[0x5d]	15500	1			T5	4		T1	470		T14	1
valid_sources[0x5e]	17288	1			T5	1		T1	514		T6	3
valid_sources[0x5f]	15105	1			T5	3		T1	419		T2	95
valid_sources[0x60]	16624	1			T5	4		T1	389		T2	109
valid_sources[0x61]	15866	1			T5	3		T1	393		T14	1
valid_sources[0x62]	14395	1			T5	6		T1	380		T2	96
valid_sources[0x63]	15729	1			T5	3		T1	394		T2	115
valid_sources[0x64]	15007	1			T5	2		T1	436		T6	3
valid_sources[0x65]	15517	1			T5	3		T1	373		T14	3
valid_sources[0x66]	14860	1			T5	3		T1	452		T14	1
valid_sources[0x67]	15240	1			T5	5		T1	344		T14	1
valid_sources[0x68]	15525	1			T5	2		T1	443		T2	83
valid_sources[0x69]	15493	1			T5	2		T1	390		T2	90
valid_sources[0x6a]	16513	1			T5	8		T1	449		T2	126
valid_sources[0x6b]	15541	1			T5	4		T1	359		T2	122
valid_sources[0x6c]	16409	1			T5	3		T1	375		T2	133
valid_sources[0x6d]	17403	1			T5	2		T1	476		T14	1
valid_sources[0x6e]	16944	1			T5	5		T1	459		T2	108
valid_sources[0x6f]	15548	1			T5	6		T1	436		T2	114
valid_sources[0x70]	14960	1			T5	2		T1	427		T2	108
valid_sources[0x71]	15223	1			T5	4		T1	367		T14	1
valid_sources[0x72]	14637	1			T5	4		T1	426		T2	100
valid_sources[0x73]	15420	1			T5	5		T1	474		T2	76
valid_sources[0x74]	14995	1			T1	434		T2	108		T3	397
valid_sources[0x75]	16484	1			T5	1		T1	433		T2	85
valid_sources[0x76]	14533	1			T5	2		T1	344		T14	2
valid_sources[0x77]	16389	1			T5	1		T1	397		T14	1
valid_sources[0x78]	15466	1			T5	8		T1	494		T2	104
valid_sources[0x79]	16297	1			T5	5		T1	437		T2	102
valid_sources[0x7a]	16525	1			T5	1		T1	366		T2	120
valid_sources[0x7b]	15840	1			T5	4		T1	365		T6	2
valid_sources[0x7c]	16755	1			T5	4		T1	317		T2	81
valid_sources[0x7d]	15813	1			T5	9		T1	503		T2	112
valid_sources[0x7e]	15640	1			T5	2		T1	496		T14	1
valid_sources[0x7f]	14094	1			T5	1		T1	386		T14	1
valid_sources[0x80]	16510	1			T5	1		T1	446		T14	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

865967

1

T5

133

T1

21610

T6

7

values[0x0]

all_enables

biggest_size

1307105

1

T5

166

T1

33700

T6

10

values[0x1]

all_enables

biggest_size

1260078

1

T5

83

T1

32369

T6

1