Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T4
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T4
1	0	Covered	T15,T26,T27
1	1	Covered	T5,T1,T6

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1060038297	14677	0	0
GateOpen_A	1060038297	21729	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060038297	14677	0	0
T1	2342465	325	0	0
T2	1300138	109	0	0
T3	1321435	323	0	0
T4	178676	0	0	0
T5	683906	7	0	0
T6	5768	0	0	0
T7	2407422	89	0	0
T8	0	20	0	0
T9	0	270	0	0
T14	18980	0	0	0
T15	7762	12	0	0
T16	14810	0	0	0
T49	0	19	0	0
T139	0	37	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060038297	21729	0	0
T1	2342465	337	0	0
T2	1300138	117	0	0
T3	1321435	343	0	0
T4	178676	60	0	0
T5	683906	19	0	0
T6	5768	0	0	0
T7	2407422	93	0	0
T8	0	44	0	0
T14	18980	0	0	0
T15	7762	16	0	0
T16	14810	0	0	0
T18	0	4	0	0
T49	0	23	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T4
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T4
1	0	Covered	T15,T26,T27
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	116905695	3497	0	0
GateOpen_A	116905695	5258	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116905695	3497	0	0
T1	431044	78	0	0
T2	721632	27	0	0
T3	729565	74	0	0
T4	13355	0	0	0
T5	75772	2	0	0
T6	642	0	0	0
T7	439411	24	0	0
T8	0	5	0	0
T9	0	66	0	0
T14	2094	0	0	0
T15	846	3	0	0
T16	1722	0	0	0
T49	0	5	0	0
T139	0	9	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116905695	5258	0	0
T1	431044	81	0	0
T2	721632	29	0	0
T3	729565	79	0	0
T4	13355	15	0	0
T5	75772	5	0	0
T6	642	0	0	0
T7	439411	25	0	0
T8	0	11	0	0
T14	2094	0	0	0
T15	846	4	0	0
T16	1722	0	0	0
T18	0	1	0	0
T49	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T4
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T4
1	0	Covered	T15,T26,T27
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	233812246	3731	0	0
GateOpen_A	233812246	5492	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233812246	3731	0	0
T1	862091	76	0	0
T2	144327	29	0	0
T3	145914	76	0	0
T4	26714	0	0	0
T5	151545	2	0	0
T6	1284	0	0	0
T7	878832	22	0	0
T8	0	5	0	0
T9	0	69	0	0
T14	4187	0	0	0
T15	1691	3	0	0
T16	3447	0	0	0
T49	0	5	0	0
T139	0	8	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233812246	5492	0	0
T1	862091	79	0	0
T2	144327	31	0	0
T3	145914	81	0	0
T4	26714	15	0	0
T5	151545	5	0	0
T6	1284	0	0	0
T7	878832	23	0	0
T8	0	11	0	0
T14	4187	0	0	0
T15	1691	4	0	0
T16	3447	0	0	0
T18	0	1	0	0
T49	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T4
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T4
1	0	Covered	T15,T26,T27
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	469059322	3746	0	0
GateOpen_A	469059322	5511	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469059322	3746	0	0
T1	172337	87	0	0
T2	288680	28	0	0
T3	293665	87	0	0
T4	92403	0	0	0
T5	300548	1	0	0
T6	2561	0	0	0
T7	176242	22	0	0
T8	0	5	0	0
T9	0	67	0	0
T14	8466	0	0	0
T15	3489	3	0	0
T16	6427	0	0	0
T49	0	3	0	0
T139	0	10	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469059322	5511	0	0
T1	172337	90	0	0
T2	288680	30	0	0
T3	293665	92	0	0
T4	92403	15	0	0
T5	300548	4	0	0
T6	2561	0	0	0
T7	176242	23	0	0
T8	0	11	0	0
T14	8466	0	0	0
T15	3489	4	0	0
T16	6427	0	0	0
T18	0	1	0	0
T49	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T4
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T4
1	0	Covered	T15,T26,T27
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	240261034	3703	0	0
GateOpen_A	240261034	5468	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240261034	3703	0	0
T1	876993	84	0	0
T2	145499	25	0	0
T3	152291	86	0	0
T4	46204	0	0	0
T5	156041	2	0	0
T6	1281	0	0	0
T7	912937	21	0	0
T8	0	5	0	0
T9	0	68	0	0
T14	4233	0	0	0
T15	1736	3	0	0
T16	3214	0	0	0
T49	0	6	0	0
T139	0	10	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240261034	5468	0	0
T1	876993	87	0	0
T2	145499	27	0	0
T3	152291	91	0	0
T4	46204	15	0	0
T5	156041	5	0	0
T6	1281	0	0	0
T7	912937	22	0	0
T8	0	11	0	0
T14	4233	0	0	0
T15	1736	4	0	0
T16	3214	0	0	0
T18	0	1	0	0
T49	0	7	0	0