Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	791931595	77860	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	791931595	77860	0	0
T1	2224830	1687	0	0
T2	3886480	541	0	0
T3	1557395	2095	0	0
T4	312820	0	0	0
T6	12940	0	0	0
T7	962960	2575	0	0
T8	530265	199	0	0
T9	0	1189	0	0
T10	0	45	0	0
T11	0	212	0	0
T12	0	1353	0	0
T13	0	668	0	0
T14	11905	0	0	0
T15	5010	0	0	0
T16	8365	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	158386319	11449	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158386319	11449	0	0
T1	444966	268	0	0
T2	777296	86	0	0
T3	311479	309	0	0
T4	62564	0	0	0
T6	2588	0	0	0
T7	192592	331	0	0
T8	106053	29	0	0
T9	0	173	0	0
T10	0	7	0	0
T11	0	34	0	0
T12	0	174	0	0
T13	0	108	0	0
T14	2381	0	0	0
T15	1002	0	0	0
T16	1673	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	158386319	11289	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158386319	11289	0	0
T1	444966	267	0	0
T2	777296	84	0	0
T3	311479	261	0	0
T4	62564	0	0	0
T6	2588	0	0	0
T7	192592	375	0	0
T8	106053	29	0	0
T9	0	167	0	0
T10	0	7	0	0
T11	0	34	0	0
T12	0	174	0	0
T13	0	105	0	0
T14	2381	0	0	0
T15	1002	0	0	0
T16	1673	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	158386319	15775	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158386319	15775	0	0
T1	444966	342	0	0
T2	777296	110	0	0
T3	311479	415	0	0
T4	62564	0	0	0
T6	2588	0	0	0
T7	192592	520	0	0
T8	106053	40	0	0
T9	0	237	0	0
T10	0	9	0	0
T11	0	44	0	0
T12	0	275	0	0
T13	0	134	0	0
T14	2381	0	0	0
T15	1002	0	0	0
T16	1673	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	158386319	15587	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158386319	15587	0	0
T1	444966	342	0	0
T2	777296	110	0	0
T3	311479	425	0	0
T4	62564	0	0	0
T6	2588	0	0	0
T7	192592	511	0	0
T8	106053	40	0	0
T9	0	239	0	0
T10	0	9	0	0
T11	0	42	0	0
T12	0	273	0	0
T13	0	135	0	0
T14	2381	0	0	0
T15	1002	0	0	0
T16	1673	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	158386319	23760	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158386319	23760	0	0
T1	444966	468	0	0
T2	777296	151	0	0
T3	311479	685	0	0
T4	62564	0	0	0
T6	2588	0	0	0
T7	192592	838	0	0
T8	106053	61	0	0
T9	0	373	0	0
T10	0	13	0	0
T11	0	58	0	0
T12	0	457	0	0
T13	0	186	0	0
T14	2381	0	0	0
T15	1002	0	0	0
T16	1673	0	0	0