Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Module :
prim_mubi4_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T1,T6 |
1 | Covered | T5,T1,T6 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T1,T6 |
1 | Covered | T5,T1,T6 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T1,T6 |
1 | Covered | T5,T1,T6 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T1,T6 |
1 | Covered | T5,T1,T6 |
Branch Coverage for Module :
prim_mubi4_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Module :
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22540 |
22540 |
0 |
0 |
T1 |
28 |
28 |
0 |
0 |
T2 |
28 |
28 |
0 |
0 |
T3 |
28 |
28 |
0 |
0 |
T4 |
28 |
28 |
0 |
0 |
T5 |
28 |
28 |
0 |
0 |
T6 |
28 |
28 |
0 |
0 |
T7 |
28 |
28 |
0 |
0 |
T14 |
28 |
28 |
0 |
0 |
T15 |
28 |
28 |
0 |
0 |
T16 |
28 |
28 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
10397203 |
10382093 |
0 |
0 |
T2 |
15253024 |
15213332 |
0 |
0 |
T3 |
8820417 |
8707616 |
0 |
0 |
T4 |
2013278 |
284407 |
0 |
0 |
T5 |
4899641 |
4888029 |
0 |
0 |
T6 |
68560 |
65471 |
0 |
0 |
T7 |
7007878 |
6969119 |
0 |
0 |
T14 |
140138 |
138297 |
0 |
0 |
T15 |
57909 |
55338 |
0 |
0 |
T16 |
104912 |
101642 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
950317914 |
937260594 |
0 |
14490 |
T1 |
2669796 |
2664948 |
0 |
18 |
T2 |
4663776 |
4650486 |
0 |
18 |
T3 |
1868874 |
1841154 |
0 |
18 |
T4 |
375384 |
23196 |
0 |
18 |
T5 |
308340 |
307440 |
0 |
18 |
T6 |
15528 |
14772 |
0 |
18 |
T7 |
1155552 |
1146516 |
0 |
18 |
T14 |
14286 |
14064 |
0 |
18 |
T15 |
6012 |
5712 |
0 |
18 |
T16 |
10038 |
9660 |
0 |
18 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
16905 |
T1 |
1796881 |
1793681 |
0 |
21 |
T2 |
3079744 |
3070934 |
0 |
21 |
T3 |
2180895 |
2148313 |
0 |
21 |
T4 |
602555 |
37260 |
0 |
21 |
T5 |
1823652 |
1818392 |
0 |
21 |
T6 |
18404 |
17512 |
0 |
21 |
T7 |
1329394 |
1318912 |
0 |
21 |
T14 |
48499 |
47785 |
0 |
21 |
T15 |
19996 |
18973 |
0 |
21 |
T16 |
36553 |
35218 |
0 |
21 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
196420 |
0 |
0 |
T1 |
1796881 |
4151 |
0 |
0 |
T2 |
3079744 |
1940 |
0 |
0 |
T3 |
2180895 |
4041 |
0 |
0 |
T4 |
602555 |
64 |
0 |
0 |
T5 |
1823652 |
595 |
0 |
0 |
T6 |
18404 |
127 |
0 |
0 |
T7 |
1329394 |
1640 |
0 |
0 |
T8 |
0 |
247 |
0 |
0 |
T9 |
0 |
1205 |
0 |
0 |
T14 |
48499 |
116 |
0 |
0 |
T15 |
19996 |
32 |
0 |
0 |
T16 |
36553 |
205 |
0 |
0 |
T32 |
0 |
90 |
0 |
0 |
T33 |
0 |
6 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
5930526 |
5923436 |
0 |
0 |
T2 |
7509504 |
7491835 |
0 |
0 |
T3 |
4770648 |
4718110 |
0 |
0 |
T4 |
1035339 |
223327 |
0 |
0 |
T5 |
2767649 |
2761963 |
0 |
0 |
T6 |
34628 |
33148 |
0 |
0 |
T7 |
4522932 |
4503665 |
0 |
0 |
T14 |
77353 |
76409 |
0 |
0 |
T15 |
31901 |
30614 |
0 |
0 |
T16 |
58321 |
56725 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T1,T6 |
1 | Covered | T5,T1,T6 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T1,T6 |
1 | Covered | T5,T1,T6 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T1,T6 |
1 | Covered | T5,T1,T6 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T1,T6 |
1 | Covered | T5,T1,T6 |
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469058879 |
464890220 |
0 |
0 |
T1 |
172337 |
172061 |
0 |
0 |
T2 |
288680 |
287833 |
0 |
0 |
T3 |
293665 |
289578 |
0 |
0 |
T4 |
92403 |
5764 |
0 |
0 |
T5 |
300548 |
299606 |
0 |
0 |
T6 |
2560 |
2439 |
0 |
0 |
T7 |
176242 |
174798 |
0 |
0 |
T14 |
8465 |
8344 |
0 |
0 |
T15 |
3488 |
3312 |
0 |
0 |
T16 |
6427 |
6197 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469058879 |
464882921 |
0 |
2415 |
T1 |
172337 |
172061 |
0 |
3 |
T2 |
288680 |
287832 |
0 |
3 |
T3 |
293665 |
289575 |
0 |
3 |
T4 |
92403 |
5716 |
0 |
3 |
T5 |
300548 |
299588 |
0 |
3 |
T6 |
2560 |
2436 |
0 |
3 |
T7 |
176242 |
174796 |
0 |
3 |
T14 |
8465 |
8341 |
0 |
3 |
T15 |
3488 |
3309 |
0 |
3 |
T16 |
6427 |
6194 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469058879 |
27282 |
0 |
0 |
T1 |
172337 |
646 |
0 |
0 |
T2 |
288680 |
169 |
0 |
0 |
T3 |
293665 |
400 |
0 |
0 |
T4 |
92403 |
0 |
0 |
0 |
T5 |
300548 |
52 |
0 |
0 |
T6 |
2560 |
35 |
0 |
0 |
T7 |
176242 |
202 |
0 |
0 |
T8 |
0 |
110 |
0 |
0 |
T9 |
0 |
519 |
0 |
0 |
T14 |
8465 |
0 |
0 |
0 |
T15 |
3488 |
0 |
0 |
0 |
T16 |
6427 |
75 |
0 |
0 |
T32 |
0 |
45 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158386319 |
156217587 |
0 |
0 |
T1 |
444966 |
444161 |
0 |
0 |
T2 |
777296 |
775090 |
0 |
0 |
T3 |
311479 |
306862 |
0 |
0 |
T4 |
62564 |
3914 |
0 |
0 |
T5 |
51390 |
51258 |
0 |
0 |
T6 |
2588 |
2465 |
0 |
0 |
T7 |
192592 |
191088 |
0 |
0 |
T14 |
2381 |
2347 |
0 |
0 |
T15 |
1002 |
955 |
0 |
0 |
T16 |
1673 |
1613 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158386319 |
156217587 |
0 |
0 |
T1 |
444966 |
444161 |
0 |
0 |
T2 |
777296 |
775090 |
0 |
0 |
T3 |
311479 |
306862 |
0 |
0 |
T4 |
62564 |
3914 |
0 |
0 |
T5 |
51390 |
51258 |
0 |
0 |
T6 |
2588 |
2465 |
0 |
0 |
T7 |
192592 |
191088 |
0 |
0 |
T14 |
2381 |
2347 |
0 |
0 |
T15 |
1002 |
955 |
0 |
0 |
T16 |
1673 |
1613 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158386319 |
156217587 |
0 |
0 |
T1 |
444966 |
444161 |
0 |
0 |
T2 |
777296 |
775090 |
0 |
0 |
T3 |
311479 |
306862 |
0 |
0 |
T4 |
62564 |
3914 |
0 |
0 |
T5 |
51390 |
51258 |
0 |
0 |
T6 |
2588 |
2465 |
0 |
0 |
T7 |
192592 |
191088 |
0 |
0 |
T14 |
2381 |
2347 |
0 |
0 |
T15 |
1002 |
955 |
0 |
0 |
T16 |
1673 |
1613 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158386319 |
156217587 |
0 |
0 |
T1 |
444966 |
444161 |
0 |
0 |
T2 |
777296 |
775090 |
0 |
0 |
T3 |
311479 |
306862 |
0 |
0 |
T4 |
62564 |
3914 |
0 |
0 |
T5 |
51390 |
51258 |
0 |
0 |
T6 |
2588 |
2465 |
0 |
0 |
T7 |
192592 |
191088 |
0 |
0 |
T14 |
2381 |
2347 |
0 |
0 |
T15 |
1002 |
955 |
0 |
0 |
T16 |
1673 |
1613 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T1,T6 |
1 | Covered | T5,T1,T2 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T1,T6 |
1 | Covered | T5,T1,T2 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T1,T6 |
1 | Covered | T5,T1,T2 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T1,T6 |
1 | Covered | T5,T1,T2 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T2 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T2 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T2 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T2 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158386319 |
156217587 |
0 |
0 |
T1 |
444966 |
444161 |
0 |
0 |
T2 |
777296 |
775090 |
0 |
0 |
T3 |
311479 |
306862 |
0 |
0 |
T4 |
62564 |
3914 |
0 |
0 |
T5 |
51390 |
51258 |
0 |
0 |
T6 |
2588 |
2465 |
0 |
0 |
T7 |
192592 |
191088 |
0 |
0 |
T14 |
2381 |
2347 |
0 |
0 |
T15 |
1002 |
955 |
0 |
0 |
T16 |
1673 |
1613 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158386319 |
156210099 |
0 |
2415 |
T1 |
444966 |
444158 |
0 |
3 |
T2 |
777296 |
775081 |
0 |
3 |
T3 |
311479 |
306859 |
0 |
3 |
T4 |
62564 |
3866 |
0 |
3 |
T5 |
51390 |
51240 |
0 |
3 |
T6 |
2588 |
2462 |
0 |
3 |
T7 |
192592 |
191086 |
0 |
3 |
T14 |
2381 |
2344 |
0 |
3 |
T15 |
1002 |
952 |
0 |
3 |
T16 |
1673 |
1610 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158386319 |
17343 |
0 |
0 |
T1 |
444966 |
407 |
0 |
0 |
T2 |
777296 |
116 |
0 |
0 |
T3 |
311479 |
254 |
0 |
0 |
T4 |
62564 |
0 |
0 |
0 |
T5 |
51390 |
37 |
0 |
0 |
T6 |
2588 |
0 |
0 |
0 |
T7 |
192592 |
127 |
0 |
0 |
T8 |
0 |
73 |
0 |
0 |
T9 |
0 |
304 |
0 |
0 |
T14 |
2381 |
0 |
0 |
0 |
T15 |
1002 |
0 |
0 |
0 |
T16 |
1673 |
25 |
0 |
0 |
T32 |
0 |
5 |
0 |
0 |
T33 |
0 |
6 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T1,T6 |
1 | Covered | T5,T1,T6 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T1,T6 |
1 | Covered | T5,T1,T6 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T1,T6 |
1 | Covered | T5,T1,T6 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T1,T6 |
1 | Covered | T5,T1,T6 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158386319 |
156217587 |
0 |
0 |
T1 |
444966 |
444161 |
0 |
0 |
T2 |
777296 |
775090 |
0 |
0 |
T3 |
311479 |
306862 |
0 |
0 |
T4 |
62564 |
3914 |
0 |
0 |
T5 |
51390 |
51258 |
0 |
0 |
T6 |
2588 |
2465 |
0 |
0 |
T7 |
192592 |
191088 |
0 |
0 |
T14 |
2381 |
2347 |
0 |
0 |
T15 |
1002 |
955 |
0 |
0 |
T16 |
1673 |
1613 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158386319 |
156210099 |
0 |
2415 |
T1 |
444966 |
444158 |
0 |
3 |
T2 |
777296 |
775081 |
0 |
3 |
T3 |
311479 |
306859 |
0 |
3 |
T4 |
62564 |
3866 |
0 |
3 |
T5 |
51390 |
51240 |
0 |
3 |
T6 |
2588 |
2462 |
0 |
3 |
T7 |
192592 |
191086 |
0 |
3 |
T14 |
2381 |
2344 |
0 |
3 |
T15 |
1002 |
952 |
0 |
3 |
T16 |
1673 |
1610 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158386319 |
19555 |
0 |
0 |
T1 |
444966 |
508 |
0 |
0 |
T2 |
777296 |
125 |
0 |
0 |
T3 |
311479 |
310 |
0 |
0 |
T4 |
62564 |
0 |
0 |
0 |
T5 |
51390 |
38 |
0 |
0 |
T6 |
2588 |
34 |
0 |
0 |
T7 |
192592 |
163 |
0 |
0 |
T8 |
0 |
64 |
0 |
0 |
T9 |
0 |
382 |
0 |
0 |
T14 |
2381 |
0 |
0 |
0 |
T15 |
1002 |
0 |
0 |
0 |
T16 |
1673 |
37 |
0 |
0 |
T32 |
0 |
40 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500802361 |
498602500 |
0 |
0 |
T1 |
183653 |
183471 |
0 |
0 |
T2 |
309118 |
308747 |
0 |
0 |
T3 |
316068 |
313641 |
0 |
0 |
T4 |
96256 |
55644 |
0 |
0 |
T5 |
355081 |
354684 |
0 |
0 |
T6 |
2667 |
2570 |
0 |
0 |
T7 |
191992 |
191366 |
0 |
0 |
T14 |
8818 |
8721 |
0 |
0 |
T15 |
3626 |
3514 |
0 |
0 |
T16 |
6695 |
6583 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500802361 |
498602500 |
0 |
0 |
T1 |
183653 |
183471 |
0 |
0 |
T2 |
309118 |
308747 |
0 |
0 |
T3 |
316068 |
313641 |
0 |
0 |
T4 |
96256 |
55644 |
0 |
0 |
T5 |
355081 |
354684 |
0 |
0 |
T6 |
2667 |
2570 |
0 |
0 |
T7 |
191992 |
191366 |
0 |
0 |
T14 |
8818 |
8721 |
0 |
0 |
T15 |
3626 |
3514 |
0 |
0 |
T16 |
6695 |
6583 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469058879 |
466968675 |
0 |
0 |
T1 |
172337 |
172196 |
0 |
0 |
T2 |
288680 |
288324 |
0 |
0 |
T3 |
293665 |
291661 |
0 |
0 |
T4 |
92403 |
53418 |
0 |
0 |
T5 |
300548 |
300168 |
0 |
0 |
T6 |
2560 |
2466 |
0 |
0 |
T7 |
176242 |
175642 |
0 |
0 |
T14 |
8465 |
8372 |
0 |
0 |
T15 |
3488 |
3381 |
0 |
0 |
T16 |
6427 |
6320 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469058879 |
466968675 |
0 |
0 |
T1 |
172337 |
172196 |
0 |
0 |
T2 |
288680 |
288324 |
0 |
0 |
T3 |
293665 |
291661 |
0 |
0 |
T4 |
92403 |
53418 |
0 |
0 |
T5 |
300548 |
300168 |
0 |
0 |
T6 |
2560 |
2466 |
0 |
0 |
T7 |
176242 |
175642 |
0 |
0 |
T14 |
8465 |
8372 |
0 |
0 |
T15 |
3488 |
3381 |
0 |
0 |
T16 |
6427 |
6320 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
233811823 |
233811823 |
0 |
0 |
T1 |
862091 |
862091 |
0 |
0 |
T2 |
144327 |
144327 |
0 |
0 |
T3 |
145914 |
145914 |
0 |
0 |
T4 |
26714 |
26714 |
0 |
0 |
T5 |
151544 |
151544 |
0 |
0 |
T6 |
1283 |
1283 |
0 |
0 |
T7 |
878831 |
878831 |
0 |
0 |
T14 |
4186 |
4186 |
0 |
0 |
T15 |
1691 |
1691 |
0 |
0 |
T16 |
3446 |
3446 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
233811823 |
233811823 |
0 |
0 |
T1 |
862091 |
862091 |
0 |
0 |
T2 |
144327 |
144327 |
0 |
0 |
T3 |
145914 |
145914 |
0 |
0 |
T4 |
26714 |
26714 |
0 |
0 |
T5 |
151544 |
151544 |
0 |
0 |
T6 |
1283 |
1283 |
0 |
0 |
T7 |
878831 |
878831 |
0 |
0 |
T14 |
4186 |
4186 |
0 |
0 |
T15 |
1691 |
1691 |
0 |
0 |
T16 |
3446 |
3446 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116905306 |
116905306 |
0 |
0 |
T1 |
431044 |
431044 |
0 |
0 |
T2 |
721632 |
721632 |
0 |
0 |
T3 |
729564 |
729564 |
0 |
0 |
T4 |
13355 |
13355 |
0 |
0 |
T5 |
75771 |
75771 |
0 |
0 |
T6 |
642 |
642 |
0 |
0 |
T7 |
439411 |
439411 |
0 |
0 |
T14 |
2093 |
2093 |
0 |
0 |
T15 |
845 |
845 |
0 |
0 |
T16 |
1722 |
1722 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116905306 |
116905306 |
0 |
0 |
T1 |
431044 |
431044 |
0 |
0 |
T2 |
721632 |
721632 |
0 |
0 |
T3 |
729564 |
729564 |
0 |
0 |
T4 |
13355 |
13355 |
0 |
0 |
T5 |
75771 |
75771 |
0 |
0 |
T6 |
642 |
642 |
0 |
0 |
T7 |
439411 |
439411 |
0 |
0 |
T14 |
2093 |
2093 |
0 |
0 |
T15 |
845 |
845 |
0 |
0 |
T16 |
1722 |
1722 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
240260609 |
239208186 |
0 |
0 |
T1 |
876993 |
876360 |
0 |
0 |
T2 |
145499 |
145321 |
0 |
0 |
T3 |
152291 |
151126 |
0 |
0 |
T4 |
46203 |
26708 |
0 |
0 |
T5 |
156041 |
155852 |
0 |
0 |
T6 |
1280 |
1233 |
0 |
0 |
T7 |
912936 |
909935 |
0 |
0 |
T14 |
4233 |
4187 |
0 |
0 |
T15 |
1735 |
1681 |
0 |
0 |
T16 |
3213 |
3160 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
240260609 |
239208186 |
0 |
0 |
T1 |
876993 |
876360 |
0 |
0 |
T2 |
145499 |
145321 |
0 |
0 |
T3 |
152291 |
151126 |
0 |
0 |
T4 |
46203 |
26708 |
0 |
0 |
T5 |
156041 |
155852 |
0 |
0 |
T6 |
1280 |
1233 |
0 |
0 |
T7 |
912936 |
909935 |
0 |
0 |
T14 |
4233 |
4187 |
0 |
0 |
T15 |
1735 |
1681 |
0 |
0 |
T16 |
3213 |
3160 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158386319 |
156217587 |
0 |
0 |
T1 |
444966 |
444161 |
0 |
0 |
T2 |
777296 |
775090 |
0 |
0 |
T3 |
311479 |
306862 |
0 |
0 |
T4 |
62564 |
3914 |
0 |
0 |
T5 |
51390 |
51258 |
0 |
0 |
T6 |
2588 |
2465 |
0 |
0 |
T7 |
192592 |
191088 |
0 |
0 |
T14 |
2381 |
2347 |
0 |
0 |
T15 |
1002 |
955 |
0 |
0 |
T16 |
1673 |
1613 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158386319 |
156210099 |
0 |
2415 |
T1 |
444966 |
444158 |
0 |
3 |
T2 |
777296 |
775081 |
0 |
3 |
T3 |
311479 |
306859 |
0 |
3 |
T4 |
62564 |
3866 |
0 |
3 |
T5 |
51390 |
51240 |
0 |
3 |
T6 |
2588 |
2462 |
0 |
3 |
T7 |
192592 |
191086 |
0 |
3 |
T14 |
2381 |
2344 |
0 |
3 |
T15 |
1002 |
952 |
0 |
3 |
T16 |
1673 |
1610 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158386319 |
156217587 |
0 |
0 |
T1 |
444966 |
444161 |
0 |
0 |
T2 |
777296 |
775090 |
0 |
0 |
T3 |
311479 |
306862 |
0 |
0 |
T4 |
62564 |
3914 |
0 |
0 |
T5 |
51390 |
51258 |
0 |
0 |
T6 |
2588 |
2465 |
0 |
0 |
T7 |
192592 |
191088 |
0 |
0 |
T14 |
2381 |
2347 |
0 |
0 |
T15 |
1002 |
955 |
0 |
0 |
T16 |
1673 |
1613 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158386319 |
156210099 |
0 |
2415 |
T1 |
444966 |
444158 |
0 |
3 |
T2 |
777296 |
775081 |
0 |
3 |
T3 |
311479 |
306859 |
0 |
3 |
T4 |
62564 |
3866 |
0 |
3 |
T5 |
51390 |
51240 |
0 |
3 |
T6 |
2588 |
2462 |
0 |
3 |
T7 |
192592 |
191086 |
0 |
3 |
T14 |
2381 |
2344 |
0 |
3 |
T15 |
1002 |
952 |
0 |
3 |
T16 |
1673 |
1610 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158386319 |
156217587 |
0 |
0 |
T1 |
444966 |
444161 |
0 |
0 |
T2 |
777296 |
775090 |
0 |
0 |
T3 |
311479 |
306862 |
0 |
0 |
T4 |
62564 |
3914 |
0 |
0 |
T5 |
51390 |
51258 |
0 |
0 |
T6 |
2588 |
2465 |
0 |
0 |
T7 |
192592 |
191088 |
0 |
0 |
T14 |
2381 |
2347 |
0 |
0 |
T15 |
1002 |
955 |
0 |
0 |
T16 |
1673 |
1613 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158386319 |
156210099 |
0 |
2415 |
T1 |
444966 |
444158 |
0 |
3 |
T2 |
777296 |
775081 |
0 |
3 |
T3 |
311479 |
306859 |
0 |
3 |
T4 |
62564 |
3866 |
0 |
3 |
T5 |
51390 |
51240 |
0 |
3 |
T6 |
2588 |
2462 |
0 |
3 |
T7 |
192592 |
191086 |
0 |
3 |
T14 |
2381 |
2344 |
0 |
3 |
T15 |
1002 |
952 |
0 |
3 |
T16 |
1673 |
1610 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158386319 |
156217587 |
0 |
0 |
T1 |
444966 |
444161 |
0 |
0 |
T2 |
777296 |
775090 |
0 |
0 |
T3 |
311479 |
306862 |
0 |
0 |
T4 |
62564 |
3914 |
0 |
0 |
T5 |
51390 |
51258 |
0 |
0 |
T6 |
2588 |
2465 |
0 |
0 |
T7 |
192592 |
191088 |
0 |
0 |
T14 |
2381 |
2347 |
0 |
0 |
T15 |
1002 |
955 |
0 |
0 |
T16 |
1673 |
1613 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158386319 |
156210099 |
0 |
2415 |
T1 |
444966 |
444158 |
0 |
3 |
T2 |
777296 |
775081 |
0 |
3 |
T3 |
311479 |
306859 |
0 |
3 |
T4 |
62564 |
3866 |
0 |
3 |
T5 |
51390 |
51240 |
0 |
3 |
T6 |
2588 |
2462 |
0 |
3 |
T7 |
192592 |
191086 |
0 |
3 |
T14 |
2381 |
2344 |
0 |
3 |
T15 |
1002 |
952 |
0 |
3 |
T16 |
1673 |
1610 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158386319 |
156217587 |
0 |
0 |
T1 |
444966 |
444161 |
0 |
0 |
T2 |
777296 |
775090 |
0 |
0 |
T3 |
311479 |
306862 |
0 |
0 |
T4 |
62564 |
3914 |
0 |
0 |
T5 |
51390 |
51258 |
0 |
0 |
T6 |
2588 |
2465 |
0 |
0 |
T7 |
192592 |
191088 |
0 |
0 |
T14 |
2381 |
2347 |
0 |
0 |
T15 |
1002 |
955 |
0 |
0 |
T16 |
1673 |
1613 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158386319 |
156210099 |
0 |
2415 |
T1 |
444966 |
444158 |
0 |
3 |
T2 |
777296 |
775081 |
0 |
3 |
T3 |
311479 |
306859 |
0 |
3 |
T4 |
62564 |
3866 |
0 |
3 |
T5 |
51390 |
51240 |
0 |
3 |
T6 |
2588 |
2462 |
0 |
3 |
T7 |
192592 |
191086 |
0 |
3 |
T14 |
2381 |
2344 |
0 |
3 |
T15 |
1002 |
952 |
0 |
3 |
T16 |
1673 |
1610 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158386319 |
156217587 |
0 |
0 |
T1 |
444966 |
444161 |
0 |
0 |
T2 |
777296 |
775090 |
0 |
0 |
T3 |
311479 |
306862 |
0 |
0 |
T4 |
62564 |
3914 |
0 |
0 |
T5 |
51390 |
51258 |
0 |
0 |
T6 |
2588 |
2465 |
0 |
0 |
T7 |
192592 |
191088 |
0 |
0 |
T14 |
2381 |
2347 |
0 |
0 |
T15 |
1002 |
955 |
0 |
0 |
T16 |
1673 |
1613 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158386319 |
156210099 |
0 |
2415 |
T1 |
444966 |
444158 |
0 |
3 |
T2 |
777296 |
775081 |
0 |
3 |
T3 |
311479 |
306859 |
0 |
3 |
T4 |
62564 |
3866 |
0 |
3 |
T5 |
51390 |
51240 |
0 |
3 |
T6 |
2588 |
2462 |
0 |
3 |
T7 |
192592 |
191086 |
0 |
3 |
T14 |
2381 |
2344 |
0 |
3 |
T15 |
1002 |
952 |
0 |
3 |
T16 |
1673 |
1610 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158386319 |
156217587 |
0 |
0 |
T1 |
444966 |
444161 |
0 |
0 |
T2 |
777296 |
775090 |
0 |
0 |
T3 |
311479 |
306862 |
0 |
0 |
T4 |
62564 |
3914 |
0 |
0 |
T5 |
51390 |
51258 |
0 |
0 |
T6 |
2588 |
2465 |
0 |
0 |
T7 |
192592 |
191088 |
0 |
0 |
T14 |
2381 |
2347 |
0 |
0 |
T15 |
1002 |
955 |
0 |
0 |
T16 |
1673 |
1613 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158386319 |
156217587 |
0 |
0 |
T1 |
444966 |
444161 |
0 |
0 |
T2 |
777296 |
775090 |
0 |
0 |
T3 |
311479 |
306862 |
0 |
0 |
T4 |
62564 |
3914 |
0 |
0 |
T5 |
51390 |
51258 |
0 |
0 |
T6 |
2588 |
2465 |
0 |
0 |
T7 |
192592 |
191088 |
0 |
0 |
T14 |
2381 |
2347 |
0 |
0 |
T15 |
1002 |
955 |
0 |
0 |
T16 |
1673 |
1613 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158386319 |
156217587 |
0 |
0 |
T1 |
444966 |
444161 |
0 |
0 |
T2 |
777296 |
775090 |
0 |
0 |
T3 |
311479 |
306862 |
0 |
0 |
T4 |
62564 |
3914 |
0 |
0 |
T5 |
51390 |
51258 |
0 |
0 |
T6 |
2588 |
2465 |
0 |
0 |
T7 |
192592 |
191088 |
0 |
0 |
T14 |
2381 |
2347 |
0 |
0 |
T15 |
1002 |
955 |
0 |
0 |
T16 |
1673 |
1613 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158386319 |
156217587 |
0 |
0 |
T1 |
444966 |
444161 |
0 |
0 |
T2 |
777296 |
775090 |
0 |
0 |
T3 |
311479 |
306862 |
0 |
0 |
T4 |
62564 |
3914 |
0 |
0 |
T5 |
51390 |
51258 |
0 |
0 |
T6 |
2588 |
2465 |
0 |
0 |
T7 |
192592 |
191088 |
0 |
0 |
T14 |
2381 |
2347 |
0 |
0 |
T15 |
1002 |
955 |
0 |
0 |
T16 |
1673 |
1613 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158386319 |
156217587 |
0 |
0 |
T1 |
444966 |
444161 |
0 |
0 |
T2 |
777296 |
775090 |
0 |
0 |
T3 |
311479 |
306862 |
0 |
0 |
T4 |
62564 |
3914 |
0 |
0 |
T5 |
51390 |
51258 |
0 |
0 |
T6 |
2588 |
2465 |
0 |
0 |
T7 |
192592 |
191088 |
0 |
0 |
T14 |
2381 |
2347 |
0 |
0 |
T15 |
1002 |
955 |
0 |
0 |
T16 |
1673 |
1613 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158386319 |
156217587 |
0 |
0 |
T1 |
444966 |
444161 |
0 |
0 |
T2 |
777296 |
775090 |
0 |
0 |
T3 |
311479 |
306862 |
0 |
0 |
T4 |
62564 |
3914 |
0 |
0 |
T5 |
51390 |
51258 |
0 |
0 |
T6 |
2588 |
2465 |
0 |
0 |
T7 |
192592 |
191088 |
0 |
0 |
T14 |
2381 |
2347 |
0 |
0 |
T15 |
1002 |
955 |
0 |
0 |
T16 |
1673 |
1613 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158386319 |
156217587 |
0 |
0 |
T1 |
444966 |
444161 |
0 |
0 |
T2 |
777296 |
775090 |
0 |
0 |
T3 |
311479 |
306862 |
0 |
0 |
T4 |
62564 |
3914 |
0 |
0 |
T5 |
51390 |
51258 |
0 |
0 |
T6 |
2588 |
2465 |
0 |
0 |
T7 |
192592 |
191088 |
0 |
0 |
T14 |
2381 |
2347 |
0 |
0 |
T15 |
1002 |
955 |
0 |
0 |
T16 |
1673 |
1613 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158386319 |
156217587 |
0 |
0 |
T1 |
444966 |
444161 |
0 |
0 |
T2 |
777296 |
775090 |
0 |
0 |
T3 |
311479 |
306862 |
0 |
0 |
T4 |
62564 |
3914 |
0 |
0 |
T5 |
51390 |
51258 |
0 |
0 |
T6 |
2588 |
2465 |
0 |
0 |
T7 |
192592 |
191088 |
0 |
0 |
T14 |
2381 |
2347 |
0 |
0 |
T15 |
1002 |
955 |
0 |
0 |
T16 |
1673 |
1613 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T1,T6 |
1 | Covered | T5,T1,T6 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T1,T6 |
1 | Covered | T5,T1,T6 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T1,T6 |
1 | Covered | T5,T1,T6 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T1,T6 |
1 | Covered | T5,T1,T6 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500802361 |
496417456 |
0 |
0 |
T1 |
183653 |
183327 |
0 |
0 |
T2 |
309118 |
308236 |
0 |
0 |
T3 |
316068 |
311258 |
0 |
0 |
T4 |
96256 |
6001 |
0 |
0 |
T5 |
355081 |
354099 |
0 |
0 |
T6 |
2667 |
2541 |
0 |
0 |
T7 |
191992 |
190488 |
0 |
0 |
T14 |
8818 |
8692 |
0 |
0 |
T15 |
3626 |
3443 |
0 |
0 |
T16 |
6695 |
6454 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500802361 |
496410118 |
0 |
2415 |
T1 |
183653 |
183326 |
0 |
3 |
T2 |
309118 |
308235 |
0 |
3 |
T3 |
316068 |
311255 |
0 |
3 |
T4 |
96256 |
5953 |
0 |
3 |
T5 |
355081 |
354081 |
0 |
3 |
T6 |
2667 |
2538 |
0 |
3 |
T7 |
191992 |
190486 |
0 |
3 |
T14 |
8818 |
8689 |
0 |
3 |
T15 |
3626 |
3440 |
0 |
3 |
T16 |
6695 |
6451 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500802361 |
32956 |
0 |
0 |
T1 |
183653 |
647 |
0 |
0 |
T2 |
309118 |
353 |
0 |
0 |
T3 |
316068 |
700 |
0 |
0 |
T4 |
96256 |
16 |
0 |
0 |
T5 |
355081 |
119 |
0 |
0 |
T6 |
2667 |
17 |
0 |
0 |
T7 |
191992 |
280 |
0 |
0 |
T14 |
8818 |
36 |
0 |
0 |
T15 |
3626 |
13 |
0 |
0 |
T16 |
6695 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500802361 |
496417456 |
0 |
0 |
T1 |
183653 |
183327 |
0 |
0 |
T2 |
309118 |
308236 |
0 |
0 |
T3 |
316068 |
311258 |
0 |
0 |
T4 |
96256 |
6001 |
0 |
0 |
T5 |
355081 |
354099 |
0 |
0 |
T6 |
2667 |
2541 |
0 |
0 |
T7 |
191992 |
190488 |
0 |
0 |
T14 |
8818 |
8692 |
0 |
0 |
T15 |
3626 |
3443 |
0 |
0 |
T16 |
6695 |
6454 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500802361 |
496417456 |
0 |
0 |
T1 |
183653 |
183327 |
0 |
0 |
T2 |
309118 |
308236 |
0 |
0 |
T3 |
316068 |
311258 |
0 |
0 |
T4 |
96256 |
6001 |
0 |
0 |
T5 |
355081 |
354099 |
0 |
0 |
T6 |
2667 |
2541 |
0 |
0 |
T7 |
191992 |
190488 |
0 |
0 |
T14 |
8818 |
8692 |
0 |
0 |
T15 |
3626 |
3443 |
0 |
0 |
T16 |
6695 |
6454 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T1,T6 |
1 | Covered | T5,T1,T6 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T1,T6 |
1 | Covered | T5,T1,T6 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T1,T6 |
1 | Covered | T5,T1,T6 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T1,T6 |
1 | Covered | T5,T1,T6 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500802361 |
496417456 |
0 |
0 |
T1 |
183653 |
183327 |
0 |
0 |
T2 |
309118 |
308236 |
0 |
0 |
T3 |
316068 |
311258 |
0 |
0 |
T4 |
96256 |
6001 |
0 |
0 |
T5 |
355081 |
354099 |
0 |
0 |
T6 |
2667 |
2541 |
0 |
0 |
T7 |
191992 |
190488 |
0 |
0 |
T14 |
8818 |
8692 |
0 |
0 |
T15 |
3626 |
3443 |
0 |
0 |
T16 |
6695 |
6454 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500802361 |
496410118 |
0 |
2415 |
T1 |
183653 |
183326 |
0 |
3 |
T2 |
309118 |
308235 |
0 |
3 |
T3 |
316068 |
311255 |
0 |
3 |
T4 |
96256 |
5953 |
0 |
3 |
T5 |
355081 |
354081 |
0 |
3 |
T6 |
2667 |
2538 |
0 |
3 |
T7 |
191992 |
190486 |
0 |
3 |
T14 |
8818 |
8689 |
0 |
3 |
T15 |
3626 |
3440 |
0 |
3 |
T16 |
6695 |
6451 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500802361 |
33102 |
0 |
0 |
T1 |
183653 |
660 |
0 |
0 |
T2 |
309118 |
416 |
0 |
0 |
T3 |
316068 |
853 |
0 |
0 |
T4 |
96256 |
16 |
0 |
0 |
T5 |
355081 |
129 |
0 |
0 |
T6 |
2667 |
15 |
0 |
0 |
T7 |
191992 |
266 |
0 |
0 |
T14 |
8818 |
30 |
0 |
0 |
T15 |
3626 |
5 |
0 |
0 |
T16 |
6695 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500802361 |
496417456 |
0 |
0 |
T1 |
183653 |
183327 |
0 |
0 |
T2 |
309118 |
308236 |
0 |
0 |
T3 |
316068 |
311258 |
0 |
0 |
T4 |
96256 |
6001 |
0 |
0 |
T5 |
355081 |
354099 |
0 |
0 |
T6 |
2667 |
2541 |
0 |
0 |
T7 |
191992 |
190488 |
0 |
0 |
T14 |
8818 |
8692 |
0 |
0 |
T15 |
3626 |
3443 |
0 |
0 |
T16 |
6695 |
6454 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500802361 |
496417456 |
0 |
0 |
T1 |
183653 |
183327 |
0 |
0 |
T2 |
309118 |
308236 |
0 |
0 |
T3 |
316068 |
311258 |
0 |
0 |
T4 |
96256 |
6001 |
0 |
0 |
T5 |
355081 |
354099 |
0 |
0 |
T6 |
2667 |
2541 |
0 |
0 |
T7 |
191992 |
190488 |
0 |
0 |
T14 |
8818 |
8692 |
0 |
0 |
T15 |
3626 |
3443 |
0 |
0 |
T16 |
6695 |
6454 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T1,T6 |
1 | Covered | T5,T1,T6 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T1,T6 |
1 | Covered | T5,T1,T6 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T1,T6 |
1 | Covered | T5,T1,T6 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T1,T6 |
1 | Covered | T5,T1,T6 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500802361 |
496417456 |
0 |
0 |
T1 |
183653 |
183327 |
0 |
0 |
T2 |
309118 |
308236 |
0 |
0 |
T3 |
316068 |
311258 |
0 |
0 |
T4 |
96256 |
6001 |
0 |
0 |
T5 |
355081 |
354099 |
0 |
0 |
T6 |
2667 |
2541 |
0 |
0 |
T7 |
191992 |
190488 |
0 |
0 |
T14 |
8818 |
8692 |
0 |
0 |
T15 |
3626 |
3443 |
0 |
0 |
T16 |
6695 |
6454 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500802361 |
496410118 |
0 |
2415 |
T1 |
183653 |
183326 |
0 |
3 |
T2 |
309118 |
308235 |
0 |
3 |
T3 |
316068 |
311255 |
0 |
3 |
T4 |
96256 |
5953 |
0 |
3 |
T5 |
355081 |
354081 |
0 |
3 |
T6 |
2667 |
2538 |
0 |
3 |
T7 |
191992 |
190486 |
0 |
3 |
T14 |
8818 |
8689 |
0 |
3 |
T15 |
3626 |
3440 |
0 |
3 |
T16 |
6695 |
6451 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500802361 |
32978 |
0 |
0 |
T1 |
183653 |
620 |
0 |
0 |
T2 |
309118 |
388 |
0 |
0 |
T3 |
316068 |
743 |
0 |
0 |
T4 |
96256 |
16 |
0 |
0 |
T5 |
355081 |
117 |
0 |
0 |
T6 |
2667 |
13 |
0 |
0 |
T7 |
191992 |
301 |
0 |
0 |
T14 |
8818 |
14 |
0 |
0 |
T15 |
3626 |
5 |
0 |
0 |
T16 |
6695 |
16 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500802361 |
496417456 |
0 |
0 |
T1 |
183653 |
183327 |
0 |
0 |
T2 |
309118 |
308236 |
0 |
0 |
T3 |
316068 |
311258 |
0 |
0 |
T4 |
96256 |
6001 |
0 |
0 |
T5 |
355081 |
354099 |
0 |
0 |
T6 |
2667 |
2541 |
0 |
0 |
T7 |
191992 |
190488 |
0 |
0 |
T14 |
8818 |
8692 |
0 |
0 |
T15 |
3626 |
3443 |
0 |
0 |
T16 |
6695 |
6454 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500802361 |
496417456 |
0 |
0 |
T1 |
183653 |
183327 |
0 |
0 |
T2 |
309118 |
308236 |
0 |
0 |
T3 |
316068 |
311258 |
0 |
0 |
T4 |
96256 |
6001 |
0 |
0 |
T5 |
355081 |
354099 |
0 |
0 |
T6 |
2667 |
2541 |
0 |
0 |
T7 |
191992 |
190488 |
0 |
0 |
T14 |
8818 |
8692 |
0 |
0 |
T15 |
3626 |
3443 |
0 |
0 |
T16 |
6695 |
6454 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T1,T6 |
1 | Covered | T5,T1,T6 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T1,T6 |
1 | Covered | T5,T1,T6 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T1,T6 |
1 | Covered | T5,T1,T6 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T1,T6 |
1 | Covered | T5,T1,T6 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500802361 |
496417456 |
0 |
0 |
T1 |
183653 |
183327 |
0 |
0 |
T2 |
309118 |
308236 |
0 |
0 |
T3 |
316068 |
311258 |
0 |
0 |
T4 |
96256 |
6001 |
0 |
0 |
T5 |
355081 |
354099 |
0 |
0 |
T6 |
2667 |
2541 |
0 |
0 |
T7 |
191992 |
190488 |
0 |
0 |
T14 |
8818 |
8692 |
0 |
0 |
T15 |
3626 |
3443 |
0 |
0 |
T16 |
6695 |
6454 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500802361 |
496410118 |
0 |
2415 |
T1 |
183653 |
183326 |
0 |
3 |
T2 |
309118 |
308235 |
0 |
3 |
T3 |
316068 |
311255 |
0 |
3 |
T4 |
96256 |
5953 |
0 |
3 |
T5 |
355081 |
354081 |
0 |
3 |
T6 |
2667 |
2538 |
0 |
3 |
T7 |
191992 |
190486 |
0 |
3 |
T14 |
8818 |
8689 |
0 |
3 |
T15 |
3626 |
3440 |
0 |
3 |
T16 |
6695 |
6451 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500802361 |
33204 |
0 |
0 |
T1 |
183653 |
663 |
0 |
0 |
T2 |
309118 |
373 |
0 |
0 |
T3 |
316068 |
781 |
0 |
0 |
T4 |
96256 |
16 |
0 |
0 |
T5 |
355081 |
103 |
0 |
0 |
T6 |
2667 |
13 |
0 |
0 |
T7 |
191992 |
301 |
0 |
0 |
T14 |
8818 |
36 |
0 |
0 |
T15 |
3626 |
9 |
0 |
0 |
T16 |
6695 |
22 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500802361 |
496417456 |
0 |
0 |
T1 |
183653 |
183327 |
0 |
0 |
T2 |
309118 |
308236 |
0 |
0 |
T3 |
316068 |
311258 |
0 |
0 |
T4 |
96256 |
6001 |
0 |
0 |
T5 |
355081 |
354099 |
0 |
0 |
T6 |
2667 |
2541 |
0 |
0 |
T7 |
191992 |
190488 |
0 |
0 |
T14 |
8818 |
8692 |
0 |
0 |
T15 |
3626 |
3443 |
0 |
0 |
T16 |
6695 |
6454 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500802361 |
496417456 |
0 |
0 |
T1 |
183653 |
183327 |
0 |
0 |
T2 |
309118 |
308236 |
0 |
0 |
T3 |
316068 |
311258 |
0 |
0 |
T4 |
96256 |
6001 |
0 |
0 |
T5 |
355081 |
354099 |
0 |
0 |
T6 |
2667 |
2541 |
0 |
0 |
T7 |
191992 |
190488 |
0 |
0 |
T14 |
8818 |
8692 |
0 |
0 |
T15 |
3626 |
3443 |
0 |
0 |
T16 |
6695 |
6454 |
0 |
0 |