Unified Coverage Report :: Module :: prim_count

Module : prim_count

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_clk_main_aes_trans.u_idle_cnt	100.00			100.00
tb.dut.u_clk_main_hmac_trans.u_idle_cnt	100.00			100.00
tb.dut.u_clk_main_kmac_trans.u_idle_cnt	100.00			100.00
tb.dut.u_clk_main_otbn_trans.u_idle_cnt	100.00			100.00

---

Module Instance : tb.dut.u_clk_main_aes_trans.u_idle_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_aes_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_clk_main_hmac_trans.u_idle_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_hmac_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_clk_main_kmac_trans.u_idle_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_kmac_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_clk_main_otbn_trans.u_idle_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_otbn_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	26	26	100.00
Total Bits 0->1	13	13	100.00
Total Bits 1->0	13	13	100.00

Ports	7	7	100.00
Port Bits	26	26	100.00
Port Bits 0->1	13	13	100.00
Port Bits 1->0	13	13	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T5,T1,T6	Yes	T5,T1,T6	INPUT
rst_ni	Yes	Yes	T5,T1,T4	Yes	T5,T1,T6	INPUT
clr_i	Yes	Yes	T5,T1,T6	Yes	T5,T1,T6	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T5,T1,T6	Yes	T5,T1,T6	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[3:0]	Yes	Yes	T5,T1,T6	Yes	T5,T1,T6	OUTPUT
cnt_after_commit_o[3:0]	Yes	Yes	T5,T1,T6	Yes	T5,T1,T6	OUTPUT
err_o	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT

Toggle Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_cnt

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	26	26	100.00
Total Bits 0->1	13	13	100.00
Total Bits 1->0	13	13	100.00

Ports	7	7	100.00
Port Bits	26	26	100.00
Port Bits 0->1	13	13	100.00
Port Bits 1->0	13	13	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T5,T1,T6	Yes	T5,T1,T6	INPUT
rst_ni	Yes	Yes	T5,T1,T4	Yes	T5,T1,T6	INPUT
clr_i	Yes	Yes	T5,T1,T6	Yes	T5,T1,T6	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T5,T1,T6	Yes	T5,T1,T6	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[3:0]	Yes	Yes	T5,T1,T6	Yes	T5,T1,T6	OUTPUT
cnt_after_commit_o[3:0]	Yes	Yes	T5,T1,T6	Yes	T5,T1,T6	OUTPUT
err_o	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT

Toggle Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_cnt

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	26	26	100.00
Total Bits 0->1	13	13	100.00
Total Bits 1->0	13	13	100.00

Ports	7	7	100.00
Port Bits	26	26	100.00
Port Bits 0->1	13	13	100.00
Port Bits 1->0	13	13	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T5,T1,T6	Yes	T5,T1,T6	INPUT
rst_ni	Yes	Yes	T5,T1,T4	Yes	T5,T1,T6	INPUT
clr_i	Yes	Yes	T5,T1,T6	Yes	T5,T1,T6	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T5,T1,T6	Yes	T5,T1,T6	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[3:0]	Yes	Yes	T5,T1,T6	Yes	T5,T1,T6	OUTPUT
cnt_after_commit_o[3:0]	Yes	Yes	T5,T1,T6	Yes	T5,T1,T6	OUTPUT
err_o	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT

Toggle Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_cnt

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	26	26	100.00
Total Bits 0->1	13	13	100.00
Total Bits 1->0	13	13	100.00

Ports	7	7	100.00
Port Bits	26	26	100.00
Port Bits 0->1	13	13	100.00
Port Bits 1->0	13	13	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T5,T1,T6	Yes	T5,T1,T6	INPUT
rst_ni	Yes	Yes	T5,T1,T4	Yes	T5,T1,T6	INPUT
clr_i	Yes	Yes	T5,T1,T6	Yes	T5,T1,T6	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T5,T1,T6	Yes	T5,T1,T6	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[3:0]	Yes	Yes	T5,T1,T6	Yes	T5,T1,T6	OUTPUT
cnt_after_commit_o[3:0]	Yes	Yes	T5,T1,T6	Yes	T5,T1,T6	OUTPUT
err_o	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT

Toggle Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_cnt

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	26	26	100.00
Total Bits 0->1	13	13	100.00
Total Bits 1->0	13	13	100.00

Ports	7	7	100.00
Port Bits	26	26	100.00
Port Bits 0->1	13	13	100.00
Port Bits 1->0	13	13	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T5,T1,T6	Yes	T5,T1,T6	INPUT
rst_ni	Yes	Yes	T5,T1,T4	Yes	T5,T1,T6	INPUT
clr_i	Yes	Yes	T5,T1,T6	Yes	T5,T1,T6	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T5,T1,T6	Yes	T5,T1,T6	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[3:0]	Yes	Yes	T5,T1,T6	Yes	T5,T1,T6	OUTPUT
cnt_after_commit_o[3:0]	Yes	Yes	T5,T1,T6	Yes	T5,T1,T6	OUTPUT
err_o	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT