Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T5,T1,T4

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	158386319	156083569	0	0
AllClkBypReqTrue_A	158386319	131585	0	0
IoClkBypReqFalse_A	158386319	156000722	0	2415
IoClkBypReqTrue_A	158386319	209566	0	0
LcClkBypAckFalse_A	158386319	156089218	0	0
LcClkBypAckTrue_A	158386319	125936	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158386319	156083569	0	0
T1	444966	443659	0	0
T2	777296	774436	0	0
T3	311479	306701	0	0
T4	62564	3898	0	0
T5	51390	50941	0	0
T6	2588	2347	0	0
T7	192592	190966	0	0
T14	2381	2346	0	0
T15	1002	954	0	0
T16	1673	1465	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158386319	131585	0	0
T1	444966	5010	0	0
T2	777296	651	0	0
T3	311479	1599	0	0
T4	62564	0	0	0
T5	51390	311	0	0
T6	2588	117	0	0
T7	192592	1209	0	0
T8	0	298	0	0
T9	0	3029	0	0
T14	2381	0	0	0
T15	1002	0	0	0
T16	1673	147	0	0
T32	0	244	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158386319	156000722	0	2415
T1	444966	443464	0	3
T2	777296	774100	0	3
T3	311479	306629	0	3
T4	62564	3866	0	3
T5	51390	50693	0	3
T6	2588	2462	0	3
T7	192592	190924	0	3
T14	2381	2344	0	3
T15	1002	952	0	3
T16	1673	1391	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158386319	209566	0	0
T1	444966	6935	0	0
T2	777296	981	0	0
T3	311479	2302	0	0
T4	62564	0	0	0
T5	51390	547	0	0
T6	2588	0	0	0
T7	192592	1618	0	0
T8	0	644	0	0
T9	0	4301	0	0
T14	2381	0	0	0
T15	1002	0	0	0
T16	1673	219	0	0
T32	0	70	0	0
T33	0	71	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158386319	156089218	0	0
T1	444966	443743	0	0
T2	777296	774535	0	0
T3	311479	306727	0	0
T4	62564	3898	0	0
T5	51390	50875	0	0
T6	2588	2464	0	0
T7	192592	190979	0	0
T14	2381	2346	0	0
T15	1002	954	0	0
T16	1673	1511	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158386319	125936	0	0
T1	444966	4165	0	0
T2	777296	552	0	0
T3	311479	1344	0	0
T4	62564	0	0	0
T5	51390	377	0	0
T6	2588	0	0	0
T7	192592	1079	0	0
T8	0	392	0	0
T9	0	2737	0	0
T14	2381	0	0	0
T15	1002	0	0	0
T16	1673	101	0	0
T32	0	64	0	0
T33	0	64	0	0