Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2003211320	15973	0	0
TransStop_A	2003211320	8214	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2003211320	15973	0	0
T1	734612	295	0	0
T2	1236472	303	0	0
T3	1264272	472	0	0
T4	385028	0	0	0
T5	1420328	109	0	0
T6	10668	0	0	0
T7	767968	189	0	0
T8	0	75	0	0
T9	0	271	0	0
T14	35272	32	0	0
T15	14504	0	0	0
T16	26784	0	0	0
T34	0	23	0	0
T85	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2003211320	8214	0	0
T1	734612	140	0	0
T2	1236472	148	0	0
T3	1264272	229	0	0
T4	385028	0	0	0
T5	1420328	58	0	0
T6	10668	0	0	0
T7	767968	106	0	0
T8	0	40	0	0
T9	0	151	0	0
T14	35272	13	0	0
T15	14504	0	0	0
T16	26784	0	0	0
T34	0	14	0	0
T86	0	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	500802830	3980	0	0
TransStop_A	500802830	2040	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500802830	3980	0	0
T1	183653	75	0	0
T2	309118	82	0	0
T3	316068	119	0	0
T4	96257	0	0	0
T5	355082	31	0	0
T6	2667	0	0	0
T7	191992	50	0	0
T8	0	17	0	0
T9	0	66	0	0
T14	8818	11	0	0
T15	3626	0	0	0
T16	6696	0	0	0
T34	0	6	0	0
T85	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500802830	2040	0	0
T1	183653	34	0	0
T2	309118	43	0	0
T3	316068	58	0	0
T4	96257	0	0	0
T5	355082	15	0	0
T6	2667	0	0	0
T7	191992	28	0	0
T8	0	10	0	0
T9	0	35	0	0
T14	8818	4	0	0
T15	3626	0	0	0
T16	6696	0	0	0
T34	0	4	0	0
T86	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	500802830	3962	0	0
TransStop_A	500802830	2022	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500802830	3962	0	0
T1	183653	68	0	0
T2	309118	69	0	0
T3	316068	108	0	0
T4	96257	0	0	0
T5	355082	27	0	0
T6	2667	0	0	0
T7	191992	44	0	0
T8	0	21	0	0
T9	0	69	0	0
T14	8818	8	0	0
T15	3626	0	0	0
T16	6696	0	0	0
T34	0	4	0	0
T85	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500802830	2022	0	0
T1	183653	35	0	0
T2	309118	34	0	0
T3	316068	54	0	0
T4	96257	0	0	0
T5	355082	14	0	0
T6	2667	0	0	0
T7	191992	24	0	0
T8	0	10	0	0
T9	0	36	0	0
T14	8818	4	0	0
T15	3626	0	0	0
T16	6696	0	0	0
T34	0	3	0	0
T86	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	500802830	4030	0	0
TransStop_A	500802830	2096	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500802830	4030	0	0
T1	183653	74	0	0
T2	309118	74	0	0
T3	316068	122	0	0
T4	96257	0	0	0
T5	355082	26	0	0
T6	2667	0	0	0
T7	191992	46	0	0
T8	0	23	0	0
T9	0	74	0	0
T14	8818	5	0	0
T15	3626	0	0	0
T16	6696	0	0	0
T34	0	5	0	0
T85	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500802830	2096	0	0
T1	183653	37	0	0
T2	309118	37	0	0
T3	316068	62	0	0
T4	96257	0	0	0
T5	355082	15	0	0
T6	2667	0	0	0
T7	191992	27	0	0
T8	0	11	0	0
T9	0	48	0	0
T14	8818	2	0	0
T15	3626	0	0	0
T16	6696	0	0	0
T34	0	2	0	0
T86	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	500802830	4001	0	0
TransStop_A	500802830	2056	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500802830	4001	0	0
T1	183653	78	0	0
T2	309118	78	0	0
T3	316068	123	0	0
T4	96257	0	0	0
T5	355082	25	0	0
T6	2667	0	0	0
T7	191992	49	0	0
T8	0	14	0	0
T9	0	62	0	0
T14	8818	8	0	0
T15	3626	0	0	0
T16	6696	0	0	0
T34	0	8	0	0
T85	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500802830	2056	0	0
T1	183653	34	0	0
T2	309118	34	0	0
T3	316068	55	0	0
T4	96257	0	0	0
T5	355082	14	0	0
T6	2667	0	0	0
T7	191992	27	0	0
T8	0	9	0	0
T9	0	32	0	0
T14	8818	3	0	0
T15	3626	0	0	0
T16	6696	0	0	0
T34	0	5	0	0
T86	0	2	0	0