Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_lc_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_clkmgr_byp.u_en_sync 100.00 100.00 100.00
tb.dut.u_clkmgr_byp.u_lc_byp_req 100.00 100.00 100.00



Module Instance : tb.dut.u_clkmgr_byp.u_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_clkmgr_byp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_clkmgr_byp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_clkmgr_byp.u_en_sync

Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_clkmgr_byp.u_lc_byp_req

Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 2 2


Assert Coverage for Module : prim_lc_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 1610 1610 0 0
OutputsKnown_A 316772638 312435174 0 0
gen_flops.OutputDelay_A 316772638 312420198 0 4830


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1610 1610 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T7 2 2 0 0
T14 2 2 0 0
T15 2 2 0 0
T16 2 2 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 316772638 312435174 0 0
T1 889932 888322 0 0
T2 1554592 1550180 0 0
T3 622958 613724 0 0
T4 125128 7828 0 0
T5 102780 102516 0 0
T6 5176 4930 0 0
T7 385184 382176 0 0
T14 4762 4694 0 0
T15 2004 1910 0 0
T16 3346 3226 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 316772638 312420198 0 4830
T1 889932 888316 0 6
T2 1554592 1550162 0 6
T3 622958 613718 0 6
T4 125128 7732 0 6
T5 102780 102480 0 6
T6 5176 4924 0 6
T7 385184 382172 0 6
T14 4762 4688 0 6
T15 2004 1904 0 6
T16 3346 3220 0 6

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_en_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 158386319 156217587 0 0
gen_flops.OutputDelay_A 158386319 156210099 0 2415


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 158386319 156217587 0 0
T1 444966 444161 0 0
T2 777296 775090 0 0
T3 311479 306862 0 0
T4 62564 3914 0 0
T5 51390 51258 0 0
T6 2588 2465 0 0
T7 192592 191088 0 0
T14 2381 2347 0 0
T15 1002 955 0 0
T16 1673 1613 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 158386319 156210099 0 2415
T1 444966 444158 0 3
T2 777296 775081 0 3
T3 311479 306859 0 3
T4 62564 3866 0 3
T5 51390 51240 0 3
T6 2588 2462 0 3
T7 192592 191086 0 3
T14 2381 2344 0 3
T15 1002 952 0 3
T16 1673 1610 0 3

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 2 2


Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 158386319 156217587 0 0
gen_flops.OutputDelay_A 158386319 156210099 0 2415


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 158386319 156217587 0 0
T1 444966 444161 0 0
T2 777296 775090 0 0
T3 311479 306862 0 0
T4 62564 3914 0 0
T5 51390 51258 0 0
T6 2588 2465 0 0
T7 192592 191088 0 0
T14 2381 2347 0 0
T15 1002 955 0 0
T16 1673 1613 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 158386319 156210099 0 2415
T1 444966 444158 0 3
T2 777296 775081 0 3
T3 311479 306859 0 3
T4 62564 3866 0 3
T5 51390 51240 0 3
T6 2588 2462 0 3
T7 192592 191086 0 3
T14 2381 2344 0 3
T15 1002 952 0 3
T16 1673 1610 0 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%