Unified Coverage Report :: Module :: prim_subreg_shadow

Module : prim_subreg_shadow

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi	99.04	100.00	96.15			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo	99.04	100.00	96.15			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi	99.04	100.00	96.15			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo	99.04	100.00	96.15			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi	99.04	100.00	96.15			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo	99.04	100.00	96.15			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi	99.04	100.00	96.15			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo	99.04	100.00	96.15			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi	99.04	100.00	96.15			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo	99.04	100.00	96.15			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Line Coverage for Module : prim_subreg_shadow

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Module : prim_subreg_shadow

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T39,T40,T41
1	1	Covered	T5,T1,T4

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T42,T39,T40
1	0	Covered	T1,T4,T2

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T39,T40,T41
1	1	1	Covered	T5,T1,T4

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T5,T1,T4
1	0	1	1	Covered	T5,T1,T4
1	1	0	1	Covered	T42,T39,T40
1	1	1	0	Not Covered
1	1	1	1	Covered	T5,T1,T4

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T5,T1,T4
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T5,T1,T4
1	Covered	T5,T1,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T5,T1,T4
1	Covered	T5,T1,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T4
1	0	Covered	T5,T1,T4
1	1	Covered	T42,T39,T40

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T42,T39,T40

---

Branch Coverage for Module : prim_subreg_shadow

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T4

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Module : prim_subreg_shadow

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	10100	10100	0	0
MubiIsNotYetSupported_A	2147483647	2147483647	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10100	10100	0	0
T1	10	10	0	0
T2	10	10	0	0
T3	10	10	0	0
T4	10	10	0	0
T5	10	10	0	0
T6	10	10	0	0
T7	10	10	0	0
T14	10	10	0	0
T15	10	10	0	0
T16	10	10	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5052236	5046288	0	0
T2	3218512	3211260	0	0
T3	3275004	3240094	0	0
T4	549862	37940	0	0
T5	2077970	2072330	0	0
T6	16864	16206	0	0
T7	5198824	5165836	0	0
T14	55590	54934	0	0
T15	22770	21772	0	0
T16	43006	41648	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T39,T40,T43
1	1	Covered	T5,T1,T4

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T39,T40,T41
1	0	Covered	T1,T4,T2

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T39,T40,T43
1	1	1	Covered	T5,T1,T4

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T5,T1,T4
1	0	1	1	Covered	T5,T1,T4
1	1	0	1	Covered	T39,T40,T41
1	1	1	0	Not Covered
1	1	1	1	Covered	T5,T1,T4

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T5,T1,T4
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T5,T1,T4
1	Covered	T5,T1,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T5,T1,T4
1	Covered	T5,T1,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T4
1	0	Covered	T5,T1,T4
1	1	Covered	T39,T40,T41

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T39,T40,T41

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T4

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	1010	1010	0	0
MubiIsNotYetSupported_A	471814153	467469745	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471814153	467469745	0	0
T1	172337	172061	0	0
T2	288680	287833	0	0
T3	293665	289578	0	0
T4	92403	5764	0	0
T5	300548	299606	0	0
T6	2560	2439	0	0
T7	176242	174798	0	0
T14	8465	8344	0	0
T15	3488	3312	0	0
T16	6427	6197	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T39,T40,T44
1	1	Covered	T5,T1,T4

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T39,T40,T41
1	0	Covered	T1,T4,T2

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T39,T40,T44
1	1	1	Covered	T5,T1,T4

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T5,T1,T4
1	0	1	1	Covered	T5,T1,T4
1	1	0	1	Covered	T39,T41,T44
1	1	1	0	Not Covered
1	1	1	1	Covered	T5,T1,T4

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T5,T1,T4
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T5,T1,T4
1	Covered	T5,T1,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T5,T1,T4
1	Covered	T5,T1,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T4
1	0	Covered	T5,T1,T4
1	1	Covered	T39,T41,T44

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T39,T40,T41

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T4

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	1010	1010	0	0
MubiIsNotYetSupported_A	471814153	467469745	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471814153	467469745	0	0
T1	172337	172061	0	0
T2	288680	287833	0	0
T3	293665	289578	0	0
T4	92403	5764	0	0
T5	300548	299606	0	0
T6	2560	2439	0	0
T7	176242	174798	0	0
T14	8465	8344	0	0
T15	3488	3312	0	0
T16	6427	6197	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T43,T45,T46
1	1	Covered	T5,T1,T4

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T42,T39,T40
1	0	Covered	T1,T4,T2

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T43,T45,T46
1	1	1	Covered	T5,T1,T4

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T5,T1,T4
1	0	1	1	Covered	T5,T1,T4
1	1	0	1	Covered	T39,T43,T45
1	1	1	0	Not Covered
1	1	1	1	Covered	T5,T1,T4

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T5,T1,T4
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T5,T1,T4
1	Covered	T5,T1,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T5,T1,T4
1	Covered	T5,T1,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T4
1	0	Covered	T5,T1,T4
1	1	Covered	T39,T43,T45

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T42,T39,T40

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T4

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	1010	1010	0	0
MubiIsNotYetSupported_A	235145726	234061829	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235145726	234061829	0	0
T1	862091	861414	0	0
T2	144327	144081	0	0
T3	145914	144872	0	0
T4	26714	2885	0	0
T5	151544	151262	0	0
T6	1283	1269	0	0
T7	878831	874612	0	0
T14	4186	4172	0	0
T15	1691	1656	0	0
T16	3446	3384	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T39,T40,T43
1	1	Covered	T5,T1,T4

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T39,T40,T47
1	0	Covered	T1,T4,T2

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T39,T40,T43
1	1	1	Covered	T5,T1,T4

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T5,T1,T4
1	0	1	1	Covered	T5,T1,T4
1	1	0	1	Covered	T39,T40,T43
1	1	1	0	Not Covered
1	1	1	1	Covered	T5,T1,T4

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T5,T1,T4
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T5,T1,T4
1	Covered	T5,T1,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T5,T1,T4
1	Covered	T5,T1,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T4
1	0	Covered	T5,T1,T4
1	1	Covered	T39,T40,T43

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T39,T40,T47

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T4

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	1010	1010	0	0
MubiIsNotYetSupported_A	235145726	234061829	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235145726	234061829	0	0
T1	862091	861414	0	0
T2	144327	144081	0	0
T3	145914	144872	0	0
T4	26714	2885	0	0
T5	151544	151262	0	0
T6	1283	1269	0	0
T7	878831	874612	0	0
T14	4186	4172	0	0
T15	1691	1656	0	0
T16	3446	3384	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T39,T41,T43
1	1	Covered	T5,T1,T4

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T39,T40,T41
1	0	Covered	T1,T4,T2

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T39,T41,T43
1	1	1	Covered	T5,T1,T4

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T5,T1,T4
1	0	1	1	Covered	T5,T1,T4
1	1	0	1	Covered	T42,T39,T40
1	1	1	0	Not Covered
1	1	1	1	Covered	T5,T1,T4

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T5,T1,T4
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T5,T1,T4
1	Covered	T5,T1,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T5,T1,T4
1	Covered	T5,T1,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T4
1	0	Covered	T5,T1,T4
1	1	Covered	T42,T39,T40

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T39,T40,T41

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T4

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	1010	1010	0	0
MubiIsNotYetSupported_A	117572248	117030420	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117572248	117030420	0	0
T1	431044	430705	0	0
T2	721632	720405	0	0
T3	729564	724357	0	0
T4	13355	1440	0	0
T5	75771	75630	0	0
T6	642	635	0	0
T7	439411	437302	0	0
T14	2093	2086	0	0
T15	845	828	0	0
T16	1722	1691	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T39,T41,T43
1	1	Covered	T5,T1,T4

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T42,T39,T40
1	0	Covered	T1,T4,T2

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T39,T41,T43
1	1	1	Covered	T5,T1,T4

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T5,T1,T4
1	0	1	1	Covered	T5,T1,T4
1	1	0	1	Covered	T42,T39,T40
1	1	1	0	Not Covered
1	1	1	1	Covered	T5,T1,T4

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T5,T1,T4
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T5,T1,T4
1	Covered	T5,T1,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T5,T1,T4
1	Covered	T5,T1,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T4
1	0	Covered	T5,T1,T4
1	1	Covered	T42,T39,T40

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T42,T39,T40

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T4

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	1010	1010	0	0
MubiIsNotYetSupported_A	117572248	117030420	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117572248	117030420	0	0
T1	431044	430705	0	0
T2	721632	720405	0	0
T3	729564	724357	0	0
T4	13355	1440	0	0
T5	75771	75630	0	0
T6	642	635	0	0
T7	439411	437302	0	0
T14	2093	2086	0	0
T15	845	828	0	0
T16	1722	1691	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T42,T39,T41
1	1	Covered	T5,T1,T4

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T42,T39,T41
1	0	Covered	T1,T4,T2

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T42,T39,T41
1	1	1	Covered	T5,T1,T4

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T5,T1,T4
1	0	1	1	Covered	T5,T1,T4
1	1	0	1	Covered	T39,T47,T44
1	1	1	0	Not Covered
1	1	1	1	Covered	T5,T1,T4

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T5,T1,T4
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T5,T1,T4
1	Covered	T5,T1,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T5,T1,T4
1	Covered	T5,T1,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T4
1	0	Covered	T5,T1,T4
1	1	Covered	T39,T47,T44

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T42,T39,T41

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T4

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	1010	1010	0	0
MubiIsNotYetSupported_A	503672543	499104537	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503672543	499104537	0	0
T1	183653	183327	0	0
T2	309118	308236	0	0
T3	316068	311258	0	0
T4	96256	6001	0	0
T5	355081	354099	0	0
T6	2667	2541	0	0
T7	191992	190488	0	0
T14	8818	8692	0	0
T15	3626	3443	0	0
T16	6695	6454	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T42,T39,T41
1	1	Covered	T5,T1,T4

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T42,T39,T41
1	0	Covered	T1,T4,T2

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T42,T39,T41
1	1	1	Covered	T5,T1,T4

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T5,T1,T4
1	0	1	1	Covered	T5,T1,T4
1	1	0	1	Covered	T42,T41,T47
1	1	1	0	Not Covered
1	1	1	1	Covered	T5,T1,T4

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T5,T1,T4
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T5,T1,T4
1	Covered	T5,T1,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T5,T1,T4
1	Covered	T5,T1,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T4
1	0	Covered	T5,T1,T4
1	1	Covered	T42,T41,T47

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T42,T39,T41

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T4

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	1010	1010	0	0
MubiIsNotYetSupported_A	503672543	499104537	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503672543	499104537	0	0
T1	183653	183327	0	0
T2	309118	308236	0	0
T3	316068	311258	0	0
T4	96256	6001	0	0
T5	355081	354099	0	0
T6	2667	2541	0	0
T7	191992	190488	0	0
T14	8818	8692	0	0
T15	3626	3443	0	0
T16	6695	6454	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T42,T39,T48
1	1	Covered	T5,T1,T4

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T42,T39,T40
1	0	Covered	T1,T4,T2

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T42,T39,T48
1	1	1	Covered	T5,T1,T4

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T5,T1,T4
1	0	1	1	Covered	T5,T1,T4
1	1	0	1	Covered	T39,T41,T47
1	1	1	0	Not Covered
1	1	1	1	Covered	T5,T1,T4

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T5,T1,T4
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T5,T1,T4
1	Covered	T5,T1,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T5,T1,T4
1	Covered	T5,T1,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T4
1	0	Covered	T5,T1,T4
1	1	Covered	T39,T41,T47

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T42,T39,T40

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T4

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	1010	1010	0	0
MubiIsNotYetSupported_A	241638260	239443805	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241638260	239443805	0	0
T1	876993	875637	0	0
T2	145499	145075	0	0
T3	152291	149982	0	0
T4	46203	2880	0	0
T5	156041	155568	0	0
T6	1280	1219	0	0
T7	912936	905718	0	0
T14	4233	4173	0	0
T15	1735	1647	0	0
T16	3213	3098	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T39,T40,T48
1	1	Covered	T5,T1,T4

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T42,T39,T40
1	0	Covered	T1,T4,T2

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T39,T40,T48
1	1	1	Covered	T5,T1,T4

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T5,T1,T4
1	0	1	1	Covered	T5,T1,T4
1	1	0	1	Covered	T39,T41,T48
1	1	1	0	Not Covered
1	1	1	1	Covered	T5,T1,T4

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T5,T1,T4
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T5,T1,T4
1	Covered	T5,T1,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T5,T1,T4
1	Covered	T5,T1,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T4
1	0	Covered	T5,T1,T4
1	1	Covered	T39,T41,T48

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T42,T39,T40

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T4

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	1010	1010	0	0
MubiIsNotYetSupported_A	241638260	239443805	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241638260	239443805	0	0
T1	876993	875637	0	0
T2	145499	145075	0	0
T3	152291	149982	0	0
T4	46203	2880	0	0
T5	156041	155568	0	0
T6	1280	1219	0	0
T7	912936	905718	0	0
T14	4233	4173	0	0
T15	1735	1647	0	0
T16	3213	3098	0	0