SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.clkmgr_lost_calib_regwen_sva_if | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.65 | 100.00 | 93.24 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
RegwenOff_A | 158386319 | 20487734 | 0 | 59 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 158386319 | 20487734 | 0 | 59 |
T1 | 444966 | 781915 | 0 | 0 |
T2 | 777296 | 309677 | 0 | 0 |
T3 | 311479 | 245661 | 0 | 0 |
T4 | 62564 | 0 | 0 | 0 |
T6 | 2588 | 0 | 0 | 0 |
T7 | 192592 | 377728 | 0 | 0 |
T8 | 106053 | 793427 | 0 | 0 |
T9 | 0 | 120453 | 0 | 0 |
T10 | 0 | 3741 | 0 | 1 |
T11 | 0 | 15660 | 0 | 1 |
T12 | 0 | 169563 | 0 | 0 |
T13 | 0 | 42792 | 0 | 0 |
T14 | 2381 | 0 | 0 | 0 |
T15 | 1002 | 0 | 0 | 0 |
T16 | 1673 | 0 | 0 | 0 |
T87 | 0 | 0 | 0 | 1 |
T88 | 0 | 0 | 0 | 1 |
T89 | 0 | 0 | 0 | 1 |
T90 | 0 | 0 | 0 | 1 |
T91 | 0 | 0 | 0 | 1 |
T92 | 0 | 0 | 0 | 1 |
T93 | 0 | 0 | 0 | 1 |
T94 | 0 | 0 | 0 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |