Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T4 |
1 | 0 | Covered | T5,T1,T4 |
1 | 1 | Covered | T5,T1,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T4 |
1 | 0 | Covered | T5,T1,T4 |
1 | 1 | Covered | T5,T1,T4 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
973916 |
0 |
0 |
T1 |
3818273 |
17535 |
0 |
0 |
T2 |
2529707 |
3706 |
0 |
0 |
T3 |
2088518 |
7252 |
0 |
0 |
T4 |
344720 |
150 |
0 |
0 |
T5 |
1237422 |
1173 |
0 |
0 |
T6 |
12306 |
0 |
0 |
0 |
T7 |
3636730 |
3780 |
0 |
0 |
T8 |
0 |
1513 |
0 |
0 |
T9 |
0 |
10589 |
0 |
0 |
T10 |
0 |
258 |
0 |
0 |
T11 |
0 |
189 |
0 |
0 |
T12 |
0 |
6095 |
0 |
0 |
T14 |
34315 |
0 |
0 |
0 |
T15 |
14034 |
0 |
0 |
0 |
T16 |
26855 |
0 |
0 |
0 |
T39 |
15612 |
3 |
0 |
0 |
T40 |
3992 |
0 |
0 |
0 |
T43 |
17336 |
3 |
0 |
0 |
T45 |
35804 |
1 |
0 |
0 |
T46 |
16354 |
1 |
0 |
0 |
T95 |
21718 |
1 |
0 |
0 |
T96 |
9126 |
1 |
0 |
0 |
T97 |
16688 |
1 |
0 |
0 |
T98 |
4414 |
1 |
0 |
0 |
T99 |
5265 |
3 |
0 |
0 |
T100 |
6859 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
970343 |
0 |
0 |
T1 |
3077807 |
17366 |
0 |
0 |
T2 |
1944647 |
3706 |
0 |
0 |
T3 |
998826 |
5942 |
0 |
0 |
T4 |
152686 |
150 |
0 |
0 |
T5 |
284268 |
1173 |
0 |
0 |
T6 |
7203 |
0 |
0 |
0 |
T7 |
1375331 |
3780 |
0 |
0 |
T8 |
0 |
1513 |
0 |
0 |
T9 |
0 |
10589 |
0 |
0 |
T10 |
0 |
258 |
0 |
0 |
T11 |
0 |
189 |
0 |
0 |
T12 |
0 |
6098 |
0 |
0 |
T14 |
11412 |
0 |
0 |
0 |
T15 |
4775 |
0 |
0 |
0 |
T16 |
8664 |
0 |
0 |
0 |
T39 |
13884 |
3 |
0 |
0 |
T40 |
3379 |
0 |
0 |
0 |
T43 |
57396 |
3 |
0 |
0 |
T45 |
15384 |
1 |
0 |
0 |
T46 |
7510 |
1 |
0 |
0 |
T95 |
19524 |
1 |
0 |
0 |
T96 |
8220 |
1 |
0 |
0 |
T97 |
7234 |
1 |
0 |
0 |
T98 |
3644 |
1 |
0 |
0 |
T99 |
9591 |
3 |
0 |
0 |
T100 |
6041 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T4 |
1 | 0 | Covered | T5,T1,T4 |
1 | 1 | Covered | T5,T1,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T4 |
1 | 0 | Covered | T5,T1,T4 |
1 | 1 | Covered | T5,T1,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471814153 |
25887 |
0 |
0 |
T1 |
172337 |
804 |
0 |
0 |
T2 |
288680 |
202 |
0 |
0 |
T3 |
293665 |
411 |
0 |
0 |
T4 |
92403 |
30 |
0 |
0 |
T5 |
300548 |
40 |
0 |
0 |
T6 |
2560 |
0 |
0 |
0 |
T7 |
176242 |
257 |
0 |
0 |
T8 |
0 |
87 |
0 |
0 |
T9 |
0 |
546 |
0 |
0 |
T10 |
0 |
18 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T14 |
8465 |
0 |
0 |
0 |
T15 |
3488 |
0 |
0 |
0 |
T16 |
6427 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159324155 |
25887 |
0 |
0 |
T1 |
444966 |
804 |
0 |
0 |
T2 |
777296 |
202 |
0 |
0 |
T3 |
311479 |
411 |
0 |
0 |
T4 |
62564 |
30 |
0 |
0 |
T5 |
51390 |
40 |
0 |
0 |
T6 |
2588 |
0 |
0 |
0 |
T7 |
192592 |
257 |
0 |
0 |
T8 |
0 |
87 |
0 |
0 |
T9 |
0 |
546 |
0 |
0 |
T10 |
0 |
18 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T14 |
2381 |
0 |
0 |
0 |
T15 |
1002 |
0 |
0 |
0 |
T16 |
1673 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T4 |
1 | 0 | Covered | T5,T1,T4 |
1 | 1 | Covered | T5,T1,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T4 |
1 | 0 | Covered | T5,T1,T4 |
1 | 1 | Covered | T5,T1,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471814153 |
31208 |
0 |
0 |
T1 |
172337 |
815 |
0 |
0 |
T2 |
288680 |
204 |
0 |
0 |
T3 |
293665 |
425 |
0 |
0 |
T4 |
92403 |
60 |
0 |
0 |
T5 |
300548 |
40 |
0 |
0 |
T6 |
2560 |
0 |
0 |
0 |
T7 |
176242 |
263 |
0 |
0 |
T8 |
0 |
95 |
0 |
0 |
T9 |
0 |
551 |
0 |
0 |
T10 |
0 |
18 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T14 |
8465 |
0 |
0 |
0 |
T15 |
3488 |
0 |
0 |
0 |
T16 |
6427 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159324155 |
31219 |
0 |
0 |
T1 |
444966 |
815 |
0 |
0 |
T2 |
777296 |
204 |
0 |
0 |
T3 |
311479 |
425 |
0 |
0 |
T4 |
62564 |
60 |
0 |
0 |
T5 |
51390 |
40 |
0 |
0 |
T6 |
2588 |
0 |
0 |
0 |
T7 |
192592 |
263 |
0 |
0 |
T8 |
0 |
95 |
0 |
0 |
T9 |
0 |
551 |
0 |
0 |
T10 |
0 |
18 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T14 |
2381 |
0 |
0 |
0 |
T15 |
1002 |
0 |
0 |
0 |
T16 |
1673 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T4 |
1 | 0 | Covered | T5,T1,T4 |
1 | 1 | Covered | T5,T1,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T4 |
1 | 0 | Covered | T5,T1,T4 |
1 | 1 | Covered | T5,T1,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159324155 |
31197 |
0 |
0 |
T1 |
444966 |
815 |
0 |
0 |
T2 |
777296 |
204 |
0 |
0 |
T3 |
311479 |
425 |
0 |
0 |
T4 |
62564 |
60 |
0 |
0 |
T5 |
51390 |
40 |
0 |
0 |
T6 |
2588 |
0 |
0 |
0 |
T7 |
192592 |
263 |
0 |
0 |
T8 |
0 |
95 |
0 |
0 |
T9 |
0 |
551 |
0 |
0 |
T10 |
0 |
18 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T14 |
2381 |
0 |
0 |
0 |
T15 |
1002 |
0 |
0 |
0 |
T16 |
1673 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471814153 |
31213 |
0 |
0 |
T1 |
172337 |
815 |
0 |
0 |
T2 |
288680 |
204 |
0 |
0 |
T3 |
293665 |
425 |
0 |
0 |
T4 |
92403 |
60 |
0 |
0 |
T5 |
300548 |
40 |
0 |
0 |
T6 |
2560 |
0 |
0 |
0 |
T7 |
176242 |
263 |
0 |
0 |
T8 |
0 |
95 |
0 |
0 |
T9 |
0 |
551 |
0 |
0 |
T10 |
0 |
18 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T14 |
8465 |
0 |
0 |
0 |
T15 |
3488 |
0 |
0 |
0 |
T16 |
6427 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T4 |
1 | 0 | Covered | T5,T1,T4 |
1 | 1 | Covered | T5,T1,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T4 |
1 | 0 | Covered | T5,T1,T4 |
1 | 1 | Covered | T5,T1,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
235145726 |
25887 |
0 |
0 |
T1 |
862091 |
804 |
0 |
0 |
T2 |
144327 |
202 |
0 |
0 |
T3 |
145914 |
411 |
0 |
0 |
T4 |
26714 |
30 |
0 |
0 |
T5 |
151544 |
40 |
0 |
0 |
T6 |
1283 |
0 |
0 |
0 |
T7 |
878831 |
257 |
0 |
0 |
T8 |
0 |
87 |
0 |
0 |
T9 |
0 |
546 |
0 |
0 |
T10 |
0 |
18 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T14 |
4186 |
0 |
0 |
0 |
T15 |
1691 |
0 |
0 |
0 |
T16 |
3446 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159324155 |
25887 |
0 |
0 |
T1 |
444966 |
804 |
0 |
0 |
T2 |
777296 |
202 |
0 |
0 |
T3 |
311479 |
411 |
0 |
0 |
T4 |
62564 |
30 |
0 |
0 |
T5 |
51390 |
40 |
0 |
0 |
T6 |
2588 |
0 |
0 |
0 |
T7 |
192592 |
257 |
0 |
0 |
T8 |
0 |
87 |
0 |
0 |
T9 |
0 |
546 |
0 |
0 |
T10 |
0 |
18 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T14 |
2381 |
0 |
0 |
0 |
T15 |
1002 |
0 |
0 |
0 |
T16 |
1673 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T4 |
1 | 0 | Covered | T5,T1,T4 |
1 | 1 | Covered | T5,T1,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T4 |
1 | 0 | Covered | T5,T1,T4 |
1 | 1 | Covered | T5,T1,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
235145726 |
31138 |
0 |
0 |
T1 |
862091 |
815 |
0 |
0 |
T2 |
144327 |
204 |
0 |
0 |
T3 |
145914 |
425 |
0 |
0 |
T4 |
26714 |
60 |
0 |
0 |
T5 |
151544 |
40 |
0 |
0 |
T6 |
1283 |
0 |
0 |
0 |
T7 |
878831 |
263 |
0 |
0 |
T8 |
0 |
95 |
0 |
0 |
T9 |
0 |
551 |
0 |
0 |
T10 |
0 |
18 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T14 |
4186 |
0 |
0 |
0 |
T15 |
1691 |
0 |
0 |
0 |
T16 |
3446 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159324155 |
31160 |
0 |
0 |
T1 |
444966 |
815 |
0 |
0 |
T2 |
777296 |
204 |
0 |
0 |
T3 |
311479 |
425 |
0 |
0 |
T4 |
62564 |
60 |
0 |
0 |
T5 |
51390 |
40 |
0 |
0 |
T6 |
2588 |
0 |
0 |
0 |
T7 |
192592 |
263 |
0 |
0 |
T8 |
0 |
95 |
0 |
0 |
T9 |
0 |
551 |
0 |
0 |
T10 |
0 |
18 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T14 |
2381 |
0 |
0 |
0 |
T15 |
1002 |
0 |
0 |
0 |
T16 |
1673 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T4 |
1 | 0 | Covered | T5,T1,T4 |
1 | 1 | Covered | T5,T1,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T4 |
1 | 0 | Covered | T5,T1,T4 |
1 | 1 | Covered | T5,T1,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159324155 |
31135 |
0 |
0 |
T1 |
444966 |
815 |
0 |
0 |
T2 |
777296 |
204 |
0 |
0 |
T3 |
311479 |
425 |
0 |
0 |
T4 |
62564 |
60 |
0 |
0 |
T5 |
51390 |
40 |
0 |
0 |
T6 |
2588 |
0 |
0 |
0 |
T7 |
192592 |
263 |
0 |
0 |
T8 |
0 |
95 |
0 |
0 |
T9 |
0 |
551 |
0 |
0 |
T10 |
0 |
18 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T14 |
2381 |
0 |
0 |
0 |
T15 |
1002 |
0 |
0 |
0 |
T16 |
1673 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
235145726 |
31140 |
0 |
0 |
T1 |
862091 |
815 |
0 |
0 |
T2 |
144327 |
204 |
0 |
0 |
T3 |
145914 |
425 |
0 |
0 |
T4 |
26714 |
60 |
0 |
0 |
T5 |
151544 |
40 |
0 |
0 |
T6 |
1283 |
0 |
0 |
0 |
T7 |
878831 |
263 |
0 |
0 |
T8 |
0 |
95 |
0 |
0 |
T9 |
0 |
551 |
0 |
0 |
T10 |
0 |
18 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T14 |
4186 |
0 |
0 |
0 |
T15 |
1691 |
0 |
0 |
0 |
T16 |
3446 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T4 |
1 | 0 | Covered | T5,T1,T4 |
1 | 1 | Covered | T5,T1,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T4 |
1 | 0 | Covered | T5,T1,T4 |
1 | 1 | Covered | T5,T1,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
117572248 |
25887 |
0 |
0 |
T1 |
431044 |
804 |
0 |
0 |
T2 |
721632 |
202 |
0 |
0 |
T3 |
729564 |
411 |
0 |
0 |
T4 |
13355 |
30 |
0 |
0 |
T5 |
75771 |
40 |
0 |
0 |
T6 |
642 |
0 |
0 |
0 |
T7 |
439411 |
257 |
0 |
0 |
T8 |
0 |
87 |
0 |
0 |
T9 |
0 |
546 |
0 |
0 |
T10 |
0 |
18 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T14 |
2093 |
0 |
0 |
0 |
T15 |
845 |
0 |
0 |
0 |
T16 |
1722 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159324155 |
25887 |
0 |
0 |
T1 |
444966 |
804 |
0 |
0 |
T2 |
777296 |
202 |
0 |
0 |
T3 |
311479 |
411 |
0 |
0 |
T4 |
62564 |
30 |
0 |
0 |
T5 |
51390 |
40 |
0 |
0 |
T6 |
2588 |
0 |
0 |
0 |
T7 |
192592 |
257 |
0 |
0 |
T8 |
0 |
87 |
0 |
0 |
T9 |
0 |
546 |
0 |
0 |
T10 |
0 |
18 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T14 |
2381 |
0 |
0 |
0 |
T15 |
1002 |
0 |
0 |
0 |
T16 |
1673 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T4 |
1 | 0 | Covered | T5,T1,T4 |
1 | 1 | Covered | T5,T1,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T4 |
1 | 0 | Covered | T5,T1,T4 |
1 | 1 | Covered | T5,T1,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
117572248 |
31284 |
0 |
0 |
T1 |
431044 |
815 |
0 |
0 |
T2 |
721632 |
204 |
0 |
0 |
T3 |
729564 |
425 |
0 |
0 |
T4 |
13355 |
60 |
0 |
0 |
T5 |
75771 |
40 |
0 |
0 |
T6 |
642 |
0 |
0 |
0 |
T7 |
439411 |
263 |
0 |
0 |
T8 |
0 |
95 |
0 |
0 |
T9 |
0 |
551 |
0 |
0 |
T10 |
0 |
18 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T14 |
2093 |
0 |
0 |
0 |
T15 |
845 |
0 |
0 |
0 |
T16 |
1722 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159324155 |
31322 |
0 |
0 |
T1 |
444966 |
815 |
0 |
0 |
T2 |
777296 |
204 |
0 |
0 |
T3 |
311479 |
425 |
0 |
0 |
T4 |
62564 |
60 |
0 |
0 |
T5 |
51390 |
40 |
0 |
0 |
T6 |
2588 |
0 |
0 |
0 |
T7 |
192592 |
263 |
0 |
0 |
T8 |
0 |
95 |
0 |
0 |
T9 |
0 |
551 |
0 |
0 |
T10 |
0 |
18 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T14 |
2381 |
0 |
0 |
0 |
T15 |
1002 |
0 |
0 |
0 |
T16 |
1673 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T4 |
1 | 0 | Covered | T5,T1,T4 |
1 | 1 | Covered | T5,T1,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T4 |
1 | 0 | Covered | T5,T1,T4 |
1 | 1 | Covered | T5,T1,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159324155 |
31278 |
0 |
0 |
T1 |
444966 |
815 |
0 |
0 |
T2 |
777296 |
204 |
0 |
0 |
T3 |
311479 |
425 |
0 |
0 |
T4 |
62564 |
60 |
0 |
0 |
T5 |
51390 |
40 |
0 |
0 |
T6 |
2588 |
0 |
0 |
0 |
T7 |
192592 |
263 |
0 |
0 |
T8 |
0 |
95 |
0 |
0 |
T9 |
0 |
551 |
0 |
0 |
T10 |
0 |
18 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T14 |
2381 |
0 |
0 |
0 |
T15 |
1002 |
0 |
0 |
0 |
T16 |
1673 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
117572248 |
31290 |
0 |
0 |
T1 |
431044 |
815 |
0 |
0 |
T2 |
721632 |
204 |
0 |
0 |
T3 |
729564 |
425 |
0 |
0 |
T4 |
13355 |
60 |
0 |
0 |
T5 |
75771 |
40 |
0 |
0 |
T6 |
642 |
0 |
0 |
0 |
T7 |
439411 |
263 |
0 |
0 |
T8 |
0 |
95 |
0 |
0 |
T9 |
0 |
551 |
0 |
0 |
T10 |
0 |
18 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T14 |
2093 |
0 |
0 |
0 |
T15 |
845 |
0 |
0 |
0 |
T16 |
1722 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T4 |
1 | 0 | Covered | T5,T1,T4 |
1 | 1 | Covered | T5,T1,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T4 |
1 | 0 | Covered | T5,T1,T4 |
1 | 1 | Covered | T5,T1,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
503672543 |
25887 |
0 |
0 |
T1 |
183653 |
804 |
0 |
0 |
T2 |
309118 |
202 |
0 |
0 |
T3 |
316068 |
411 |
0 |
0 |
T4 |
96256 |
30 |
0 |
0 |
T5 |
355081 |
40 |
0 |
0 |
T6 |
2667 |
0 |
0 |
0 |
T7 |
191992 |
257 |
0 |
0 |
T8 |
0 |
87 |
0 |
0 |
T9 |
0 |
546 |
0 |
0 |
T10 |
0 |
18 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T14 |
8818 |
0 |
0 |
0 |
T15 |
3626 |
0 |
0 |
0 |
T16 |
6695 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159324155 |
25887 |
0 |
0 |
T1 |
444966 |
804 |
0 |
0 |
T2 |
777296 |
202 |
0 |
0 |
T3 |
311479 |
411 |
0 |
0 |
T4 |
62564 |
30 |
0 |
0 |
T5 |
51390 |
40 |
0 |
0 |
T6 |
2588 |
0 |
0 |
0 |
T7 |
192592 |
257 |
0 |
0 |
T8 |
0 |
87 |
0 |
0 |
T9 |
0 |
546 |
0 |
0 |
T10 |
0 |
18 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T14 |
2381 |
0 |
0 |
0 |
T15 |
1002 |
0 |
0 |
0 |
T16 |
1673 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T4 |
1 | 0 | Covered | T5,T1,T4 |
1 | 1 | Covered | T5,T1,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T4 |
1 | 0 | Covered | T5,T1,T4 |
1 | 1 | Covered | T5,T1,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
503672543 |
31272 |
0 |
0 |
T1 |
183653 |
815 |
0 |
0 |
T2 |
309118 |
204 |
0 |
0 |
T3 |
316068 |
425 |
0 |
0 |
T4 |
96256 |
60 |
0 |
0 |
T5 |
355081 |
40 |
0 |
0 |
T6 |
2667 |
0 |
0 |
0 |
T7 |
191992 |
263 |
0 |
0 |
T8 |
0 |
95 |
0 |
0 |
T9 |
0 |
551 |
0 |
0 |
T10 |
0 |
18 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T14 |
8818 |
0 |
0 |
0 |
T15 |
3626 |
0 |
0 |
0 |
T16 |
6695 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159324155 |
31287 |
0 |
0 |
T1 |
444966 |
815 |
0 |
0 |
T2 |
777296 |
204 |
0 |
0 |
T3 |
311479 |
425 |
0 |
0 |
T4 |
62564 |
60 |
0 |
0 |
T5 |
51390 |
40 |
0 |
0 |
T6 |
2588 |
0 |
0 |
0 |
T7 |
192592 |
263 |
0 |
0 |
T8 |
0 |
95 |
0 |
0 |
T9 |
0 |
551 |
0 |
0 |
T10 |
0 |
18 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T14 |
2381 |
0 |
0 |
0 |
T15 |
1002 |
0 |
0 |
0 |
T16 |
1673 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T4 |
1 | 0 | Covered | T5,T1,T4 |
1 | 1 | Covered | T5,T1,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T4 |
1 | 0 | Covered | T5,T1,T4 |
1 | 1 | Covered | T5,T1,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159324155 |
31259 |
0 |
0 |
T1 |
444966 |
815 |
0 |
0 |
T2 |
777296 |
204 |
0 |
0 |
T3 |
311479 |
425 |
0 |
0 |
T4 |
62564 |
60 |
0 |
0 |
T5 |
51390 |
40 |
0 |
0 |
T6 |
2588 |
0 |
0 |
0 |
T7 |
192592 |
263 |
0 |
0 |
T8 |
0 |
95 |
0 |
0 |
T9 |
0 |
551 |
0 |
0 |
T10 |
0 |
18 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T14 |
2381 |
0 |
0 |
0 |
T15 |
1002 |
0 |
0 |
0 |
T16 |
1673 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
503672543 |
31278 |
0 |
0 |
T1 |
183653 |
815 |
0 |
0 |
T2 |
309118 |
204 |
0 |
0 |
T3 |
316068 |
425 |
0 |
0 |
T4 |
96256 |
60 |
0 |
0 |
T5 |
355081 |
40 |
0 |
0 |
T6 |
2667 |
0 |
0 |
0 |
T7 |
191992 |
263 |
0 |
0 |
T8 |
0 |
95 |
0 |
0 |
T9 |
0 |
551 |
0 |
0 |
T10 |
0 |
18 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T14 |
8818 |
0 |
0 |
0 |
T15 |
3626 |
0 |
0 |
0 |
T16 |
6695 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T4 |
1 | 0 | Covered | T5,T1,T4 |
1 | 1 | Covered | T5,T1,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T4 |
1 | 0 | Covered | T5,T1,T2 |
1 | 1 | Covered | T5,T1,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
241638260 |
25492 |
0 |
0 |
T1 |
876993 |
804 |
0 |
0 |
T2 |
145499 |
202 |
0 |
0 |
T3 |
152291 |
411 |
0 |
0 |
T4 |
46203 |
15 |
0 |
0 |
T5 |
156041 |
40 |
0 |
0 |
T6 |
1280 |
0 |
0 |
0 |
T7 |
912936 |
257 |
0 |
0 |
T8 |
0 |
87 |
0 |
0 |
T9 |
0 |
546 |
0 |
0 |
T10 |
0 |
18 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T14 |
4233 |
0 |
0 |
0 |
T15 |
1735 |
0 |
0 |
0 |
T16 |
3213 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159324155 |
25887 |
0 |
0 |
T1 |
444966 |
804 |
0 |
0 |
T2 |
777296 |
202 |
0 |
0 |
T3 |
311479 |
411 |
0 |
0 |
T4 |
62564 |
30 |
0 |
0 |
T5 |
51390 |
40 |
0 |
0 |
T6 |
2588 |
0 |
0 |
0 |
T7 |
192592 |
257 |
0 |
0 |
T8 |
0 |
87 |
0 |
0 |
T9 |
0 |
546 |
0 |
0 |
T10 |
0 |
18 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T14 |
2381 |
0 |
0 |
0 |
T15 |
1002 |
0 |
0 |
0 |
T16 |
1673 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T4 |
1 | 0 | Covered | T5,T1,T4 |
1 | 1 | Covered | T5,T1,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T4 |
1 | 0 | Covered | T5,T1,T4 |
1 | 1 | Covered | T5,T1,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
241638260 |
31183 |
0 |
0 |
T1 |
876993 |
815 |
0 |
0 |
T2 |
145499 |
204 |
0 |
0 |
T3 |
152291 |
425 |
0 |
0 |
T4 |
46203 |
45 |
0 |
0 |
T5 |
156041 |
40 |
0 |
0 |
T6 |
1280 |
0 |
0 |
0 |
T7 |
912936 |
263 |
0 |
0 |
T8 |
0 |
95 |
0 |
0 |
T9 |
0 |
551 |
0 |
0 |
T10 |
0 |
18 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T14 |
4233 |
0 |
0 |
0 |
T15 |
1735 |
0 |
0 |
0 |
T16 |
3213 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159324155 |
31285 |
0 |
0 |
T1 |
444966 |
815 |
0 |
0 |
T2 |
777296 |
204 |
0 |
0 |
T3 |
311479 |
425 |
0 |
0 |
T4 |
62564 |
60 |
0 |
0 |
T5 |
51390 |
40 |
0 |
0 |
T6 |
2588 |
0 |
0 |
0 |
T7 |
192592 |
263 |
0 |
0 |
T8 |
0 |
95 |
0 |
0 |
T9 |
0 |
551 |
0 |
0 |
T10 |
0 |
18 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T14 |
2381 |
0 |
0 |
0 |
T15 |
1002 |
0 |
0 |
0 |
T16 |
1673 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T4 |
1 | 0 | Covered | T5,T1,T4 |
1 | 1 | Covered | T5,T1,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T4 |
1 | 0 | Covered | T5,T1,T4 |
1 | 1 | Covered | T5,T1,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159324155 |
31034 |
0 |
0 |
T1 |
444966 |
815 |
0 |
0 |
T2 |
777296 |
204 |
0 |
0 |
T3 |
311479 |
425 |
0 |
0 |
T4 |
62564 |
45 |
0 |
0 |
T5 |
51390 |
40 |
0 |
0 |
T6 |
2588 |
0 |
0 |
0 |
T7 |
192592 |
263 |
0 |
0 |
T8 |
0 |
95 |
0 |
0 |
T9 |
0 |
551 |
0 |
0 |
T10 |
0 |
18 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T14 |
2381 |
0 |
0 |
0 |
T15 |
1002 |
0 |
0 |
0 |
T16 |
1673 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
241638260 |
31203 |
0 |
0 |
T1 |
876993 |
815 |
0 |
0 |
T2 |
145499 |
204 |
0 |
0 |
T3 |
152291 |
425 |
0 |
0 |
T4 |
46203 |
50 |
0 |
0 |
T5 |
156041 |
40 |
0 |
0 |
T6 |
1280 |
0 |
0 |
0 |
T7 |
912936 |
263 |
0 |
0 |
T8 |
0 |
95 |
0 |
0 |
T9 |
0 |
551 |
0 |
0 |
T10 |
0 |
18 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T14 |
4233 |
0 |
0 |
0 |
T15 |
1735 |
0 |
0 |
0 |
T16 |
3213 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T39,T40,T41 |
1 | 0 | Covered | T39,T40,T41 |
1 | 1 | Covered | T39,T40,T48 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T39,T40,T41 |
1 | 0 | Covered | T39,T40,T48 |
1 | 1 | Covered | T39,T40,T41 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159324155 |
39 |
0 |
0 |
T39 |
7806 |
3 |
0 |
0 |
T40 |
3992 |
2 |
0 |
0 |
T41 |
4406 |
1 |
0 |
0 |
T43 |
8668 |
3 |
0 |
0 |
T44 |
16750 |
1 |
0 |
0 |
T46 |
8177 |
1 |
0 |
0 |
T48 |
3511 |
2 |
0 |
0 |
T95 |
10859 |
1 |
0 |
0 |
T101 |
7213 |
2 |
0 |
0 |
T102 |
10519 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471814153 |
39 |
0 |
0 |
T39 |
15293 |
3 |
0 |
0 |
T40 |
7822 |
2 |
0 |
0 |
T41 |
9195 |
1 |
0 |
0 |
T43 |
59441 |
3 |
0 |
0 |
T44 |
16080 |
1 |
0 |
0 |
T46 |
8351 |
1 |
0 |
0 |
T48 |
21066 |
2 |
0 |
0 |
T95 |
20848 |
1 |
0 |
0 |
T101 |
6923 |
2 |
0 |
0 |
T102 |
43903 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T39,T41,T44 |
1 | 0 | Covered | T39,T41,T44 |
1 | 1 | Covered | T39,T41,T44 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T39,T41,T44 |
1 | 0 | Covered | T39,T41,T44 |
1 | 1 | Covered | T39,T41,T44 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159324155 |
44 |
0 |
0 |
T39 |
7806 |
3 |
0 |
0 |
T41 |
4406 |
2 |
0 |
0 |
T43 |
8668 |
3 |
0 |
0 |
T44 |
16750 |
2 |
0 |
0 |
T48 |
3511 |
1 |
0 |
0 |
T95 |
10859 |
1 |
0 |
0 |
T101 |
7213 |
2 |
0 |
0 |
T102 |
10519 |
2 |
0 |
0 |
T103 |
2780 |
3 |
0 |
0 |
T104 |
7014 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471814153 |
44 |
0 |
0 |
T39 |
15293 |
3 |
0 |
0 |
T41 |
9195 |
2 |
0 |
0 |
T43 |
59441 |
3 |
0 |
0 |
T44 |
16080 |
2 |
0 |
0 |
T48 |
21066 |
1 |
0 |
0 |
T95 |
20848 |
1 |
0 |
0 |
T101 |
6923 |
2 |
0 |
0 |
T102 |
43903 |
2 |
0 |
0 |
T103 |
11604 |
3 |
0 |
0 |
T104 |
61213 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T39,T43,T45 |
1 | 0 | Covered | T39,T43,T45 |
1 | 1 | Covered | T39,T43,T105 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T39,T43,T45 |
1 | 0 | Covered | T39,T43,T105 |
1 | 1 | Covered | T39,T43,T45 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159324155 |
28 |
0 |
0 |
T39 |
7806 |
3 |
0 |
0 |
T43 |
8668 |
3 |
0 |
0 |
T45 |
17902 |
1 |
0 |
0 |
T46 |
8177 |
1 |
0 |
0 |
T95 |
10859 |
1 |
0 |
0 |
T96 |
4563 |
1 |
0 |
0 |
T97 |
8344 |
1 |
0 |
0 |
T98 |
4414 |
1 |
0 |
0 |
T99 |
5265 |
3 |
0 |
0 |
T100 |
6859 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
235145726 |
28 |
0 |
0 |
T39 |
6942 |
3 |
0 |
0 |
T43 |
28698 |
3 |
0 |
0 |
T45 |
7692 |
1 |
0 |
0 |
T46 |
3755 |
1 |
0 |
0 |
T95 |
9762 |
1 |
0 |
0 |
T96 |
4110 |
1 |
0 |
0 |
T97 |
3617 |
1 |
0 |
0 |
T98 |
3644 |
1 |
0 |
0 |
T99 |
9591 |
3 |
0 |
0 |
T100 |
6041 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T39,T40,T43 |
1 | 0 | Covered | T39,T40,T43 |
1 | 1 | Covered | T39,T43,T97 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T39,T40,T43 |
1 | 0 | Covered | T39,T43,T97 |
1 | 1 | Covered | T39,T40,T43 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159324155 |
29 |
0 |
0 |
T39 |
7806 |
2 |
0 |
0 |
T40 |
3992 |
1 |
0 |
0 |
T43 |
8668 |
4 |
0 |
0 |
T45 |
17902 |
2 |
0 |
0 |
T46 |
8177 |
1 |
0 |
0 |
T95 |
10859 |
1 |
0 |
0 |
T96 |
4563 |
1 |
0 |
0 |
T97 |
8344 |
2 |
0 |
0 |
T102 |
10519 |
1 |
0 |
0 |
T106 |
7367 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
235145726 |
29 |
0 |
0 |
T39 |
6942 |
2 |
0 |
0 |
T40 |
3379 |
1 |
0 |
0 |
T43 |
28698 |
4 |
0 |
0 |
T45 |
7692 |
2 |
0 |
0 |
T46 |
3755 |
1 |
0 |
0 |
T95 |
9762 |
1 |
0 |
0 |
T96 |
4110 |
1 |
0 |
0 |
T97 |
3617 |
2 |
0 |
0 |
T102 |
21039 |
1 |
0 |
0 |
T106 |
6345 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T42,T39,T40 |
1 | 0 | Covered | T42,T39,T40 |
1 | 1 | Covered | T42,T43,T99 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T42,T39,T40 |
1 | 0 | Covered | T42,T43,T99 |
1 | 1 | Covered | T42,T39,T40 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159324155 |
42 |
0 |
0 |
T39 |
7806 |
2 |
0 |
0 |
T40 |
3992 |
1 |
0 |
0 |
T41 |
4406 |
1 |
0 |
0 |
T42 |
2973 |
2 |
0 |
0 |
T43 |
8668 |
3 |
0 |
0 |
T44 |
16750 |
1 |
0 |
0 |
T45 |
17902 |
1 |
0 |
0 |
T48 |
3511 |
2 |
0 |
0 |
T95 |
10859 |
1 |
0 |
0 |
T101 |
7213 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
117572248 |
42 |
0 |
0 |
T39 |
3469 |
2 |
0 |
0 |
T40 |
1691 |
1 |
0 |
0 |
T41 |
2133 |
1 |
0 |
0 |
T42 |
3993 |
2 |
0 |
0 |
T43 |
14349 |
3 |
0 |
0 |
T44 |
3562 |
1 |
0 |
0 |
T45 |
3845 |
1 |
0 |
0 |
T48 |
5092 |
2 |
0 |
0 |
T95 |
4882 |
1 |
0 |
0 |
T101 |
1498 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T42,T39,T40 |
1 | 0 | Covered | T42,T39,T40 |
1 | 1 | Covered | T43,T107 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T42,T39,T40 |
1 | 0 | Covered | T43,T107 |
1 | 1 | Covered | T42,T39,T40 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159324155 |
40 |
0 |
0 |
T39 |
7806 |
2 |
0 |
0 |
T40 |
3992 |
2 |
0 |
0 |
T41 |
4406 |
1 |
0 |
0 |
T42 |
2973 |
1 |
0 |
0 |
T43 |
8668 |
3 |
0 |
0 |
T45 |
17902 |
1 |
0 |
0 |
T48 |
3511 |
2 |
0 |
0 |
T95 |
10859 |
1 |
0 |
0 |
T101 |
7213 |
1 |
0 |
0 |
T102 |
10519 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
117572248 |
40 |
0 |
0 |
T39 |
3469 |
2 |
0 |
0 |
T40 |
1691 |
2 |
0 |
0 |
T41 |
2133 |
1 |
0 |
0 |
T42 |
3993 |
1 |
0 |
0 |
T43 |
14349 |
3 |
0 |
0 |
T45 |
3845 |
1 |
0 |
0 |
T48 |
5092 |
2 |
0 |
0 |
T95 |
4882 |
1 |
0 |
0 |
T101 |
1498 |
1 |
0 |
0 |
T102 |
10521 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T39,T47,T44 |
1 | 0 | Covered | T39,T47,T44 |
1 | 1 | Covered | T47,T48,T108 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T39,T47,T44 |
1 | 0 | Covered | T47,T48,T108 |
1 | 1 | Covered | T39,T47,T44 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159324155 |
34 |
0 |
0 |
T39 |
7806 |
1 |
0 |
0 |
T44 |
16750 |
1 |
0 |
0 |
T45 |
17902 |
1 |
0 |
0 |
T47 |
3896 |
3 |
0 |
0 |
T48 |
3511 |
2 |
0 |
0 |
T103 |
2780 |
1 |
0 |
0 |
T104 |
7014 |
1 |
0 |
0 |
T106 |
7367 |
1 |
0 |
0 |
T108 |
7494 |
2 |
0 |
0 |
T109 |
7325 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
503672543 |
34 |
0 |
0 |
T39 |
15930 |
1 |
0 |
0 |
T44 |
16750 |
1 |
0 |
0 |
T45 |
17902 |
1 |
0 |
0 |
T47 |
15584 |
3 |
0 |
0 |
T48 |
21945 |
2 |
0 |
0 |
T103 |
12088 |
1 |
0 |
0 |
T104 |
63766 |
1 |
0 |
0 |
T106 |
15035 |
1 |
0 |
0 |
T108 |
7889 |
2 |
0 |
0 |
T109 |
7399 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T42,T41,T47 |
1 | 0 | Covered | T42,T41,T47 |
1 | 1 | Covered | T47,T45,T48 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T42,T41,T47 |
1 | 0 | Covered | T47,T45,T48 |
1 | 1 | Covered | T42,T41,T47 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159324155 |
38 |
0 |
0 |
T41 |
4406 |
1 |
0 |
0 |
T42 |
2973 |
1 |
0 |
0 |
T43 |
8668 |
1 |
0 |
0 |
T45 |
17902 |
2 |
0 |
0 |
T47 |
3896 |
2 |
0 |
0 |
T48 |
3511 |
2 |
0 |
0 |
T102 |
10519 |
1 |
0 |
0 |
T103 |
2780 |
1 |
0 |
0 |
T106 |
7367 |
1 |
0 |
0 |
T108 |
7494 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
503672543 |
38 |
0 |
0 |
T41 |
9579 |
1 |
0 |
0 |
T42 |
17489 |
1 |
0 |
0 |
T43 |
61919 |
1 |
0 |
0 |
T45 |
17902 |
2 |
0 |
0 |
T47 |
15584 |
2 |
0 |
0 |
T48 |
21945 |
2 |
0 |
0 |
T102 |
45733 |
1 |
0 |
0 |
T103 |
12088 |
1 |
0 |
0 |
T106 |
15035 |
1 |
0 |
0 |
T108 |
7889 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T39,T41,T47 |
1 | 0 | Covered | T39,T41,T47 |
1 | 1 | Covered | T39,T41,T46 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T39,T41,T47 |
1 | 0 | Covered | T39,T41,T46 |
1 | 1 | Covered | T39,T41,T47 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159324155 |
34 |
0 |
0 |
T39 |
7806 |
3 |
0 |
0 |
T41 |
4406 |
3 |
0 |
0 |
T46 |
8177 |
2 |
0 |
0 |
T47 |
3896 |
1 |
0 |
0 |
T48 |
3511 |
1 |
0 |
0 |
T102 |
10519 |
1 |
0 |
0 |
T103 |
2780 |
1 |
0 |
0 |
T106 |
7367 |
2 |
0 |
0 |
T109 |
7325 |
2 |
0 |
0 |
T110 |
4186 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
241638260 |
34 |
0 |
0 |
T39 |
7647 |
3 |
0 |
0 |
T41 |
4598 |
3 |
0 |
0 |
T46 |
4176 |
2 |
0 |
0 |
T47 |
7480 |
1 |
0 |
0 |
T48 |
10534 |
1 |
0 |
0 |
T102 |
21952 |
1 |
0 |
0 |
T103 |
5802 |
1 |
0 |
0 |
T106 |
7217 |
2 |
0 |
0 |
T109 |
3551 |
2 |
0 |
0 |
T110 |
9569 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T39,T41,T48 |
1 | 0 | Covered | T39,T41,T48 |
1 | 1 | Covered | T41,T109,T111 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T39,T41,T48 |
1 | 0 | Covered | T41,T109,T111 |
1 | 1 | Covered | T39,T41,T48 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159324155 |
29 |
0 |
0 |
T39 |
7806 |
2 |
0 |
0 |
T41 |
4406 |
4 |
0 |
0 |
T46 |
8177 |
1 |
0 |
0 |
T48 |
3511 |
1 |
0 |
0 |
T98 |
4414 |
1 |
0 |
0 |
T102 |
10519 |
1 |
0 |
0 |
T104 |
7014 |
1 |
0 |
0 |
T109 |
7325 |
3 |
0 |
0 |
T110 |
4186 |
1 |
0 |
0 |
T112 |
4644 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
241638260 |
29 |
0 |
0 |
T39 |
7647 |
2 |
0 |
0 |
T41 |
4598 |
4 |
0 |
0 |
T46 |
4176 |
1 |
0 |
0 |
T48 |
10534 |
1 |
0 |
0 |
T98 |
4238 |
1 |
0 |
0 |
T102 |
21952 |
1 |
0 |
0 |
T104 |
30608 |
1 |
0 |
0 |
T109 |
3551 |
3 |
0 |
0 |
T110 |
9569 |
1 |
0 |
0 |
T112 |
14862 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T2 |
1 | 0 | Covered | T5,T1,T2 |
1 | 1 | Covered | T5,T1,T2 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T2 |
1 | 0 | Covered | T5,T1,T2 |
1 | 1 | Covered | T5,T1,T2 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469058879 |
99169 |
0 |
0 |
T1 |
172337 |
3727 |
0 |
0 |
T2 |
288680 |
732 |
0 |
0 |
T3 |
293665 |
1450 |
0 |
0 |
T4 |
92403 |
0 |
0 |
0 |
T5 |
300548 |
253 |
0 |
0 |
T6 |
2560 |
0 |
0 |
0 |
T7 |
176242 |
708 |
0 |
0 |
T8 |
0 |
288 |
0 |
0 |
T9 |
0 |
2065 |
0 |
0 |
T10 |
0 |
51 |
0 |
0 |
T11 |
0 |
33 |
0 |
0 |
T12 |
0 |
1357 |
0 |
0 |
T14 |
8465 |
0 |
0 |
0 |
T15 |
3488 |
0 |
0 |
0 |
T16 |
6427 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
15272807 |
97991 |
0 |
0 |
T1 |
335540 |
3728 |
0 |
0 |
T2 |
61390 |
732 |
0 |
0 |
T3 |
56619 |
1013 |
0 |
0 |
T4 |
211 |
0 |
0 |
0 |
T5 |
7465 |
253 |
0 |
0 |
T6 |
186 |
0 |
0 |
0 |
T7 |
27787 |
708 |
0 |
0 |
T8 |
0 |
288 |
0 |
0 |
T9 |
0 |
2065 |
0 |
0 |
T10 |
0 |
51 |
0 |
0 |
T11 |
0 |
33 |
0 |
0 |
T12 |
0 |
1358 |
0 |
0 |
T14 |
616 |
0 |
0 |
0 |
T15 |
270 |
0 |
0 |
0 |
T16 |
468 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T2 |
1 | 0 | Covered | T5,T1,T2 |
1 | 1 | Covered | T5,T1,T2 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T2 |
1 | 0 | Covered | T5,T1,T2 |
1 | 1 | Covered | T5,T1,T2 |
Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
233811823 |
98378 |
0 |
0 |
T1 |
862091 |
3686 |
0 |
0 |
T2 |
144327 |
732 |
0 |
0 |
T3 |
145914 |
1450 |
0 |
0 |
T4 |
26714 |
0 |
0 |
0 |
T5 |
151544 |
252 |
0 |
0 |
T6 |
1283 |
0 |
0 |
0 |
T7 |
878831 |
708 |
0 |
0 |
T8 |
0 |
288 |
0 |
0 |
T9 |
0 |
2059 |
0 |
0 |
T10 |
0 |
51 |
0 |
0 |
T11 |
0 |
33 |
0 |
0 |
T12 |
0 |
1357 |
0 |
0 |
T14 |
4186 |
0 |
0 |
0 |
T15 |
1691 |
0 |
0 |
0 |
T16 |
3446 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
15272807 |
97200 |
0 |
0 |
T1 |
335540 |
3687 |
0 |
0 |
T2 |
61390 |
732 |
0 |
0 |
T3 |
56619 |
1013 |
0 |
0 |
T4 |
211 |
0 |
0 |
0 |
T5 |
7465 |
252 |
0 |
0 |
T6 |
186 |
0 |
0 |
0 |
T7 |
27787 |
708 |
0 |
0 |
T8 |
0 |
288 |
0 |
0 |
T9 |
0 |
2059 |
0 |
0 |
T10 |
0 |
51 |
0 |
0 |
T11 |
0 |
33 |
0 |
0 |
T12 |
0 |
1358 |
0 |
0 |
T14 |
616 |
0 |
0 |
0 |
T15 |
270 |
0 |
0 |
0 |
T16 |
468 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T2 |
1 | 0 | Covered | T5,T1,T2 |
1 | 1 | Covered | T5,T1,T2 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T2 |
1 | 0 | Covered | T5,T1,T2 |
1 | 1 | Covered | T5,T1,T2 |
Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116905306 |
97075 |
0 |
0 |
T1 |
431044 |
3511 |
0 |
0 |
T2 |
721632 |
732 |
0 |
0 |
T3 |
729564 |
1449 |
0 |
0 |
T4 |
13355 |
0 |
0 |
0 |
T5 |
75771 |
233 |
0 |
0 |
T6 |
642 |
0 |
0 |
0 |
T7 |
439411 |
707 |
0 |
0 |
T8 |
0 |
288 |
0 |
0 |
T9 |
0 |
2046 |
0 |
0 |
T10 |
0 |
51 |
0 |
0 |
T11 |
0 |
33 |
0 |
0 |
T12 |
0 |
1357 |
0 |
0 |
T14 |
2093 |
0 |
0 |
0 |
T15 |
845 |
0 |
0 |
0 |
T16 |
1722 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
15272807 |
95904 |
0 |
0 |
T1 |
335540 |
3512 |
0 |
0 |
T2 |
61390 |
732 |
0 |
0 |
T3 |
56619 |
1013 |
0 |
0 |
T4 |
211 |
0 |
0 |
0 |
T5 |
7465 |
233 |
0 |
0 |
T6 |
186 |
0 |
0 |
0 |
T7 |
27787 |
707 |
0 |
0 |
T8 |
0 |
288 |
0 |
0 |
T9 |
0 |
2046 |
0 |
0 |
T10 |
0 |
51 |
0 |
0 |
T11 |
0 |
33 |
0 |
0 |
T12 |
0 |
1358 |
0 |
0 |
T14 |
616 |
0 |
0 |
0 |
T15 |
270 |
0 |
0 |
0 |
T16 |
468 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T2 |
1 | 0 | Covered | T5,T1,T2 |
1 | 1 | Covered | T5,T1,T2 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T2 |
1 | 0 | Covered | T5,T1,T2 |
1 | 1 | Covered | T5,T1,T2 |
Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500802361 |
119936 |
0 |
0 |
T1 |
183653 |
4177 |
0 |
0 |
T2 |
309118 |
900 |
0 |
0 |
T3 |
316068 |
1642 |
0 |
0 |
T4 |
96256 |
0 |
0 |
0 |
T5 |
355081 |
315 |
0 |
0 |
T6 |
2667 |
0 |
0 |
0 |
T7 |
191992 |
874 |
0 |
0 |
T8 |
0 |
372 |
0 |
0 |
T9 |
0 |
2771 |
0 |
0 |
T10 |
0 |
51 |
0 |
0 |
T11 |
0 |
30 |
0 |
0 |
T12 |
0 |
2024 |
0 |
0 |
T14 |
8818 |
0 |
0 |
0 |
T15 |
3626 |
0 |
0 |
0 |
T16 |
6695 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
15305506 |
119114 |
0 |
0 |
T1 |
319164 |
4005 |
0 |
0 |
T2 |
61558 |
900 |
0 |
0 |
T3 |
60097 |
1642 |
0 |
0 |
T4 |
211 |
0 |
0 |
0 |
T5 |
7549 |
315 |
0 |
0 |
T6 |
186 |
0 |
0 |
0 |
T7 |
27955 |
874 |
0 |
0 |
T8 |
0 |
372 |
0 |
0 |
T9 |
0 |
2771 |
0 |
0 |
T10 |
0 |
51 |
0 |
0 |
T11 |
0 |
30 |
0 |
0 |
T12 |
0 |
2024 |
0 |
0 |
T14 |
616 |
0 |
0 |
0 |
T15 |
270 |
0 |
0 |
0 |
T16 |
468 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T2 |
1 | 0 | Covered | T5,T1,T2 |
1 | 1 | Covered | T5,T1,T2 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T5,T1,T2 |
1 | 0 | Covered | T5,T1,T2 |
1 | 1 | Covered | T5,T1,T2 |
Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
240260609 |
117973 |
0 |
0 |
T1 |
876993 |
3848 |
0 |
0 |
T2 |
145499 |
779 |
0 |
0 |
T3 |
152291 |
1666 |
0 |
0 |
T4 |
46203 |
0 |
0 |
0 |
T5 |
156041 |
240 |
0 |
0 |
T6 |
1280 |
0 |
0 |
0 |
T7 |
912936 |
834 |
0 |
0 |
T8 |
0 |
408 |
0 |
0 |
T9 |
0 |
2752 |
0 |
0 |
T10 |
0 |
51 |
0 |
0 |
T11 |
0 |
28 |
0 |
0 |
T12 |
0 |
2058 |
0 |
0 |
T14 |
4233 |
0 |
0 |
0 |
T15 |
1735 |
0 |
0 |
0 |
T16 |
3213 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
15326783 |
117945 |
0 |
0 |
T1 |
336176 |
3849 |
0 |
0 |
T2 |
61438 |
779 |
0 |
0 |
T3 |
60121 |
1666 |
0 |
0 |
T4 |
211 |
0 |
0 |
0 |
T5 |
7489 |
240 |
0 |
0 |
T6 |
186 |
0 |
0 |
0 |
T7 |
27919 |
834 |
0 |
0 |
T8 |
0 |
408 |
0 |
0 |
T9 |
0 |
2752 |
0 |
0 |
T10 |
0 |
51 |
0 |
0 |
T11 |
0 |
28 |
0 |
0 |
T12 |
0 |
2058 |
0 |
0 |
T14 |
616 |
0 |
0 |
0 |
T15 |
270 |
0 |
0 |
0 |
T16 |
468 |
0 |
0 |
0 |