Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	159324155	5013320	0	0
clk_enables_rd_A	159324155	44253	0	0
clk_hints_rd_A	159324155	39273	0	0
extclk_ctrl_rd_A	159324155	49876	0	0
extclk_ctrl_regwen_rd_A	159324155	39008	0	0
jitter_enable_rd_A	159324155	55802	0	0
jitter_regwen_rd_A	159324155	42793	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159324155	5013320	0	0
T1	444966	127950	0	0
T2	777296	29961	0	0
T3	311479	107837	0	0
T4	62564	0	0	0
T6	2588	0	0	0
T7	192592	65026	0	0
T8	106053	52915	0	0
T9	0	98297	0	0
T12	0	104663	0	0
T13	0	21677	0	0
T14	2381	0	0	0
T15	1002	0	0	0
T16	1673	0	0	0
T17	0	197779	0	0
T22	0	251374	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159324155	44253	0	0
T1	444966	4631	0	0
T2	777296	0	0	0
T3	311479	0	0	0
T4	62564	0	0	0
T6	2588	0	0	0
T7	192592	0	0	0
T8	106053	0	0	0
T9	0	2302	0	0
T12	0	2276	0	0
T14	2381	0	0	0
T15	1002	0	0	0
T16	1673	0	0	0
T66	0	3972	0	0
T113	0	3	0	0
T114	0	2	0	0
T115	0	830	0	0
T116	0	2759	0	0
T117	0	13	0	0
T118	0	3	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159324155	39273	0	0
T1	444966	4160	0	0
T2	777296	0	0	0
T3	311479	0	0	0
T4	62564	0	0	0
T6	2588	0	0	0
T7	192592	0	0	0
T8	106053	0	0	0
T9	0	1938	0	0
T12	0	1892	0	0
T14	2381	0	0	0
T15	1002	0	0	0
T16	1673	0	0	0
T66	0	3377	0	0
T113	0	6	0	0
T114	0	2	0	0
T115	0	843	0	0
T116	0	2430	0	0
T117	0	10	0	0
T119	0	9	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159324155	49876	0	0
T1	444966	5399	0	0
T2	777296	0	0	0
T3	311479	0	0	0
T4	62564	0	0	0
T5	51390	58	0	0
T6	2588	41	0	0
T7	192592	0	0	0
T9	0	2418	0	0
T14	2381	0	0	0
T15	1002	0	0	0
T16	1673	0	0	0
T32	0	43	0	0
T35	0	43	0	0
T120	0	14	0	0
T121	0	18	0	0
T122	0	35	0	0
T123	0	38	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159324155	39008	0	0
T1	444966	4318	0	0
T2	777296	0	0	0
T3	311479	0	0	0
T4	62564	0	0	0
T6	2588	0	0	0
T7	192592	0	0	0
T8	106053	0	0	0
T9	0	1937	0	0
T12	0	2057	0	0
T14	2381	0	0	0
T15	1002	0	0	0
T16	1673	0	0	0
T66	0	3687	0	0
T115	0	812	0	0
T116	0	2696	0	0
T124	0	17	0	0
T125	0	1304	0	0
T126	0	35	0	0
T127	0	46	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159324155	55802	0	0
T1	444966	5774	0	0
T2	777296	0	0	0
T3	311479	0	0	0
T4	62564	0	0	0
T6	2588	0	0	0
T7	192592	0	0	0
T8	106053	0	0	0
T9	0	2477	0	0
T12	0	2996	0	0
T14	2381	0	0	0
T15	1002	0	0	0
T16	1673	0	0	0
T66	0	4828	0	0
T113	0	115	0	0
T114	0	86	0	0
T115	0	1319	0	0
T116	0	3025	0	0
T117	0	266	0	0
T119	0	97	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159324155	42793	0	0
T1	444966	4563	0	0
T2	777296	0	0	0
T3	311479	0	0	0
T4	62564	0	0	0
T6	2588	0	0	0
T7	192592	0	0	0
T8	106053	0	0	0
T9	0	2084	0	0
T12	0	2081	0	0
T14	2381	0	0	0
T15	1002	0	0	0
T16	1673	0	0	0
T66	0	4157	0	0
T115	0	841	0	0
T116	0	2993	0	0
T125	0	1673	0	0
T128	0	3002	0	0
T129	0	4677	0	0
T130	0	2010	0	0