Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T6

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	469059322	4565	0	0
g_div2.Div2Whole_A	469059322	5307	0	0
g_div4.Div4Stepped_A	233812246	4452	0	0
g_div4.Div4Whole_A	233812246	5041	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469059322	4565	0	0
T1	172337	132	0	0
T2	288680	31	0	0
T3	293665	48	0	0
T4	92403	0	0	0
T5	300548	12	0	0
T6	2561	1	0	0
T7	176242	31	0	0
T8	0	16	0	0
T9	0	87	0	0
T14	8466	0	0	0
T15	3489	0	0	0
T16	6427	7	0	0
T32	0	5	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469059322	5307	0	0
T1	172337	133	0	0
T2	288680	35	0	0
T3	293665	70	0	0
T4	92403	0	0	0
T5	300548	12	0	0
T6	2561	7	0	0
T7	176242	40	0	0
T8	0	20	0	0
T9	0	94	0	0
T14	8466	0	0	0
T15	3489	0	0	0
T16	6427	8	0	0
T32	0	11	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233812246	4452	0	0
T1	862091	132	0	0
T2	144327	31	0	0
T3	145914	47	0	0
T4	26714	0	0	0
T5	151545	12	0	0
T6	1284	1	0	0
T7	878832	29	0	0
T8	0	16	0	0
T9	0	86	0	0
T14	4187	0	0	0
T15	1691	0	0	0
T16	3447	7	0	0
T32	0	4	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233812246	5041	0	0
T1	862091	133	0	0
T2	144327	35	0	0
T3	145914	58	0	0
T4	26714	0	0	0
T5	151545	12	0	0
T6	1284	6	0	0
T7	878832	33	0	0
T8	0	20	0	0
T9	0	94	0	0
T14	4187	0	0	0
T15	1691	0	0	0
T16	3447	7	0	0
T32	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	469059322	4565	0	0
g_div2.Div2Whole_A	469059322	5307	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469059322	4565	0	0
T1	172337	132	0	0
T2	288680	31	0	0
T3	293665	48	0	0
T4	92403	0	0	0
T5	300548	12	0	0
T6	2561	1	0	0
T7	176242	31	0	0
T8	0	16	0	0
T9	0	87	0	0
T14	8466	0	0	0
T15	3489	0	0	0
T16	6427	7	0	0
T32	0	5	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469059322	5307	0	0
T1	172337	133	0	0
T2	288680	35	0	0
T3	293665	70	0	0
T4	92403	0	0	0
T5	300548	12	0	0
T6	2561	7	0	0
T7	176242	40	0	0
T8	0	20	0	0
T9	0	94	0	0
T14	8466	0	0	0
T15	3489	0	0	0
T16	6427	8	0	0
T32	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	233812246	4452	0	0
g_div4.Div4Whole_A	233812246	5041	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233812246	4452	0	0
T1	862091	132	0	0
T2	144327	31	0	0
T3	145914	47	0	0
T4	26714	0	0	0
T5	151545	12	0	0
T6	1284	1	0	0
T7	878832	29	0	0
T8	0	16	0	0
T9	0	86	0	0
T14	4187	0	0	0
T15	1691	0	0	0
T16	3447	7	0	0
T32	0	4	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233812246	5041	0	0
T1	862091	133	0	0
T2	144327	35	0	0
T3	145914	58	0	0
T4	26714	0	0	0
T5	151545	12	0	0
T6	1284	6	0	0
T7	878832	33	0	0
T8	0	20	0	0
T9	0	94	0	0
T14	4187	0	0	0
T15	1691	0	0	0
T16	3447	7	0	0
T32	0	10	0	0