Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	475158957	510	0	0
StatusRise_A	475158957	510	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475158957	510	0	0
T3	934437	0	0	0
T7	577776	0	0	0
T8	318159	0	0	0
T9	952479	0	0	0
T10	82245	0	0	0
T15	3006	9	0	0
T16	5019	0	0	0
T18	3363	0	0	0
T26	0	10	0	0
T27	0	11	0	0
T28	87942	0	0	0
T49	2187	0	0	0
T131	0	13	0	0
T132	0	9	0	0
T133	0	3	0	0
T134	0	6	0	0
T135	0	5	0	0
T136	0	14	0	0
T137	0	8	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475158957	510	0	0
T3	934437	0	0	0
T7	577776	0	0	0
T8	318159	0	0	0
T9	952479	0	0	0
T10	82245	0	0	0
T15	3006	9	0	0
T16	5019	0	0	0
T18	3363	0	0	0
T26	0	10	0	0
T27	0	11	0	0
T28	87942	0	0	0
T49	2187	0	0	0
T131	0	13	0	0
T132	0	9	0	0
T133	0	3	0	0
T134	0	6	0	0
T135	0	5	0	0
T136	0	14	0	0
T137	0	8	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	158386319	164	0	0
StatusRise_A	158386319	164	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158386319	164	0	0
T3	311479	0	0	0
T7	192592	0	0	0
T8	106053	0	0	0
T9	317493	0	0	0
T10	27415	0	0	0
T15	1002	3	0	0
T16	1673	0	0	0
T18	1121	0	0	0
T26	0	3	0	0
T27	0	3	0	0
T28	29314	0	0	0
T49	729	0	0	0
T131	0	4	0	0
T132	0	2	0	0
T133	0	1	0	0
T134	0	2	0	0
T135	0	2	0	0
T136	0	5	0	0
T137	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158386319	164	0	0
T3	311479	0	0	0
T7	192592	0	0	0
T8	106053	0	0	0
T9	317493	0	0	0
T10	27415	0	0	0
T15	1002	3	0	0
T16	1673	0	0	0
T18	1121	0	0	0
T26	0	3	0	0
T27	0	3	0	0
T28	29314	0	0	0
T49	729	0	0	0
T131	0	4	0	0
T132	0	2	0	0
T133	0	1	0	0
T134	0	2	0	0
T135	0	2	0	0
T136	0	5	0	0
T137	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	158386319	168	0	0
StatusRise_A	158386319	168	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158386319	168	0	0
T3	311479	0	0	0
T7	192592	0	0	0
T8	106053	0	0	0
T9	317493	0	0	0
T10	27415	0	0	0
T15	1002	3	0	0
T16	1673	0	0	0
T18	1121	0	0	0
T26	0	3	0	0
T27	0	3	0	0
T28	29314	0	0	0
T49	729	0	0	0
T131	0	5	0	0
T132	0	4	0	0
T133	0	1	0	0
T134	0	2	0	0
T135	0	2	0	0
T136	0	5	0	0
T137	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158386319	168	0	0
T3	311479	0	0	0
T7	192592	0	0	0
T8	106053	0	0	0
T9	317493	0	0	0
T10	27415	0	0	0
T15	1002	3	0	0
T16	1673	0	0	0
T18	1121	0	0	0
T26	0	3	0	0
T27	0	3	0	0
T28	29314	0	0	0
T49	729	0	0	0
T131	0	5	0	0
T132	0	4	0	0
T133	0	1	0	0
T134	0	2	0	0
T135	0	2	0	0
T136	0	5	0	0
T137	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	158386319	178	0	0
StatusRise_A	158386319	178	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158386319	178	0	0
T3	311479	0	0	0
T7	192592	0	0	0
T8	106053	0	0	0
T9	317493	0	0	0
T10	27415	0	0	0
T15	1002	3	0	0
T16	1673	0	0	0
T18	1121	0	0	0
T26	0	4	0	0
T27	0	5	0	0
T28	29314	0	0	0
T49	729	0	0	0
T131	0	4	0	0
T132	0	3	0	0
T133	0	1	0	0
T134	0	2	0	0
T135	0	1	0	0
T136	0	4	0	0
T137	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158386319	178	0	0
T3	311479	0	0	0
T7	192592	0	0	0
T8	106053	0	0	0
T9	317493	0	0	0
T10	27415	0	0	0
T15	1002	3	0	0
T16	1673	0	0	0
T18	1121	0	0	0
T26	0	4	0	0
T27	0	5	0	0
T28	29314	0	0	0
T49	729	0	0	0
T131	0	4	0	0
T132	0	3	0	0
T133	0	1	0	0
T134	0	2	0	0
T135	0	1	0	0
T136	0	4	0	0
T137	0	3	0	0