Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T4
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	50418	0	0
CgEnOn_A	2147483647	40685	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50418	0	0
T1	3077077	485	0	0
T2	2536610	260	0	0
T3	5998404	541	0	0
T4	563699	48	0	0
T5	2104228	54	0	0
T6	16433	3	0	0
T7	6845614	173	0	0
T8	3167797	17	0	0
T9	2756599	66	0	0
T10	489201	0	0	0
T14	54249	14	0	0
T15	38964	30	0	0
T16	73230	3	0	0
T17	0	5	0	0
T18	20721	0	0	0
T26	0	15	0	0
T27	0	15	0	0
T28	127270	0	0	0
T34	0	6	0	0
T49	13998	0	0	0
T131	0	25	0	0
T132	0	20	0	0
T133	0	5	0	0
T134	0	10	0	0
T138	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	40685	0	0
T1	3077077	253	0	0
T2	2536610	114	0	0
T3	5998404	260	0	0
T4	563699	0	0	0
T5	2104228	4	0	0
T6	16433	0	0	0
T7	6845614	70	0	0
T8	3167797	14	0	0
T9	2756599	205	0	0
T10	489201	0	0	0
T14	54249	0	0	0
T15	38964	21	0	0
T16	73230	0	0	0
T17	0	4	0	0
T18	20721	0	0	0
T26	0	15	0	0
T27	0	15	0	0
T28	127270	0	0	0
T49	13998	18	0	0
T131	0	25	0	0
T132	0	20	0	0
T133	0	5	0	0
T134	0	10	0	0
T135	0	2	0	0
T136	0	5	0	0
T137	0	2	0	0
T138	0	4	0	0
T139	0	20	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T4
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	233811823	177	0	0
CgEnOn_A	233811823	177	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233811823	177	0	0
T3	145914	1	0	0
T7	878831	0	0	0
T8	979837	0	0	0
T9	275885	0	0	0
T10	50587	0	0	0
T15	1691	3	0	0
T16	3446	0	0	0
T17	0	1	0	0
T18	2114	0	0	0
T26	0	3	0	0
T27	0	3	0	0
T28	10166	0	0	0
T49	1413	0	0	0
T131	0	5	0	0
T132	0	4	0	0
T133	0	1	0	0
T134	0	2	0	0
T138	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233811823	177	0	0
T3	145914	1	0	0
T7	878831	0	0	0
T8	979837	0	0	0
T9	275885	0	0	0
T10	50587	0	0	0
T15	1691	3	0	0
T16	3446	0	0	0
T17	0	1	0	0
T18	2114	0	0	0
T26	0	3	0	0
T27	0	3	0	0
T28	10166	0	0	0
T49	1413	0	0	0
T131	0	5	0	0
T132	0	4	0	0
T133	0	1	0	0
T134	0	2	0	0
T138	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T4
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	116905306	177	0	0
CgEnOn_A	116905306	177	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116905306	177	0	0
T3	729564	1	0	0
T7	439411	0	0	0
T8	489915	0	0	0
T9	137941	0	0	0
T10	25293	0	0	0
T15	845	3	0	0
T16	1722	0	0	0
T17	0	1	0	0
T18	1057	0	0	0
T26	0	3	0	0
T27	0	3	0	0
T28	5082	0	0	0
T49	707	0	0	0
T131	0	5	0	0
T132	0	4	0	0
T133	0	1	0	0
T134	0	2	0	0
T138	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116905306	177	0	0
T3	729564	1	0	0
T7	439411	0	0	0
T8	489915	0	0	0
T9	137941	0	0	0
T10	25293	0	0	0
T15	845	3	0	0
T16	1722	0	0	0
T17	0	1	0	0
T18	1057	0	0	0
T26	0	3	0	0
T27	0	3	0	0
T28	5082	0	0	0
T49	707	0	0	0
T131	0	5	0	0
T132	0	4	0	0
T133	0	1	0	0
T134	0	2	0	0
T138	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T4
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	116905306	177	0	0
CgEnOn_A	116905306	177	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116905306	177	0	0
T3	729564	1	0	0
T7	439411	0	0	0
T8	489915	0	0	0
T9	137941	0	0	0
T10	25293	0	0	0
T15	845	3	0	0
T16	1722	0	0	0
T17	0	1	0	0
T18	1057	0	0	0
T26	0	3	0	0
T27	0	3	0	0
T28	5082	0	0	0
T49	707	0	0	0
T131	0	5	0	0
T132	0	4	0	0
T133	0	1	0	0
T134	0	2	0	0
T138	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116905306	177	0	0
T3	729564	1	0	0
T7	439411	0	0	0
T8	489915	0	0	0
T9	137941	0	0	0
T10	25293	0	0	0
T15	845	3	0	0
T16	1722	0	0	0
T17	0	1	0	0
T18	1057	0	0	0
T26	0	3	0	0
T27	0	3	0	0
T28	5082	0	0	0
T49	707	0	0	0
T131	0	5	0	0
T132	0	4	0	0
T133	0	1	0	0
T134	0	2	0	0
T138	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T4
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	116905306	177	0	0
CgEnOn_A	116905306	177	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116905306	177	0	0
T3	729564	1	0	0
T7	439411	0	0	0
T8	489915	0	0	0
T9	137941	0	0	0
T10	25293	0	0	0
T15	845	3	0	0
T16	1722	0	0	0
T17	0	1	0	0
T18	1057	0	0	0
T26	0	3	0	0
T27	0	3	0	0
T28	5082	0	0	0
T49	707	0	0	0
T131	0	5	0	0
T132	0	4	0	0
T133	0	1	0	0
T134	0	2	0	0
T138	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116905306	177	0	0
T3	729564	1	0	0
T7	439411	0	0	0
T8	489915	0	0	0
T9	137941	0	0	0
T10	25293	0	0	0
T15	845	3	0	0
T16	1722	0	0	0
T17	0	1	0	0
T18	1057	0	0	0
T26	0	3	0	0
T27	0	3	0	0
T28	5082	0	0	0
T49	707	0	0	0
T131	0	5	0	0
T132	0	4	0	0
T133	0	1	0	0
T134	0	2	0	0
T138	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T4
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	469058879	177	0	0
CgEnOn_A	469058879	169	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469058879	177	0	0
T3	293665	1	0	0
T7	176242	0	0	0
T8	197279	0	0	0
T9	551543	0	0	0
T10	101226	0	0	0
T15	3488	3	0	0
T16	6427	0	0	0
T17	0	1	0	0
T18	4308	0	0	0
T26	0	3	0	0
T27	0	3	0	0
T28	28425	0	0	0
T49	2920	0	0	0
T131	0	5	0	0
T132	0	4	0	0
T133	0	1	0	0
T134	0	2	0	0
T138	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469058879	169	0	0
T3	293665	0	0	0
T7	176242	0	0	0
T8	197279	0	0	0
T9	551543	0	0	0
T10	101226	0	0	0
T15	3488	3	0	0
T16	6427	0	0	0
T18	4308	0	0	0
T26	0	3	0	0
T27	0	3	0	0
T28	28425	0	0	0
T49	2920	0	0	0
T131	0	5	0	0
T132	0	4	0	0
T133	0	1	0	0
T134	0	2	0	0
T135	0	2	0	0
T136	0	5	0	0
T137	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T4
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	500802361	167	0	0
CgEnOn_A	500802361	165	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500802361	167	0	0
T3	316068	0	0	0
T7	191992	0	0	0
T8	209706	0	0	0
T9	611142	0	0	0
T10	105447	0	0	0
T15	3626	3	0	0
T16	6695	0	0	0
T18	4487	0	0	0
T26	0	3	0	0
T27	0	3	0	0
T28	29610	0	0	0
T49	3042	0	0	0
T131	0	4	0	0
T132	0	2	0	0
T133	0	1	0	0
T134	0	2	0	0
T135	0	2	0	0
T136	0	5	0	0
T137	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500802361	165	0	0
T3	316068	0	0	0
T7	191992	0	0	0
T8	209706	0	0	0
T9	611142	0	0	0
T10	105447	0	0	0
T15	3626	3	0	0
T16	6695	0	0	0
T18	4487	0	0	0
T26	0	3	0	0
T27	0	3	0	0
T28	29610	0	0	0
T49	3042	0	0	0
T131	0	4	0	0
T132	0	2	0	0
T133	0	1	0	0
T134	0	2	0	0
T135	0	2	0	0
T136	0	5	0	0
T137	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T4
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	500802361	167	0	0
CgEnOn_A	500802361	165	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500802361	167	0	0
T3	316068	0	0	0
T7	191992	0	0	0
T8	209706	0	0	0
T9	611142	0	0	0
T10	105447	0	0	0
T15	3626	3	0	0
T16	6695	0	0	0
T18	4487	0	0	0
T26	0	3	0	0
T27	0	3	0	0
T28	29610	0	0	0
T49	3042	0	0	0
T131	0	4	0	0
T132	0	2	0	0
T133	0	1	0	0
T134	0	2	0	0
T135	0	2	0	0
T136	0	5	0	0
T137	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500802361	165	0	0
T3	316068	0	0	0
T7	191992	0	0	0
T8	209706	0	0	0
T9	611142	0	0	0
T10	105447	0	0	0
T15	3626	3	0	0
T16	6695	0	0	0
T18	4487	0	0	0
T26	0	3	0	0
T27	0	3	0	0
T28	29610	0	0	0
T49	3042	0	0	0
T131	0	4	0	0
T132	0	2	0	0
T133	0	1	0	0
T134	0	2	0	0
T135	0	2	0	0
T136	0	5	0	0
T137	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T4
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	240260609	178	0	0
CgEnOn_A	240260609	178	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240260609	178	0	0
T3	152291	0	0	0
T7	912936	0	0	0
T8	101524	0	0	0
T9	293064	0	0	0
T10	50615	0	0	0
T15	1735	3	0	0
T16	3213	0	0	0
T18	2154	0	0	0
T26	0	4	0	0
T27	0	5	0	0
T28	14213	0	0	0
T49	1460	0	0	0
T131	0	4	0	0
T132	0	3	0	0
T133	0	1	0	0
T134	0	2	0	0
T135	0	1	0	0
T136	0	4	0	0
T137	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240260609	178	0	0
T3	152291	0	0	0
T7	912936	0	0	0
T8	101524	0	0	0
T9	293064	0	0	0
T10	50615	0	0	0
T15	1735	3	0	0
T16	3213	0	0	0
T18	2154	0	0	0
T26	0	4	0	0
T27	0	5	0	0
T28	14213	0	0	0
T49	1460	0	0	0
T131	0	4	0	0
T132	0	3	0	0
T133	0	1	0	0
T134	0	2	0	0
T135	0	1	0	0
T136	0	4	0	0
T137	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T15,T26,T27
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	116905306	8043	0	0
CgEnOn_A	116905306	5619	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116905306	8043	0	0
T1	431044	136	0	0
T2	721632	60	0	0
T3	729564	140	0	0
T4	13355	16	0	0
T5	75771	8	0	0
T6	642	1	0	0
T7	439411	42	0	0
T14	2093	1	0	0
T15	845	4	0	0
T16	1722	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116905306	5619	0	0
T1	431044	126	0	0
T2	721632	57	0	0
T3	729564	131	0	0
T4	13355	0	0	0
T5	75771	2	0	0
T6	642	0	0	0
T7	439411	36	0	0
T8	0	7	0	0
T9	0	102	0	0
T14	2093	0	0	0
T15	845	3	0	0
T16	1722	0	0	0
T49	0	9	0	0
T139	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T15,T26,T27
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	233811823	8125	0	0
CgEnOn_A	233811823	5701	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233811823	8125	0	0
T1	862091	137	0	0
T2	144327	60	0	0
T3	145914	134	0	0
T4	26714	16	0	0
T5	151544	8	0	0
T6	1283	1	0	0
T7	878831	40	0	0
T14	4186	1	0	0
T15	1691	4	0	0
T16	3446	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233811823	5701	0	0
T1	862091	127	0	0
T2	144327	57	0	0
T3	145914	125	0	0
T4	26714	0	0	0
T5	151544	2	0	0
T6	1283	0	0	0
T7	878831	34	0	0
T8	0	7	0	0
T9	0	103	0	0
T14	4186	0	0	0
T15	1691	3	0	0
T16	3446	0	0	0
T49	0	9	0	0
T139	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T15,T26,T27
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	469058879	8131	0	0
CgEnOn_A	469058879	5699	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469058879	8131	0	0
T1	172337	137	0	0
T2	288680	58	0	0
T3	293665	143	0	0
T4	92403	16	0	0
T5	300548	7	0	0
T6	2560	1	0	0
T7	176242	41	0	0
T14	8465	1	0	0
T15	3488	4	0	0
T16	6427	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469058879	5699	0	0
T1	172337	127	0	0
T2	288680	55	0	0
T3	293665	133	0	0
T4	92403	0	0	0
T5	300548	1	0	0
T6	2560	0	0	0
T7	176242	35	0	0
T8	0	7	0	0
T9	0	101	0	0
T14	8465	0	0	0
T15	3488	3	0	0
T16	6427	0	0	0
T49	0	8	0	0
T139	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T15,T26,T27
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	240260609	8081	0	0
CgEnOn_A	240260609	5648	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240260609	8081	0	0
T1	876993	135	0	0
T2	145499	60	0	0
T3	152291	141	0	0
T4	46203	16	0	0
T5	156041	8	0	0
T6	1280	1	0	0
T7	912936	42	0	0
T14	4233	1	0	0
T15	1735	4	0	0
T16	3213	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240260609	5648	0	0
T1	876993	125	0	0
T2	145499	57	0	0
T3	152291	131	0	0
T4	46203	0	0	0
T5	156041	2	0	0
T6	1280	0	0	0
T7	912936	36	0	0
T8	0	7	0	0
T9	0	99	0	0
T14	4233	0	0	0
T15	1735	3	0	0
T16	3213	0	0	0
T49	0	9	0	0
T139	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T4
1	0	Covered	T5,T1,T14
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	500802361	4147	0	0
CgEnOn_A	500802361	4145	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500802361	4147	0	0
T1	183653	75	0	0
T2	309118	82	0	0
T3	316068	119	0	0
T4	96256	0	0	0
T5	355081	31	0	0
T6	2667	0	0	0
T7	191992	50	0	0
T8	0	17	0	0
T9	0	66	0	0
T14	8818	11	0	0
T15	3626	3	0	0
T16	6695	0	0	0
T34	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500802361	4145	0	0
T1	183653	75	0	0
T2	309118	82	0	0
T3	316068	119	0	0
T4	96256	0	0	0
T5	355081	31	0	0
T6	2667	0	0	0
T7	191992	50	0	0
T8	0	17	0	0
T9	0	66	0	0
T14	8818	11	0	0
T15	3626	3	0	0
T16	6695	0	0	0
T34	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T4
1	0	Covered	T5,T1,T14
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	500802361	4129	0	0
CgEnOn_A	500802361	4127	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500802361	4129	0	0
T1	183653	68	0	0
T2	309118	69	0	0
T3	316068	108	0	0
T4	96256	0	0	0
T5	355081	27	0	0
T6	2667	0	0	0
T7	191992	44	0	0
T8	0	21	0	0
T9	0	69	0	0
T14	8818	8	0	0
T15	3626	3	0	0
T16	6695	0	0	0
T34	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500802361	4127	0	0
T1	183653	68	0	0
T2	309118	69	0	0
T3	316068	108	0	0
T4	96256	0	0	0
T5	355081	27	0	0
T6	2667	0	0	0
T7	191992	44	0	0
T8	0	21	0	0
T9	0	69	0	0
T14	8818	8	0	0
T15	3626	3	0	0
T16	6695	0	0	0
T34	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T4
1	0	Covered	T5,T1,T14
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	500802361	4197	0	0
CgEnOn_A	500802361	4195	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500802361	4197	0	0
T1	183653	74	0	0
T2	309118	74	0	0
T3	316068	122	0	0
T4	96256	0	0	0
T5	355081	26	0	0
T6	2667	0	0	0
T7	191992	46	0	0
T8	0	23	0	0
T9	0	74	0	0
T14	8818	5	0	0
T15	3626	3	0	0
T16	6695	0	0	0
T34	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500802361	4195	0	0
T1	183653	74	0	0
T2	309118	74	0	0
T3	316068	122	0	0
T4	96256	0	0	0
T5	355081	26	0	0
T6	2667	0	0	0
T7	191992	46	0	0
T8	0	23	0	0
T9	0	74	0	0
T14	8818	5	0	0
T15	3626	3	0	0
T16	6695	0	0	0
T34	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T4
1	0	Covered	T5,T1,T14
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	500802361	4168	0	0
CgEnOn_A	500802361	4166	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500802361	4168	0	0
T1	183653	78	0	0
T2	309118	78	0	0
T3	316068	123	0	0
T4	96256	0	0	0
T5	355081	25	0	0
T6	2667	0	0	0
T7	191992	49	0	0
T8	0	14	0	0
T9	0	62	0	0
T14	8818	8	0	0
T15	3626	3	0	0
T16	6695	0	0	0
T34	0	8	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500802361	4166	0	0
T1	183653	78	0	0
T2	309118	78	0	0
T3	316068	123	0	0
T4	96256	0	0	0
T5	355081	25	0	0
T6	2667	0	0	0
T7	191992	49	0	0
T8	0	14	0	0
T9	0	62	0	0
T14	8818	8	0	0
T15	3626	3	0	0
T16	6695	0	0	0
T34	0	8	0	0