Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	296495	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1377107

1

T6

41

T7

2

T8

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	428861	1			T6	68		T8	7		T24	12
values[0x0]	577057	1			T6	30		T7	5		T8	10
values[0x1]	667684	1			T6	21		T7	4		T8	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	177242	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1496360

1

T6

50

T7

5

T8

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6305	1			T7	2		T2	2		T23	2
valid_sources[0x01]	6501	1			T6	1		T12	227		T72	1
valid_sources[0x02]	7126	1			T32	3		T12	174		T29	2
valid_sources[0x03]	6259	1			T7	1		T26	1		T21	8
valid_sources[0x04]	6636	1			T12	244		T29	4		T76	1
valid_sources[0x05]	6649	1			T23	1		T32	3		T12	199
valid_sources[0x06]	6681	1			T32	1		T33	1		T12	164
valid_sources[0x07]	6561	1			T32	2		T12	209		T73	2
valid_sources[0x08]	6506	1			T7	2		T32	2		T12	192
valid_sources[0x09]	6481	1			T6	1		T26	1		T32	2
valid_sources[0x0a]	7450	1			T6	2		T2	4		T3	2
valid_sources[0x0b]	6112	1			T23	1		T32	3		T12	202
valid_sources[0x0c]	6337	1			T2	2		T12	224		T43	1
valid_sources[0x0d]	6642	1			T6	1		T8	4		T21	1
valid_sources[0x0e]	6336	1			T6	1		T32	4		T12	160
valid_sources[0x0f]	5973	1			T32	1		T12	210		T73	1
valid_sources[0x10]	6602	1			T8	1		T25	1		T12	168
valid_sources[0x11]	6446	1			T26	4		T32	3		T12	179
valid_sources[0x12]	5952	1			T32	1		T12	178		T29	3
valid_sources[0x13]	6306	1			T1	3		T3	1		T32	3
valid_sources[0x14]	7707	1			T26	1		T23	1		T12	220
valid_sources[0x15]	6587	1			T6	1		T32	4		T12	192
valid_sources[0x16]	6374	1			T1	11		T2	8		T3	3
valid_sources[0x17]	6083	1			T6	2		T32	1		T12	222
valid_sources[0x18]	6235	1			T6	1		T32	4		T12	164
valid_sources[0x19]	6386	1			T3	4		T23	1		T32	1
valid_sources[0x1a]	6885	1			T1	6		T23	1		T32	2
valid_sources[0x1b]	8177	1			T23	1		T12	196		T29	3
valid_sources[0x1c]	6762	1			T26	1		T2	2		T12	207
valid_sources[0x1d]	6752	1			T3	1		T32	1		T12	200
valid_sources[0x1e]	6644	1			T6	1		T1	15		T2	16
valid_sources[0x1f]	6545	1			T6	2		T32	4		T12	215
valid_sources[0x20]	6733	1			T6	2		T26	1		T1	13
valid_sources[0x21]	6224	1			T1	3		T32	2		T12	157
valid_sources[0x22]	6306	1			T19	49		T2	8		T32	2
valid_sources[0x23]	6429	1			T1	12		T32	2		T12	195
valid_sources[0x24]	6286	1			T27	2		T32	2		T33	1
valid_sources[0x25]	6515	1			T6	5		T23	1		T33	2
valid_sources[0x26]	6771	1			T32	1		T12	187		T29	1
valid_sources[0x27]	6570	1			T2	7		T12	159		T43	1
valid_sources[0x28]	6914	1			T6	1		T12	203		T72	2
valid_sources[0x29]	6160	1			T26	1		T23	1		T33	1
valid_sources[0x2a]	6498	1			T32	4		T12	184		T35	1
valid_sources[0x2b]	6447	1			T3	2		T12	198		T35	2
valid_sources[0x2c]	6448	1			T6	1		T32	1		T12	191
valid_sources[0x2d]	6218	1			T26	1		T32	1		T12	225
valid_sources[0x2e]	6814	1			T27	2		T2	1		T32	3
valid_sources[0x2f]	6747	1			T6	1		T32	3		T12	258
valid_sources[0x30]	6398	1			T12	203		T38	1		T194	2
valid_sources[0x31]	6668	1			T6	1		T2	3		T3	1
valid_sources[0x32]	6336	1			T26	1		T2	3		T12	177
valid_sources[0x33]	6435	1			T26	1		T32	2		T12	205
valid_sources[0x34]	6339	1			T3	2		T23	2		T32	2
valid_sources[0x35]	6472	1			T6	4		T1	1		T23	1
valid_sources[0x36]	6326	1			T6	1		T2	3		T3	2
valid_sources[0x37]	6789	1			T6	1		T32	1		T12	218
valid_sources[0x38]	6387	1			T12	211		T35	5		T38	3
valid_sources[0x39]	6039	1			T6	1		T2	2		T23	2
valid_sources[0x3a]	6488	1			T3	1		T12	210		T72	1
valid_sources[0x3b]	7189	1			T1	30		T32	2		T12	184
valid_sources[0x3c]	6533	1			T2	2		T3	2		T12	197
valid_sources[0x3d]	6512	1			T6	1		T12	207		T72	1
valid_sources[0x3e]	6208	1			T6	1		T1	1		T12	180
valid_sources[0x3f]	6201	1			T6	1		T12	185		T29	1
valid_sources[0x40]	6485	1			T6	1		T2	1		T3	1
valid_sources[0x41]	6581	1			T7	1		T2	2		T32	2
valid_sources[0x42]	6354	1			T2	15		T23	1		T32	2
valid_sources[0x43]	6101	1			T26	2		T32	4		T12	223
valid_sources[0x44]	6158	1			T6	1		T1	20		T23	1
valid_sources[0x45]	7014	1			T5	199		T12	186		T43	1
valid_sources[0x46]	6663	1			T32	1		T12	235		T29	3
valid_sources[0x47]	6232	1			T26	1		T12	207		T38	1
valid_sources[0x48]	5971	1			T25	1		T27	1		T23	1
valid_sources[0x49]	7432	1			T2	4		T12	225		T43	1
valid_sources[0x4a]	6289	1			T32	1		T12	195		T38	1
valid_sources[0x4b]	6683	1			T26	1		T21	1		T23	1
valid_sources[0x4c]	6178	1			T3	2		T32	2		T12	193
valid_sources[0x4d]	6161	1			T6	2		T32	3		T12	160
valid_sources[0x4e]	6298	1			T6	2		T12	216		T29	1
valid_sources[0x4f]	6328	1			T6	2		T23	1		T32	3
valid_sources[0x50]	6355	1			T1	8		T32	4		T12	186
valid_sources[0x51]	6318	1			T6	2		T26	1		T32	8
valid_sources[0x52]	6421	1			T21	1		T12	233		T29	2
valid_sources[0x53]	6920	1			T6	1		T32	1		T12	234
valid_sources[0x54]	6540	1			T6	2		T23	1		T32	1
valid_sources[0x55]	6228	1			T1	9		T21	1		T2	1
valid_sources[0x56]	6169	1			T27	1		T32	1		T12	166
valid_sources[0x57]	6677	1			T6	1		T12	201		T39	3
valid_sources[0x58]	6215	1			T6	2		T32	3		T12	166
valid_sources[0x59]	6396	1			T6	1		T23	1		T32	1
valid_sources[0x5a]	6413	1			T1	7		T32	2		T12	196
valid_sources[0x5b]	6139	1			T2	16		T3	2		T12	196
valid_sources[0x5c]	6194	1			T32	1		T12	247		T38	1
valid_sources[0x5d]	6360	1			T6	1		T32	1		T12	148
valid_sources[0x5e]	6465	1			T8	1		T26	2		T2	12
valid_sources[0x5f]	6331	1			T6	2		T26	1		T32	8
valid_sources[0x60]	6436	1			T6	2		T12	243		T29	1
valid_sources[0x61]	6466	1			T1	12		T32	4		T12	195
valid_sources[0x62]	6200	1			T12	180		T29	2		T38	3
valid_sources[0x63]	6380	1			T32	3		T12	214		T29	5
valid_sources[0x64]	6354	1			T12	175		T35	2		T29	2
valid_sources[0x65]	6178	1			T2	23		T32	3		T12	205
valid_sources[0x66]	6340	1			T6	1		T26	1		T12	207
valid_sources[0x67]	6414	1			T23	2		T12	211		T35	1
valid_sources[0x68]	6688	1			T12	233		T29	1		T39	3
valid_sources[0x69]	6962	1			T21	3		T2	12		T3	2
valid_sources[0x6a]	7974	1			T6	1		T3	3		T23	2
valid_sources[0x6b]	6181	1			T26	2		T12	182		T38	1
valid_sources[0x6c]	6158	1			T32	1		T12	244		T29	1
valid_sources[0x6d]	6144	1			T12	189		T35	4		T38	1
valid_sources[0x6e]	6413	1			T12	190		T29	11		T38	2
valid_sources[0x6f]	6431	1			T6	1		T8	2		T26	1
valid_sources[0x70]	6338	1			T2	5		T23	1		T32	2
valid_sources[0x71]	6528	1			T2	6		T32	1		T12	251
valid_sources[0x72]	6588	1			T26	1		T32	2		T12	168
valid_sources[0x73]	6833	1			T6	1		T32	3		T12	196
valid_sources[0x74]	6128	1			T6	1		T2	4		T12	173
valid_sources[0x75]	6443	1			T32	2		T12	225		T72	1
valid_sources[0x76]	6658	1			T6	2		T1	4		T23	1
valid_sources[0x77]	6226	1			T1	2		T21	1		T32	3
valid_sources[0x78]	6419	1			T26	1		T1	1		T12	168
valid_sources[0x79]	6310	1			T27	3		T2	2		T32	2
valid_sources[0x7a]	6165	1			T6	1		T1	4		T2	5
valid_sources[0x7b]	6743	1			T6	2		T21	2		T3	3
valid_sources[0x7c]	6298	1			T6	1		T27	8		T1	9
valid_sources[0x7d]	6505	1			T32	4		T12	206		T72	1
valid_sources[0x7e]	6300	1			T6	2		T32	2		T12	219
valid_sources[0x7f]	6703	1			T3	3		T23	1		T32	2
valid_sources[0x80]	8026	1			T26	1		T32	1		T12	205

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

354664

1

T6

34

T8

3

T24

6

values[0x0]

all_enables

biggest_size

526020

1

T6

5

T7

2

T8

3

values[0x1]

all_enables

biggest_size

496423

1

T6

2

T8

2

T26

3