Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T27,T28,T20
0	1	Covered	T27,T12,T74
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T27,T4,T12
1	0	Covered	T28,T20,T22
1	1	Covered	T6,T7,T8

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	465233978	7585	0	0
GateOpen_A	465233978	13863	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465233978	7585	0	0
T1	301561	0	0	0
T2	432919	0	0	0
T4	286268	0	0	0
T5	189858	0	0	0
T12	0	89	0	0
T19	9037	0	0	0
T20	3635	13	0	0
T21	22096	0	0	0
T22	10265	11	0	0
T27	5055	37	0	0
T28	4314	8	0	0
T29	0	21	0	0
T37	0	4	0	0
T43	0	4	0	0
T74	0	4	0	0
T190	0	15	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465233978	13863	0	0
T1	301561	4	0	0
T4	0	80	0	0
T6	29405	4	0	0
T7	2738	0	0	0
T8	12785	0	0	0
T19	9037	0	0	0
T20	0	17	0	0
T21	0	4	0	0
T24	3828	4	0	0
T25	8557	4	0	0
T26	4582	4	0	0
T27	5055	37	0	0
T28	4314	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T27,T28,T20
0	1	Covered	T27,T12,T74
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T27,T4,T12
1	0	Covered	T28,T20,T22
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	51111787	1829	0	0
GateOpen_A	51111787	3397	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51111787	1829	0	0
T1	33496	0	0	0
T2	48082	0	0	0
T4	22764	0	0	0
T5	19480	0	0	0
T12	0	18	0	0
T19	1024	0	0	0
T20	396	3	0	0
T21	2561	0	0	0
T22	1149	3	0	0
T27	544	8	0	0
T28	474	2	0	0
T29	0	6	0	0
T37	0	1	0	0
T43	0	1	0	0
T74	0	1	0	0
T190	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51111787	3397	0	0
T1	33496	1	0	0
T4	0	20	0	0
T6	3245	1	0	0
T7	298	0	0	0
T8	1496	0	0	0
T19	1024	0	0	0
T20	0	4	0	0
T21	0	1	0	0
T24	419	1	0	0
T25	931	1	0	0
T26	494	1	0	0
T27	544	8	0	0
T28	474	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T27,T28,T20
0	1	Covered	T27,T12,T74
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T27,T4,T12
1	0	Covered	T28,T20,T22
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	102223923	1926	0	0
GateOpen_A	102223923	3494	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102223923	1926	0	0
T1	66991	0	0	0
T2	96163	0	0	0
T4	45528	0	0	0
T5	38959	0	0	0
T12	0	23	0	0
T19	2048	0	0	0
T20	792	3	0	0
T21	5122	0	0	0
T22	2298	3	0	0
T27	1088	11	0	0
T28	948	2	0	0
T29	0	6	0	0
T37	0	1	0	0
T43	0	1	0	0
T74	0	1	0	0
T190	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102223923	3494	0	0
T1	66991	1	0	0
T4	0	20	0	0
T6	6490	1	0	0
T7	596	0	0	0
T8	2993	0	0	0
T19	2048	0	0	0
T20	0	4	0	0
T21	0	1	0	0
T24	838	1	0	0
T25	1860	1	0	0
T26	987	1	0	0
T27	1088	11	0	0
T28	948	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T27,T28,T20
0	1	Covered	T27,T12,T74
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T27,T4,T12
1	0	Covered	T28,T20,T22
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	206049359	1912	0	0
GateOpen_A	206049359	3483	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206049359	1912	0	0
T1	134047	0	0	0
T2	192446	0	0	0
T4	145315	0	0	0
T5	78011	0	0	0
T12	0	24	0	0
T19	3977	0	0	0
T20	1623	3	0	0
T21	9608	0	0	0
T22	4619	3	0	0
T27	2282	8	0	0
T28	1920	2	0	0
T29	0	5	0	0
T37	0	1	0	0
T43	0	1	0	0
T74	0	1	0	0
T190	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206049359	3483	0	0
T1	134047	1	0	0
T4	0	20	0	0
T6	13113	1	0	0
T7	1229	0	0	0
T8	5530	0	0	0
T19	3977	0	0	0
T20	0	4	0	0
T21	0	1	0	0
T24	1714	1	0	0
T25	3844	1	0	0
T26	2067	1	0	0
T27	2282	8	0	0
T28	1920	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T27,T28,T20
0	1	Covered	T27,T12,T74
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T27,T4,T12
1	0	Covered	T28,T20,T22
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	105848909	1918	0	0
GateOpen_A	105848909	3489	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105848909	1918	0	0
T1	67027	0	0	0
T2	96228	0	0	0
T4	72661	0	0	0
T5	53408	0	0	0
T12	0	24	0	0
T19	1988	0	0	0
T20	824	4	0	0
T21	4805	0	0	0
T22	2199	2	0	0
T27	1141	10	0	0
T28	972	2	0	0
T29	0	4	0	0
T37	0	1	0	0
T43	0	1	0	0
T74	0	1	0	0
T190	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105848909	3489	0	0
T1	67027	1	0	0
T4	0	20	0	0
T6	6557	1	0	0
T7	615	0	0	0
T8	2766	0	0	0
T19	1988	0	0	0
T20	0	5	0	0
T21	0	1	0	0
T24	857	1	0	0
T25	1922	1	0	0
T26	1034	1	0	0
T27	1141	10	0	0
T28	972	3	0	0