Unified Coverage Report :: Module :: prim_generic_clock_inv

Module : prim_generic_clock_inv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_inv_0/rtl/prim_generic_clock_inv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_inv.gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_inv.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_div2.u_inv

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_generic_clock_inv

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_inv_0/rtl/prim_generic_clock_inv.sv' or '../src/lowrisc_prim_generic_clock_inv_0/rtl/prim_generic_clock_inv.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28		unreachable
29	1	1