Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_lc_sender
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_clkmgr_byp.u_send 100.00 100.00



Module Instance : tb.dut.u_clkmgr_byp.u_send

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_clkmgr_byp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_lc_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN6611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
32 1 1
66 1 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%