Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	368574215	39710	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368574215	39710	0	0
T1	432875	212	0	0
T2	491160	333	0	0
T3	31120	32	0	0
T4	181645	0	0	0
T5	139075	0	0	0
T12	0	1176	0	0
T13	0	61	0	0
T14	0	1524	0	0
T15	0	2076	0	0
T16	0	1032	0	0
T17	0	209	0	0
T18	0	1105	0	0
T19	10350	0	0	0
T20	4905	0	0	0
T21	6505	0	0	0
T22	5320	0	0	0
T23	11105	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	73714843	6013	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73714843	6013	0	0
T1	86575	31	0	0
T2	98232	50	0	0
T3	6224	6	0	0
T4	36329	0	0	0
T5	27815	0	0	0
T12	0	205	0	0
T13	0	10	0	0
T14	0	198	0	0
T15	0	332	0	0
T16	0	167	0	0
T17	0	27	0	0
T18	0	177	0	0
T19	2070	0	0	0
T20	981	0	0	0
T21	1301	0	0	0
T22	1064	0	0	0
T23	2221	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	73714843	5861	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73714843	5861	0	0
T1	86575	30	0	0
T2	98232	50	0	0
T3	6224	6	0	0
T4	36329	0	0	0
T5	27815	0	0	0
T12	0	205	0	0
T13	0	10	0	0
T14	0	220	0	0
T15	0	327	0	0
T16	0	164	0	0
T17	0	30	0	0
T18	0	177	0	0
T19	2070	0	0	0
T20	981	0	0	0
T21	1301	0	0	0
T22	1064	0	0	0
T23	2221	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	73714843	7957	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73714843	7957	0	0
T1	86575	43	0	0
T2	98232	66	0	0
T3	6224	6	0	0
T4	36329	0	0	0
T5	27815	0	0	0
T12	0	239	0	0
T13	0	13	0	0
T14	0	306	0	0
T15	0	417	0	0
T16	0	209	0	0
T17	0	42	0	0
T18	0	221	0	0
T19	2070	0	0	0
T20	981	0	0	0
T21	1301	0	0	0
T22	1064	0	0	0
T23	2221	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	73714843	7964	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73714843	7964	0	0
T1	86575	40	0	0
T2	98232	66	0	0
T3	6224	6	0	0
T4	36329	0	0	0
T5	27815	0	0	0
T12	0	236	0	0
T13	0	11	0	0
T14	0	298	0	0
T15	0	418	0	0
T16	0	209	0	0
T17	0	42	0	0
T18	0	225	0	0
T19	2070	0	0	0
T20	981	0	0	0
T21	1301	0	0	0
T22	1064	0	0	0
T23	2221	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	73714843	11915	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73714843	11915	0	0
T1	86575	68	0	0
T2	98232	101	0	0
T3	6224	8	0	0
T4	36329	0	0	0
T5	27815	0	0	0
T12	0	291	0	0
T13	0	17	0	0
T14	0	502	0	0
T15	0	582	0	0
T16	0	283	0	0
T17	0	68	0	0
T18	0	305	0	0
T19	2070	0	0	0
T20	981	0	0	0
T21	1301	0	0	0
T22	1064	0	0	0
T23	2221	0	0	0