Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Module :
prim_mubi4_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
Branch Coverage for Module :
prim_mubi4_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Module :
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
21672 |
21672 |
0 |
0 |
T1 |
28 |
28 |
0 |
0 |
T6 |
28 |
28 |
0 |
0 |
T7 |
28 |
28 |
0 |
0 |
T8 |
28 |
28 |
0 |
0 |
T19 |
28 |
28 |
0 |
0 |
T24 |
28 |
28 |
0 |
0 |
T25 |
28 |
28 |
0 |
0 |
T26 |
28 |
28 |
0 |
0 |
T27 |
28 |
28 |
0 |
0 |
T28 |
28 |
28 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
2904387 |
2901739 |
0 |
0 |
T6 |
211334 |
207867 |
0 |
0 |
T7 |
33235 |
29938 |
0 |
0 |
T8 |
89502 |
87499 |
0 |
0 |
T19 |
79271 |
75733 |
0 |
0 |
T24 |
45577 |
43293 |
0 |
0 |
T25 |
61330 |
57890 |
0 |
0 |
T26 |
54029 |
50716 |
0 |
0 |
T27 |
44692 |
40659 |
0 |
0 |
T28 |
38629 |
35904 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442289058 |
430862994 |
0 |
13932 |
T1 |
519450 |
518910 |
0 |
18 |
T6 |
19662 |
19284 |
0 |
18 |
T7 |
7608 |
6756 |
0 |
18 |
T8 |
8292 |
8070 |
0 |
18 |
T19 |
12420 |
11772 |
0 |
18 |
T24 |
10278 |
9696 |
0 |
18 |
T25 |
5526 |
5160 |
0 |
18 |
T26 |
12006 |
11208 |
0 |
18 |
T27 |
6846 |
6138 |
0 |
18 |
T28 |
6360 |
5850 |
0 |
18 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235524186 |
1211636206 |
0 |
16254 |
T1 |
865744 |
864851 |
0 |
21 |
T6 |
74307 |
72902 |
0 |
21 |
T7 |
8884 |
7891 |
0 |
21 |
T8 |
31334 |
30550 |
0 |
21 |
T19 |
24685 |
23402 |
0 |
21 |
T24 |
12275 |
11584 |
0 |
21 |
T25 |
21702 |
20300 |
0 |
21 |
T26 |
14677 |
13701 |
0 |
21 |
T27 |
14067 |
12625 |
0 |
21 |
T28 |
11843 |
10820 |
0 |
21 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235524186 |
116628 |
0 |
0 |
T1 |
865744 |
4 |
0 |
0 |
T5 |
133640 |
0 |
0 |
0 |
T6 |
54640 |
227 |
0 |
0 |
T7 |
5120 |
12 |
0 |
0 |
T8 |
31334 |
78 |
0 |
0 |
T12 |
0 |
505 |
0 |
0 |
T19 |
24685 |
142 |
0 |
0 |
T20 |
3584 |
0 |
0 |
0 |
T21 |
0 |
49 |
0 |
0 |
T23 |
0 |
150 |
0 |
0 |
T24 |
12275 |
44 |
0 |
0 |
T25 |
21702 |
11 |
0 |
0 |
T26 |
14677 |
97 |
0 |
0 |
T27 |
14067 |
57 |
0 |
0 |
T28 |
11843 |
19 |
0 |
0 |
T34 |
0 |
51 |
0 |
0 |
T73 |
0 |
97 |
0 |
0 |
T75 |
0 |
3 |
0 |
0 |
T122 |
0 |
33 |
0 |
0 |
T123 |
0 |
7 |
0 |
0 |
T124 |
0 |
5 |
0 |
0 |
T125 |
0 |
27 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2010078348 |
1977639174 |
0 |
0 |
T1 |
1519193 |
1517939 |
0 |
0 |
T6 |
117365 |
115642 |
0 |
0 |
T7 |
16743 |
15252 |
0 |
0 |
T8 |
49876 |
48840 |
0 |
0 |
T19 |
42166 |
40520 |
0 |
0 |
T24 |
23024 |
21974 |
0 |
0 |
T25 |
34102 |
32391 |
0 |
0 |
T26 |
27346 |
25768 |
0 |
0 |
T27 |
23779 |
21857 |
0 |
0 |
T28 |
20426 |
19195 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T8,T25,T19 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T8,T25,T19 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T8,T25,T19 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T8,T25,T19 |
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T25,T19 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T25,T19 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T25,T19 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T25,T19 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774 |
774 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206048960 |
202175773 |
0 |
0 |
T1 |
134046 |
133912 |
0 |
0 |
T6 |
13113 |
12869 |
0 |
0 |
T7 |
1228 |
1094 |
0 |
0 |
T8 |
5530 |
5395 |
0 |
0 |
T19 |
3977 |
3773 |
0 |
0 |
T24 |
1713 |
1619 |
0 |
0 |
T25 |
3844 |
3599 |
0 |
0 |
T26 |
2067 |
1932 |
0 |
0 |
T27 |
2281 |
2050 |
0 |
0 |
T28 |
1919 |
1757 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206048960 |
202169452 |
0 |
2322 |
T1 |
134046 |
133909 |
0 |
3 |
T6 |
13113 |
12866 |
0 |
3 |
T7 |
1228 |
1091 |
0 |
3 |
T8 |
5530 |
5392 |
0 |
3 |
T19 |
3977 |
3770 |
0 |
3 |
T24 |
1713 |
1616 |
0 |
3 |
T25 |
3844 |
3596 |
0 |
3 |
T26 |
2067 |
1929 |
0 |
3 |
T27 |
2281 |
2047 |
0 |
3 |
T28 |
1919 |
1754 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206048960 |
16892 |
0 |
0 |
T1 |
134046 |
0 |
0 |
0 |
T5 |
78010 |
0 |
0 |
0 |
T8 |
5530 |
23 |
0 |
0 |
T12 |
0 |
213 |
0 |
0 |
T19 |
3977 |
37 |
0 |
0 |
T20 |
1622 |
0 |
0 |
0 |
T21 |
0 |
26 |
0 |
0 |
T23 |
0 |
87 |
0 |
0 |
T24 |
1713 |
0 |
0 |
0 |
T25 |
3844 |
4 |
0 |
0 |
T26 |
2067 |
0 |
0 |
0 |
T27 |
2281 |
0 |
0 |
0 |
T28 |
1919 |
0 |
0 |
0 |
T34 |
0 |
27 |
0 |
0 |
T73 |
0 |
48 |
0 |
0 |
T75 |
0 |
1 |
0 |
0 |
T122 |
0 |
15 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774 |
774 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73714843 |
71817051 |
0 |
0 |
T1 |
86575 |
86488 |
0 |
0 |
T6 |
3277 |
3217 |
0 |
0 |
T7 |
1268 |
1129 |
0 |
0 |
T8 |
1382 |
1348 |
0 |
0 |
T19 |
2070 |
1965 |
0 |
0 |
T24 |
1713 |
1619 |
0 |
0 |
T25 |
921 |
863 |
0 |
0 |
T26 |
2001 |
1871 |
0 |
0 |
T27 |
1141 |
1026 |
0 |
0 |
T28 |
1060 |
978 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73714843 |
71817051 |
0 |
0 |
T1 |
86575 |
86488 |
0 |
0 |
T6 |
3277 |
3217 |
0 |
0 |
T7 |
1268 |
1129 |
0 |
0 |
T8 |
1382 |
1348 |
0 |
0 |
T19 |
2070 |
1965 |
0 |
0 |
T24 |
1713 |
1619 |
0 |
0 |
T25 |
921 |
863 |
0 |
0 |
T26 |
2001 |
1871 |
0 |
0 |
T27 |
1141 |
1026 |
0 |
0 |
T28 |
1060 |
978 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774 |
774 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73714843 |
71817051 |
0 |
0 |
T1 |
86575 |
86488 |
0 |
0 |
T6 |
3277 |
3217 |
0 |
0 |
T7 |
1268 |
1129 |
0 |
0 |
T8 |
1382 |
1348 |
0 |
0 |
T19 |
2070 |
1965 |
0 |
0 |
T24 |
1713 |
1619 |
0 |
0 |
T25 |
921 |
863 |
0 |
0 |
T26 |
2001 |
1871 |
0 |
0 |
T27 |
1141 |
1026 |
0 |
0 |
T28 |
1060 |
978 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73714843 |
71817051 |
0 |
0 |
T1 |
86575 |
86488 |
0 |
0 |
T6 |
3277 |
3217 |
0 |
0 |
T7 |
1268 |
1129 |
0 |
0 |
T8 |
1382 |
1348 |
0 |
0 |
T19 |
2070 |
1965 |
0 |
0 |
T24 |
1713 |
1619 |
0 |
0 |
T25 |
921 |
863 |
0 |
0 |
T26 |
2001 |
1871 |
0 |
0 |
T27 |
1141 |
1026 |
0 |
0 |
T28 |
1060 |
978 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T8,T19,T23 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T8,T19,T23 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T8,T19,T23 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T8,T19,T23 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T19,T23 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T19,T23 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T19,T23 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T19,T23 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774 |
774 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73714843 |
71817051 |
0 |
0 |
T1 |
86575 |
86488 |
0 |
0 |
T6 |
3277 |
3217 |
0 |
0 |
T7 |
1268 |
1129 |
0 |
0 |
T8 |
1382 |
1348 |
0 |
0 |
T19 |
2070 |
1965 |
0 |
0 |
T24 |
1713 |
1619 |
0 |
0 |
T25 |
921 |
863 |
0 |
0 |
T26 |
2001 |
1871 |
0 |
0 |
T27 |
1141 |
1026 |
0 |
0 |
T28 |
1060 |
978 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73714843 |
71810499 |
0 |
2322 |
T1 |
86575 |
86485 |
0 |
3 |
T6 |
3277 |
3214 |
0 |
3 |
T7 |
1268 |
1126 |
0 |
3 |
T8 |
1382 |
1345 |
0 |
3 |
T19 |
2070 |
1962 |
0 |
3 |
T24 |
1713 |
1616 |
0 |
3 |
T25 |
921 |
860 |
0 |
3 |
T26 |
2001 |
1868 |
0 |
3 |
T27 |
1141 |
1023 |
0 |
3 |
T28 |
1060 |
975 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73714843 |
10508 |
0 |
0 |
T1 |
86575 |
0 |
0 |
0 |
T5 |
27815 |
0 |
0 |
0 |
T8 |
1382 |
14 |
0 |
0 |
T12 |
0 |
134 |
0 |
0 |
T19 |
2070 |
7 |
0 |
0 |
T20 |
981 |
0 |
0 |
0 |
T23 |
0 |
26 |
0 |
0 |
T24 |
1713 |
0 |
0 |
0 |
T25 |
921 |
0 |
0 |
0 |
T26 |
2001 |
0 |
0 |
0 |
T27 |
1141 |
0 |
0 |
0 |
T28 |
1060 |
0 |
0 |
0 |
T34 |
0 |
15 |
0 |
0 |
T73 |
0 |
26 |
0 |
0 |
T122 |
0 |
9 |
0 |
0 |
T123 |
0 |
7 |
0 |
0 |
T124 |
0 |
5 |
0 |
0 |
T125 |
0 |
27 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T8,T25,T19 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T8,T25,T19 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T8,T25,T19 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T8,T25,T19 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T25,T19 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T25,T19 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T25,T19 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T25,T19 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774 |
774 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73714843 |
71817051 |
0 |
0 |
T1 |
86575 |
86488 |
0 |
0 |
T6 |
3277 |
3217 |
0 |
0 |
T7 |
1268 |
1129 |
0 |
0 |
T8 |
1382 |
1348 |
0 |
0 |
T19 |
2070 |
1965 |
0 |
0 |
T24 |
1713 |
1619 |
0 |
0 |
T25 |
921 |
863 |
0 |
0 |
T26 |
2001 |
1871 |
0 |
0 |
T27 |
1141 |
1026 |
0 |
0 |
T28 |
1060 |
978 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73714843 |
71810499 |
0 |
2322 |
T1 |
86575 |
86485 |
0 |
3 |
T6 |
3277 |
3214 |
0 |
3 |
T7 |
1268 |
1126 |
0 |
3 |
T8 |
1382 |
1345 |
0 |
3 |
T19 |
2070 |
1962 |
0 |
3 |
T24 |
1713 |
1616 |
0 |
3 |
T25 |
921 |
860 |
0 |
3 |
T26 |
2001 |
1868 |
0 |
3 |
T27 |
1141 |
1023 |
0 |
3 |
T28 |
1060 |
975 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73714843 |
11765 |
0 |
0 |
T1 |
86575 |
0 |
0 |
0 |
T5 |
27815 |
0 |
0 |
0 |
T8 |
1382 |
15 |
0 |
0 |
T12 |
0 |
158 |
0 |
0 |
T19 |
2070 |
29 |
0 |
0 |
T20 |
981 |
0 |
0 |
0 |
T21 |
0 |
23 |
0 |
0 |
T23 |
0 |
37 |
0 |
0 |
T24 |
1713 |
0 |
0 |
0 |
T25 |
921 |
3 |
0 |
0 |
T26 |
2001 |
0 |
0 |
0 |
T27 |
1141 |
0 |
0 |
0 |
T28 |
1060 |
0 |
0 |
0 |
T34 |
0 |
9 |
0 |
0 |
T73 |
0 |
23 |
0 |
0 |
T75 |
0 |
2 |
0 |
0 |
T122 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774 |
774 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
220511385 |
218510520 |
0 |
0 |
T1 |
139637 |
139568 |
0 |
0 |
T6 |
13660 |
13519 |
0 |
0 |
T7 |
1280 |
1240 |
0 |
0 |
T8 |
5760 |
5649 |
0 |
0 |
T19 |
4142 |
4073 |
0 |
0 |
T24 |
1784 |
1744 |
0 |
0 |
T25 |
4004 |
3863 |
0 |
0 |
T26 |
2152 |
2055 |
0 |
0 |
T27 |
2376 |
2265 |
0 |
0 |
T28 |
1951 |
1925 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
220511385 |
218510520 |
0 |
0 |
T1 |
139637 |
139568 |
0 |
0 |
T6 |
13660 |
13519 |
0 |
0 |
T7 |
1280 |
1240 |
0 |
0 |
T8 |
5760 |
5649 |
0 |
0 |
T19 |
4142 |
4073 |
0 |
0 |
T24 |
1784 |
1744 |
0 |
0 |
T25 |
4004 |
3863 |
0 |
0 |
T26 |
2152 |
2055 |
0 |
0 |
T27 |
2376 |
2265 |
0 |
0 |
T28 |
1951 |
1925 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774 |
774 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206048960 |
204130437 |
0 |
0 |
T1 |
134046 |
133980 |
0 |
0 |
T6 |
13113 |
12978 |
0 |
0 |
T7 |
1228 |
1190 |
0 |
0 |
T8 |
5530 |
5423 |
0 |
0 |
T19 |
3977 |
3910 |
0 |
0 |
T24 |
1713 |
1674 |
0 |
0 |
T25 |
3844 |
3709 |
0 |
0 |
T26 |
2067 |
1973 |
0 |
0 |
T27 |
2281 |
2174 |
0 |
0 |
T28 |
1919 |
1894 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206048960 |
204130437 |
0 |
0 |
T1 |
134046 |
133980 |
0 |
0 |
T6 |
13113 |
12978 |
0 |
0 |
T7 |
1228 |
1190 |
0 |
0 |
T8 |
5530 |
5423 |
0 |
0 |
T19 |
3977 |
3910 |
0 |
0 |
T24 |
1713 |
1674 |
0 |
0 |
T25 |
3844 |
3709 |
0 |
0 |
T26 |
2067 |
1973 |
0 |
0 |
T27 |
2281 |
2174 |
0 |
0 |
T28 |
1919 |
1894 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774 |
774 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
102223519 |
102223519 |
0 |
0 |
T1 |
66990 |
66990 |
0 |
0 |
T6 |
6489 |
6489 |
0 |
0 |
T7 |
595 |
595 |
0 |
0 |
T8 |
2993 |
2993 |
0 |
0 |
T19 |
2047 |
2047 |
0 |
0 |
T24 |
837 |
837 |
0 |
0 |
T25 |
1860 |
1860 |
0 |
0 |
T26 |
987 |
987 |
0 |
0 |
T27 |
1087 |
1087 |
0 |
0 |
T28 |
947 |
947 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
102223519 |
102223519 |
0 |
0 |
T1 |
66990 |
66990 |
0 |
0 |
T6 |
6489 |
6489 |
0 |
0 |
T7 |
595 |
595 |
0 |
0 |
T8 |
2993 |
2993 |
0 |
0 |
T19 |
2047 |
2047 |
0 |
0 |
T24 |
837 |
837 |
0 |
0 |
T25 |
1860 |
1860 |
0 |
0 |
T26 |
987 |
987 |
0 |
0 |
T27 |
1087 |
1087 |
0 |
0 |
T28 |
947 |
947 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774 |
774 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
51111378 |
51111378 |
0 |
0 |
T1 |
33495 |
33495 |
0 |
0 |
T6 |
3245 |
3245 |
0 |
0 |
T7 |
298 |
298 |
0 |
0 |
T8 |
1496 |
1496 |
0 |
0 |
T19 |
1024 |
1024 |
0 |
0 |
T24 |
419 |
419 |
0 |
0 |
T25 |
930 |
930 |
0 |
0 |
T26 |
493 |
493 |
0 |
0 |
T27 |
544 |
544 |
0 |
0 |
T28 |
474 |
474 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
51111378 |
51111378 |
0 |
0 |
T1 |
33495 |
33495 |
0 |
0 |
T6 |
3245 |
3245 |
0 |
0 |
T7 |
298 |
298 |
0 |
0 |
T8 |
1496 |
1496 |
0 |
0 |
T19 |
1024 |
1024 |
0 |
0 |
T24 |
419 |
419 |
0 |
0 |
T25 |
930 |
930 |
0 |
0 |
T26 |
493 |
493 |
0 |
0 |
T27 |
544 |
544 |
0 |
0 |
T28 |
474 |
474 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774 |
774 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
105848508 |
104889862 |
0 |
0 |
T1 |
67027 |
66994 |
0 |
0 |
T6 |
6556 |
6489 |
0 |
0 |
T7 |
614 |
595 |
0 |
0 |
T8 |
2765 |
2711 |
0 |
0 |
T19 |
1988 |
1956 |
0 |
0 |
T24 |
857 |
838 |
0 |
0 |
T25 |
1922 |
1855 |
0 |
0 |
T26 |
1033 |
986 |
0 |
0 |
T27 |
1141 |
1087 |
0 |
0 |
T28 |
971 |
959 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
105848508 |
104889862 |
0 |
0 |
T1 |
67027 |
66994 |
0 |
0 |
T6 |
6556 |
6489 |
0 |
0 |
T7 |
614 |
595 |
0 |
0 |
T8 |
2765 |
2711 |
0 |
0 |
T19 |
1988 |
1956 |
0 |
0 |
T24 |
857 |
838 |
0 |
0 |
T25 |
1922 |
1855 |
0 |
0 |
T26 |
1033 |
986 |
0 |
0 |
T27 |
1141 |
1087 |
0 |
0 |
T28 |
971 |
959 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774 |
774 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73714843 |
71817051 |
0 |
0 |
T1 |
86575 |
86488 |
0 |
0 |
T6 |
3277 |
3217 |
0 |
0 |
T7 |
1268 |
1129 |
0 |
0 |
T8 |
1382 |
1348 |
0 |
0 |
T19 |
2070 |
1965 |
0 |
0 |
T24 |
1713 |
1619 |
0 |
0 |
T25 |
921 |
863 |
0 |
0 |
T26 |
2001 |
1871 |
0 |
0 |
T27 |
1141 |
1026 |
0 |
0 |
T28 |
1060 |
978 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73714843 |
71810499 |
0 |
2322 |
T1 |
86575 |
86485 |
0 |
3 |
T6 |
3277 |
3214 |
0 |
3 |
T7 |
1268 |
1126 |
0 |
3 |
T8 |
1382 |
1345 |
0 |
3 |
T19 |
2070 |
1962 |
0 |
3 |
T24 |
1713 |
1616 |
0 |
3 |
T25 |
921 |
860 |
0 |
3 |
T26 |
2001 |
1868 |
0 |
3 |
T27 |
1141 |
1023 |
0 |
3 |
T28 |
1060 |
975 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774 |
774 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73714843 |
71817051 |
0 |
0 |
T1 |
86575 |
86488 |
0 |
0 |
T6 |
3277 |
3217 |
0 |
0 |
T7 |
1268 |
1129 |
0 |
0 |
T8 |
1382 |
1348 |
0 |
0 |
T19 |
2070 |
1965 |
0 |
0 |
T24 |
1713 |
1619 |
0 |
0 |
T25 |
921 |
863 |
0 |
0 |
T26 |
2001 |
1871 |
0 |
0 |
T27 |
1141 |
1026 |
0 |
0 |
T28 |
1060 |
978 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73714843 |
71810499 |
0 |
2322 |
T1 |
86575 |
86485 |
0 |
3 |
T6 |
3277 |
3214 |
0 |
3 |
T7 |
1268 |
1126 |
0 |
3 |
T8 |
1382 |
1345 |
0 |
3 |
T19 |
2070 |
1962 |
0 |
3 |
T24 |
1713 |
1616 |
0 |
3 |
T25 |
921 |
860 |
0 |
3 |
T26 |
2001 |
1868 |
0 |
3 |
T27 |
1141 |
1023 |
0 |
3 |
T28 |
1060 |
975 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774 |
774 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73714843 |
71817051 |
0 |
0 |
T1 |
86575 |
86488 |
0 |
0 |
T6 |
3277 |
3217 |
0 |
0 |
T7 |
1268 |
1129 |
0 |
0 |
T8 |
1382 |
1348 |
0 |
0 |
T19 |
2070 |
1965 |
0 |
0 |
T24 |
1713 |
1619 |
0 |
0 |
T25 |
921 |
863 |
0 |
0 |
T26 |
2001 |
1871 |
0 |
0 |
T27 |
1141 |
1026 |
0 |
0 |
T28 |
1060 |
978 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73714843 |
71810499 |
0 |
2322 |
T1 |
86575 |
86485 |
0 |
3 |
T6 |
3277 |
3214 |
0 |
3 |
T7 |
1268 |
1126 |
0 |
3 |
T8 |
1382 |
1345 |
0 |
3 |
T19 |
2070 |
1962 |
0 |
3 |
T24 |
1713 |
1616 |
0 |
3 |
T25 |
921 |
860 |
0 |
3 |
T26 |
2001 |
1868 |
0 |
3 |
T27 |
1141 |
1023 |
0 |
3 |
T28 |
1060 |
975 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774 |
774 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73714843 |
71817051 |
0 |
0 |
T1 |
86575 |
86488 |
0 |
0 |
T6 |
3277 |
3217 |
0 |
0 |
T7 |
1268 |
1129 |
0 |
0 |
T8 |
1382 |
1348 |
0 |
0 |
T19 |
2070 |
1965 |
0 |
0 |
T24 |
1713 |
1619 |
0 |
0 |
T25 |
921 |
863 |
0 |
0 |
T26 |
2001 |
1871 |
0 |
0 |
T27 |
1141 |
1026 |
0 |
0 |
T28 |
1060 |
978 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73714843 |
71810499 |
0 |
2322 |
T1 |
86575 |
86485 |
0 |
3 |
T6 |
3277 |
3214 |
0 |
3 |
T7 |
1268 |
1126 |
0 |
3 |
T8 |
1382 |
1345 |
0 |
3 |
T19 |
2070 |
1962 |
0 |
3 |
T24 |
1713 |
1616 |
0 |
3 |
T25 |
921 |
860 |
0 |
3 |
T26 |
2001 |
1868 |
0 |
3 |
T27 |
1141 |
1023 |
0 |
3 |
T28 |
1060 |
975 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774 |
774 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73714843 |
71817051 |
0 |
0 |
T1 |
86575 |
86488 |
0 |
0 |
T6 |
3277 |
3217 |
0 |
0 |
T7 |
1268 |
1129 |
0 |
0 |
T8 |
1382 |
1348 |
0 |
0 |
T19 |
2070 |
1965 |
0 |
0 |
T24 |
1713 |
1619 |
0 |
0 |
T25 |
921 |
863 |
0 |
0 |
T26 |
2001 |
1871 |
0 |
0 |
T27 |
1141 |
1026 |
0 |
0 |
T28 |
1060 |
978 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73714843 |
71810499 |
0 |
2322 |
T1 |
86575 |
86485 |
0 |
3 |
T6 |
3277 |
3214 |
0 |
3 |
T7 |
1268 |
1126 |
0 |
3 |
T8 |
1382 |
1345 |
0 |
3 |
T19 |
2070 |
1962 |
0 |
3 |
T24 |
1713 |
1616 |
0 |
3 |
T25 |
921 |
860 |
0 |
3 |
T26 |
2001 |
1868 |
0 |
3 |
T27 |
1141 |
1023 |
0 |
3 |
T28 |
1060 |
975 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774 |
774 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73714843 |
71817051 |
0 |
0 |
T1 |
86575 |
86488 |
0 |
0 |
T6 |
3277 |
3217 |
0 |
0 |
T7 |
1268 |
1129 |
0 |
0 |
T8 |
1382 |
1348 |
0 |
0 |
T19 |
2070 |
1965 |
0 |
0 |
T24 |
1713 |
1619 |
0 |
0 |
T25 |
921 |
863 |
0 |
0 |
T26 |
2001 |
1871 |
0 |
0 |
T27 |
1141 |
1026 |
0 |
0 |
T28 |
1060 |
978 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73714843 |
71810499 |
0 |
2322 |
T1 |
86575 |
86485 |
0 |
3 |
T6 |
3277 |
3214 |
0 |
3 |
T7 |
1268 |
1126 |
0 |
3 |
T8 |
1382 |
1345 |
0 |
3 |
T19 |
2070 |
1962 |
0 |
3 |
T24 |
1713 |
1616 |
0 |
3 |
T25 |
921 |
860 |
0 |
3 |
T26 |
2001 |
1868 |
0 |
3 |
T27 |
1141 |
1023 |
0 |
3 |
T28 |
1060 |
975 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774 |
774 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73714843 |
71817051 |
0 |
0 |
T1 |
86575 |
86488 |
0 |
0 |
T6 |
3277 |
3217 |
0 |
0 |
T7 |
1268 |
1129 |
0 |
0 |
T8 |
1382 |
1348 |
0 |
0 |
T19 |
2070 |
1965 |
0 |
0 |
T24 |
1713 |
1619 |
0 |
0 |
T25 |
921 |
863 |
0 |
0 |
T26 |
2001 |
1871 |
0 |
0 |
T27 |
1141 |
1026 |
0 |
0 |
T28 |
1060 |
978 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73714843 |
71817051 |
0 |
0 |
T1 |
86575 |
86488 |
0 |
0 |
T6 |
3277 |
3217 |
0 |
0 |
T7 |
1268 |
1129 |
0 |
0 |
T8 |
1382 |
1348 |
0 |
0 |
T19 |
2070 |
1965 |
0 |
0 |
T24 |
1713 |
1619 |
0 |
0 |
T25 |
921 |
863 |
0 |
0 |
T26 |
2001 |
1871 |
0 |
0 |
T27 |
1141 |
1026 |
0 |
0 |
T28 |
1060 |
978 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774 |
774 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73714843 |
71817051 |
0 |
0 |
T1 |
86575 |
86488 |
0 |
0 |
T6 |
3277 |
3217 |
0 |
0 |
T7 |
1268 |
1129 |
0 |
0 |
T8 |
1382 |
1348 |
0 |
0 |
T19 |
2070 |
1965 |
0 |
0 |
T24 |
1713 |
1619 |
0 |
0 |
T25 |
921 |
863 |
0 |
0 |
T26 |
2001 |
1871 |
0 |
0 |
T27 |
1141 |
1026 |
0 |
0 |
T28 |
1060 |
978 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73714843 |
71817051 |
0 |
0 |
T1 |
86575 |
86488 |
0 |
0 |
T6 |
3277 |
3217 |
0 |
0 |
T7 |
1268 |
1129 |
0 |
0 |
T8 |
1382 |
1348 |
0 |
0 |
T19 |
2070 |
1965 |
0 |
0 |
T24 |
1713 |
1619 |
0 |
0 |
T25 |
921 |
863 |
0 |
0 |
T26 |
2001 |
1871 |
0 |
0 |
T27 |
1141 |
1026 |
0 |
0 |
T28 |
1060 |
978 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774 |
774 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73714843 |
71817051 |
0 |
0 |
T1 |
86575 |
86488 |
0 |
0 |
T6 |
3277 |
3217 |
0 |
0 |
T7 |
1268 |
1129 |
0 |
0 |
T8 |
1382 |
1348 |
0 |
0 |
T19 |
2070 |
1965 |
0 |
0 |
T24 |
1713 |
1619 |
0 |
0 |
T25 |
921 |
863 |
0 |
0 |
T26 |
2001 |
1871 |
0 |
0 |
T27 |
1141 |
1026 |
0 |
0 |
T28 |
1060 |
978 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73714843 |
71817051 |
0 |
0 |
T1 |
86575 |
86488 |
0 |
0 |
T6 |
3277 |
3217 |
0 |
0 |
T7 |
1268 |
1129 |
0 |
0 |
T8 |
1382 |
1348 |
0 |
0 |
T19 |
2070 |
1965 |
0 |
0 |
T24 |
1713 |
1619 |
0 |
0 |
T25 |
921 |
863 |
0 |
0 |
T26 |
2001 |
1871 |
0 |
0 |
T27 |
1141 |
1026 |
0 |
0 |
T28 |
1060 |
978 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774 |
774 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73714843 |
71817051 |
0 |
0 |
T1 |
86575 |
86488 |
0 |
0 |
T6 |
3277 |
3217 |
0 |
0 |
T7 |
1268 |
1129 |
0 |
0 |
T8 |
1382 |
1348 |
0 |
0 |
T19 |
2070 |
1965 |
0 |
0 |
T24 |
1713 |
1619 |
0 |
0 |
T25 |
921 |
863 |
0 |
0 |
T26 |
2001 |
1871 |
0 |
0 |
T27 |
1141 |
1026 |
0 |
0 |
T28 |
1060 |
978 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73714843 |
71817051 |
0 |
0 |
T1 |
86575 |
86488 |
0 |
0 |
T6 |
3277 |
3217 |
0 |
0 |
T7 |
1268 |
1129 |
0 |
0 |
T8 |
1382 |
1348 |
0 |
0 |
T19 |
2070 |
1965 |
0 |
0 |
T24 |
1713 |
1619 |
0 |
0 |
T25 |
921 |
863 |
0 |
0 |
T26 |
2001 |
1871 |
0 |
0 |
T27 |
1141 |
1026 |
0 |
0 |
T28 |
1060 |
978 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774 |
774 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
220511385 |
216467788 |
0 |
0 |
T1 |
139637 |
139496 |
0 |
0 |
T6 |
13660 |
13405 |
0 |
0 |
T7 |
1280 |
1140 |
0 |
0 |
T8 |
5760 |
5620 |
0 |
0 |
T19 |
4142 |
3930 |
0 |
0 |
T24 |
1784 |
1687 |
0 |
0 |
T25 |
4004 |
3749 |
0 |
0 |
T26 |
2152 |
2012 |
0 |
0 |
T27 |
2376 |
2136 |
0 |
0 |
T28 |
1951 |
1782 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
220511385 |
216461439 |
0 |
2322 |
T1 |
139637 |
139493 |
0 |
3 |
T6 |
13660 |
13402 |
0 |
3 |
T7 |
1280 |
1137 |
0 |
3 |
T8 |
5760 |
5617 |
0 |
3 |
T19 |
4142 |
3927 |
0 |
3 |
T24 |
1784 |
1684 |
0 |
3 |
T25 |
4004 |
3746 |
0 |
3 |
T26 |
2152 |
2009 |
0 |
3 |
T27 |
2376 |
2133 |
0 |
3 |
T28 |
1951 |
1779 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
220511385 |
19458 |
0 |
0 |
T1 |
139637 |
1 |
0 |
0 |
T6 |
13660 |
58 |
0 |
0 |
T7 |
1280 |
3 |
0 |
0 |
T8 |
5760 |
5 |
0 |
0 |
T19 |
4142 |
19 |
0 |
0 |
T24 |
1784 |
12 |
0 |
0 |
T25 |
4004 |
1 |
0 |
0 |
T26 |
2152 |
26 |
0 |
0 |
T27 |
2376 |
18 |
0 |
0 |
T28 |
1951 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774 |
774 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
220511385 |
216467788 |
0 |
0 |
T1 |
139637 |
139496 |
0 |
0 |
T6 |
13660 |
13405 |
0 |
0 |
T7 |
1280 |
1140 |
0 |
0 |
T8 |
5760 |
5620 |
0 |
0 |
T19 |
4142 |
3930 |
0 |
0 |
T24 |
1784 |
1687 |
0 |
0 |
T25 |
4004 |
3749 |
0 |
0 |
T26 |
2152 |
2012 |
0 |
0 |
T27 |
2376 |
2136 |
0 |
0 |
T28 |
1951 |
1782 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
220511385 |
216467788 |
0 |
0 |
T1 |
139637 |
139496 |
0 |
0 |
T6 |
13660 |
13405 |
0 |
0 |
T7 |
1280 |
1140 |
0 |
0 |
T8 |
5760 |
5620 |
0 |
0 |
T19 |
4142 |
3930 |
0 |
0 |
T24 |
1784 |
1687 |
0 |
0 |
T25 |
4004 |
3749 |
0 |
0 |
T26 |
2152 |
2012 |
0 |
0 |
T27 |
2376 |
2136 |
0 |
0 |
T28 |
1951 |
1782 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774 |
774 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
220511385 |
216467788 |
0 |
0 |
T1 |
139637 |
139496 |
0 |
0 |
T6 |
13660 |
13405 |
0 |
0 |
T7 |
1280 |
1140 |
0 |
0 |
T8 |
5760 |
5620 |
0 |
0 |
T19 |
4142 |
3930 |
0 |
0 |
T24 |
1784 |
1687 |
0 |
0 |
T25 |
4004 |
3749 |
0 |
0 |
T26 |
2152 |
2012 |
0 |
0 |
T27 |
2376 |
2136 |
0 |
0 |
T28 |
1951 |
1782 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
220511385 |
216461439 |
0 |
2322 |
T1 |
139637 |
139493 |
0 |
3 |
T6 |
13660 |
13402 |
0 |
3 |
T7 |
1280 |
1137 |
0 |
3 |
T8 |
5760 |
5617 |
0 |
3 |
T19 |
4142 |
3927 |
0 |
3 |
T24 |
1784 |
1684 |
0 |
3 |
T25 |
4004 |
3746 |
0 |
3 |
T26 |
2152 |
2009 |
0 |
3 |
T27 |
2376 |
2133 |
0 |
3 |
T28 |
1951 |
1779 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
220511385 |
19271 |
0 |
0 |
T1 |
139637 |
1 |
0 |
0 |
T6 |
13660 |
56 |
0 |
0 |
T7 |
1280 |
3 |
0 |
0 |
T8 |
5760 |
8 |
0 |
0 |
T19 |
4142 |
14 |
0 |
0 |
T24 |
1784 |
9 |
0 |
0 |
T25 |
4004 |
1 |
0 |
0 |
T26 |
2152 |
19 |
0 |
0 |
T27 |
2376 |
14 |
0 |
0 |
T28 |
1951 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774 |
774 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
220511385 |
216467788 |
0 |
0 |
T1 |
139637 |
139496 |
0 |
0 |
T6 |
13660 |
13405 |
0 |
0 |
T7 |
1280 |
1140 |
0 |
0 |
T8 |
5760 |
5620 |
0 |
0 |
T19 |
4142 |
3930 |
0 |
0 |
T24 |
1784 |
1687 |
0 |
0 |
T25 |
4004 |
3749 |
0 |
0 |
T26 |
2152 |
2012 |
0 |
0 |
T27 |
2376 |
2136 |
0 |
0 |
T28 |
1951 |
1782 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
220511385 |
216467788 |
0 |
0 |
T1 |
139637 |
139496 |
0 |
0 |
T6 |
13660 |
13405 |
0 |
0 |
T7 |
1280 |
1140 |
0 |
0 |
T8 |
5760 |
5620 |
0 |
0 |
T19 |
4142 |
3930 |
0 |
0 |
T24 |
1784 |
1687 |
0 |
0 |
T25 |
4004 |
3749 |
0 |
0 |
T26 |
2152 |
2012 |
0 |
0 |
T27 |
2376 |
2136 |
0 |
0 |
T28 |
1951 |
1782 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774 |
774 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
220511385 |
216467788 |
0 |
0 |
T1 |
139637 |
139496 |
0 |
0 |
T6 |
13660 |
13405 |
0 |
0 |
T7 |
1280 |
1140 |
0 |
0 |
T8 |
5760 |
5620 |
0 |
0 |
T19 |
4142 |
3930 |
0 |
0 |
T24 |
1784 |
1687 |
0 |
0 |
T25 |
4004 |
3749 |
0 |
0 |
T26 |
2152 |
2012 |
0 |
0 |
T27 |
2376 |
2136 |
0 |
0 |
T28 |
1951 |
1782 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
220511385 |
216461439 |
0 |
2322 |
T1 |
139637 |
139493 |
0 |
3 |
T6 |
13660 |
13402 |
0 |
3 |
T7 |
1280 |
1137 |
0 |
3 |
T8 |
5760 |
5617 |
0 |
3 |
T19 |
4142 |
3927 |
0 |
3 |
T24 |
1784 |
1684 |
0 |
3 |
T25 |
4004 |
3746 |
0 |
3 |
T26 |
2152 |
2009 |
0 |
3 |
T27 |
2376 |
2133 |
0 |
3 |
T28 |
1951 |
1779 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
220511385 |
19311 |
0 |
0 |
T1 |
139637 |
1 |
0 |
0 |
T6 |
13660 |
60 |
0 |
0 |
T7 |
1280 |
3 |
0 |
0 |
T8 |
5760 |
5 |
0 |
0 |
T19 |
4142 |
18 |
0 |
0 |
T24 |
1784 |
12 |
0 |
0 |
T25 |
4004 |
1 |
0 |
0 |
T26 |
2152 |
27 |
0 |
0 |
T27 |
2376 |
16 |
0 |
0 |
T28 |
1951 |
8 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774 |
774 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
220511385 |
216467788 |
0 |
0 |
T1 |
139637 |
139496 |
0 |
0 |
T6 |
13660 |
13405 |
0 |
0 |
T7 |
1280 |
1140 |
0 |
0 |
T8 |
5760 |
5620 |
0 |
0 |
T19 |
4142 |
3930 |
0 |
0 |
T24 |
1784 |
1687 |
0 |
0 |
T25 |
4004 |
3749 |
0 |
0 |
T26 |
2152 |
2012 |
0 |
0 |
T27 |
2376 |
2136 |
0 |
0 |
T28 |
1951 |
1782 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
220511385 |
216467788 |
0 |
0 |
T1 |
139637 |
139496 |
0 |
0 |
T6 |
13660 |
13405 |
0 |
0 |
T7 |
1280 |
1140 |
0 |
0 |
T8 |
5760 |
5620 |
0 |
0 |
T19 |
4142 |
3930 |
0 |
0 |
T24 |
1784 |
1687 |
0 |
0 |
T25 |
4004 |
3749 |
0 |
0 |
T26 |
2152 |
2012 |
0 |
0 |
T27 |
2376 |
2136 |
0 |
0 |
T28 |
1951 |
1782 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774 |
774 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
220511385 |
216467788 |
0 |
0 |
T1 |
139637 |
139496 |
0 |
0 |
T6 |
13660 |
13405 |
0 |
0 |
T7 |
1280 |
1140 |
0 |
0 |
T8 |
5760 |
5620 |
0 |
0 |
T19 |
4142 |
3930 |
0 |
0 |
T24 |
1784 |
1687 |
0 |
0 |
T25 |
4004 |
3749 |
0 |
0 |
T26 |
2152 |
2012 |
0 |
0 |
T27 |
2376 |
2136 |
0 |
0 |
T28 |
1951 |
1782 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
220511385 |
216461439 |
0 |
2322 |
T1 |
139637 |
139493 |
0 |
3 |
T6 |
13660 |
13402 |
0 |
3 |
T7 |
1280 |
1137 |
0 |
3 |
T8 |
5760 |
5617 |
0 |
3 |
T19 |
4142 |
3927 |
0 |
3 |
T24 |
1784 |
1684 |
0 |
3 |
T25 |
4004 |
3746 |
0 |
3 |
T26 |
2152 |
2009 |
0 |
3 |
T27 |
2376 |
2133 |
0 |
3 |
T28 |
1951 |
1779 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
220511385 |
19423 |
0 |
0 |
T1 |
139637 |
1 |
0 |
0 |
T6 |
13660 |
53 |
0 |
0 |
T7 |
1280 |
3 |
0 |
0 |
T8 |
5760 |
8 |
0 |
0 |
T19 |
4142 |
18 |
0 |
0 |
T24 |
1784 |
11 |
0 |
0 |
T25 |
4004 |
1 |
0 |
0 |
T26 |
2152 |
25 |
0 |
0 |
T27 |
2376 |
9 |
0 |
0 |
T28 |
1951 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774 |
774 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
220511385 |
216467788 |
0 |
0 |
T1 |
139637 |
139496 |
0 |
0 |
T6 |
13660 |
13405 |
0 |
0 |
T7 |
1280 |
1140 |
0 |
0 |
T8 |
5760 |
5620 |
0 |
0 |
T19 |
4142 |
3930 |
0 |
0 |
T24 |
1784 |
1687 |
0 |
0 |
T25 |
4004 |
3749 |
0 |
0 |
T26 |
2152 |
2012 |
0 |
0 |
T27 |
2376 |
2136 |
0 |
0 |
T28 |
1951 |
1782 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
220511385 |
216467788 |
0 |
0 |
T1 |
139637 |
139496 |
0 |
0 |
T6 |
13660 |
13405 |
0 |
0 |
T7 |
1280 |
1140 |
0 |
0 |
T8 |
5760 |
5620 |
0 |
0 |
T19 |
4142 |
3930 |
0 |
0 |
T24 |
1784 |
1687 |
0 |
0 |
T25 |
4004 |
3749 |
0 |
0 |
T26 |
2152 |
2012 |
0 |
0 |
T27 |
2376 |
2136 |
0 |
0 |
T28 |
1951 |
1782 |
0 |
0 |