Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T4,T12,T29

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	73714843	71739189	0	0
AllClkBypReqTrue_A	73714843	75755	0	0
IoClkBypReqFalse_A	73714843	71688394	0	2322
IoClkBypReqTrue_A	73714843	122336	0	0
LcClkBypAckFalse_A	73714843	71744604	0	0
LcClkBypAckTrue_A	73714843	70340	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73714843	71739189	0	0
T1	86575	86487	0	0
T6	3277	3216	0	0
T7	1268	1128	0	0
T8	1382	1293	0	0
T19	2070	1860	0	0
T24	1713	1618	0	0
T25	921	856	0	0
T26	2001	1870	0	0
T27	1141	1025	0	0
T28	1060	977	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73714843	75755	0	0
T1	86575	0	0	0
T5	27815	0	0	0
T8	1382	54	0	0
T12	0	1175	0	0
T19	2070	104	0	0
T20	981	0	0	0
T21	0	136	0	0
T23	0	233	0	0
T24	1713	0	0	0
T25	921	6	0	0
T26	2001	0	0	0
T27	1141	0	0	0
T28	1060	0	0	0
T34	0	6	0	0
T122	0	41	0	0
T123	0	47	0	0
T124	0	192	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73714843	71688394	0	2322
T1	86575	86485	0	3
T6	3277	3214	0	3
T7	1268	1126	0	3
T8	1382	1172	0	3
T19	2070	1853	0	3
T24	1713	1616	0	3
T25	921	860	0	3
T26	2001	1868	0	3
T27	1141	1023	0	3
T28	1060	975	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73714843	122336	0	0
T1	86575	0	0	0
T5	27815	0	0	0
T8	1382	173	0	0
T12	0	2083	0	0
T19	2070	109	0	0
T20	981	0	0	0
T23	0	364	0	0
T24	1713	0	0	0
T25	921	0	0	0
T26	2001	0	0	0
T27	1141	0	0	0
T28	1060	0	0	0
T34	0	152	0	0
T73	0	340	0	0
T122	0	105	0	0
T123	0	73	0	0
T124	0	92	0	0
T125	0	327	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73714843	71744604	0	0
T1	86575	86487	0	0
T6	3277	3216	0	0
T7	1268	1128	0	0
T8	1382	1228	0	0
T19	2070	1930	0	0
T24	1713	1618	0	0
T25	921	862	0	0
T26	2001	1870	0	0
T27	1141	1025	0	0
T28	1060	977	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73714843	70340	0	0
T1	86575	0	0	0
T5	27815	0	0	0
T8	1382	119	0	0
T12	0	1301	0	0
T19	2070	34	0	0
T20	981	0	0	0
T23	0	172	0	0
T24	1713	0	0	0
T25	921	0	0	0
T26	2001	0	0	0
T27	1141	0	0	0
T28	1060	0	0	0
T34	0	135	0	0
T73	0	201	0	0
T122	0	63	0	0
T123	0	58	0	0
T124	0	84	0	0
T125	0	248	0	0