Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	882047268	8640	0	0
TransStop_A	882047268	4521	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	882047268	8640	0	0
T1	558548	0	0	0
T6	54644	36	0	0
T7	5124	0	0	0
T8	23040	0	0	0
T12	0	145	0	0
T19	16572	0	0	0
T24	7140	4	0	0
T25	16016	0	0	0
T26	8612	16	0	0
T27	9504	0	0	0
T28	7808	0	0	0
T29	0	36	0	0
T43	0	4	0	0
T72	0	8	0	0
T126	0	9	0	0
T127	0	4	0	0
T128	0	18	0	0
T129	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	882047268	4521	0	0
T1	558548	0	0	0
T6	54644	26	0	0
T7	5124	0	0	0
T8	23040	0	0	0
T12	0	74	0	0
T19	16572	0	0	0
T24	7140	3	0	0
T25	16016	0	0	0
T26	8612	11	0	0
T27	9504	0	0	0
T28	7808	0	0	0
T29	0	30	0	0
T43	0	4	0	0
T72	0	2	0	0
T126	0	5	0	0
T127	0	4	0	0
T128	0	14	0	0
T129	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	220511817	2118	0	0
TransStop_A	220511817	1086	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220511817	2118	0	0
T1	139637	0	0	0
T6	13661	10	0	0
T7	1281	0	0	0
T8	5760	0	0	0
T12	0	41	0	0
T19	4143	0	0	0
T24	1785	0	0	0
T25	4004	0	0	0
T26	2153	2	0	0
T27	2376	0	0	0
T28	1952	0	0	0
T29	0	10	0	0
T43	0	1	0	0
T72	0	3	0	0
T126	0	3	0	0
T127	0	1	0	0
T128	0	4	0	0
T129	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220511817	1086	0	0
T1	139637	0	0	0
T6	13661	7	0	0
T7	1281	0	0	0
T8	5760	0	0	0
T12	0	21	0	0
T19	4143	0	0	0
T24	1785	0	0	0
T25	4004	0	0	0
T26	2153	2	0	0
T27	2376	0	0	0
T28	1952	0	0	0
T29	0	8	0	0
T43	0	1	0	0
T72	0	1	0	0
T126	0	2	0	0
T127	0	1	0	0
T128	0	3	0	0
T129	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	220511817	2229	0	0
TransStop_A	220511817	1184	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220511817	2229	0	0
T1	139637	0	0	0
T6	13661	10	0	0
T7	1281	0	0	0
T8	5760	0	0	0
T12	0	35	0	0
T19	4143	0	0	0
T24	1785	1	0	0
T25	4004	0	0	0
T26	2153	5	0	0
T27	2376	0	0	0
T28	1952	0	0	0
T29	0	8	0	0
T43	0	1	0	0
T72	0	1	0	0
T126	0	2	0	0
T127	0	1	0	0
T128	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220511817	1184	0	0
T1	139637	0	0	0
T6	13661	7	0	0
T7	1281	0	0	0
T8	5760	0	0	0
T12	0	18	0	0
T19	4143	0	0	0
T24	1785	1	0	0
T25	4004	0	0	0
T26	2153	3	0	0
T27	2376	0	0	0
T28	1952	0	0	0
T29	0	7	0	0
T43	0	1	0	0
T72	0	1	0	0
T126	0	1	0	0
T127	0	1	0	0
T128	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	220511817	2141	0	0
TransStop_A	220511817	1127	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220511817	2141	0	0
T1	139637	0	0	0
T6	13661	7	0	0
T7	1281	0	0	0
T8	5760	0	0	0
T12	0	36	0	0
T19	4143	0	0	0
T24	1785	1	0	0
T25	4004	0	0	0
T26	2153	4	0	0
T27	2376	0	0	0
T28	1952	0	0	0
T29	0	9	0	0
T43	0	1	0	0
T72	0	2	0	0
T126	0	3	0	0
T127	0	1	0	0
T128	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220511817	1127	0	0
T1	139637	0	0	0
T6	13661	5	0	0
T7	1281	0	0	0
T8	5760	0	0	0
T12	0	21	0	0
T19	4143	0	0	0
T24	1785	1	0	0
T25	4004	0	0	0
T26	2153	3	0	0
T27	2376	0	0	0
T28	1952	0	0	0
T29	0	8	0	0
T43	0	1	0	0
T126	0	1	0	0
T127	0	1	0	0
T128	0	4	0	0
T129	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	220511817	2152	0	0
TransStop_A	220511817	1124	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220511817	2152	0	0
T1	139637	0	0	0
T6	13661	9	0	0
T7	1281	0	0	0
T8	5760	0	0	0
T12	0	33	0	0
T19	4143	0	0	0
T24	1785	2	0	0
T25	4004	0	0	0
T26	2153	5	0	0
T27	2376	0	0	0
T28	1952	0	0	0
T29	0	9	0	0
T43	0	1	0	0
T72	0	2	0	0
T126	0	1	0	0
T127	0	1	0	0
T128	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220511817	1124	0	0
T1	139637	0	0	0
T6	13661	7	0	0
T7	1281	0	0	0
T8	5760	0	0	0
T12	0	14	0	0
T19	4143	0	0	0
T24	1785	1	0	0
T25	4004	0	0	0
T26	2153	3	0	0
T27	2376	0	0	0
T28	1952	0	0	0
T29	0	7	0	0
T43	0	1	0	0
T126	0	1	0	0
T127	0	1	0	0
T128	0	3	0	0
T129	0	1	0	0