Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	73714843	11673351	0	58

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73714843	11673351	0	58
T1	86575	23062	0	1
T2	98232	30381	0	1
T3	6224	2284	0	1
T4	36329	0	0	0
T5	27815	0	0	0
T12	0	60631	0	0
T13	0	4242	0	1
T14	0	172627	0	1
T15	0	924940	0	0
T16	0	69135	0	0
T17	0	25025	0	1
T19	2070	0	0	0
T20	981	0	0	0
T21	1301	0	0	0
T22	1064	0	0	0
T23	2221	0	0	0
T29	0	671	0	0
T79	0	0	0	1
T130	0	0	0	1
T131	0	0	0	1
T132	0	0	0	1