Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	74632872	1933403	0	0
clk_enables_rd_A	74632872	20947	0	0
clk_hints_rd_A	74632872	18422	0	0
extclk_ctrl_rd_A	74632872	24776	0	0
extclk_ctrl_regwen_rd_A	74632872	18035	0	0
jitter_enable_rd_A	74632872	27125	0	0
jitter_regwen_rd_A	74632872	19810	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74632872	1933403	0	0
T12	185322	65479	0	0
T15	0	127665	0	0
T16	0	143248	0	0
T18	0	143872	0	0
T29	40987	0	0	0
T35	186263	0	0	0
T36	9492	0	0	0
T38	195855	0	0	0
T43	1610	0	0	0
T66	0	139446	0	0
T67	0	64261	0	0
T68	0	113770	0	0
T69	0	55852	0	0
T70	0	54756	0	0
T71	0	94715	0	0
T72	1027	0	0	0
T73	2816	0	0	0
T74	989	0	0	0
T75	928	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74632872	20947	0	0
T13	13240	0	0	0
T39	11634	0	0	0
T42	0	11	0	0
T66	0	5428	0	0
T68	0	4489	0	0
T127	2449	1	0	0
T128	1497	0	0	0
T152	0	5	0	0
T153	0	1	0	0
T154	0	2	0	0
T155	0	4	0	0
T156	0	2	0	0
T157	0	1	0	0
T158	1736	0	0	0
T159	1034	0	0	0
T160	878	0	0	0
T161	1688	0	0	0
T162	1121	0	0	0
T163	1408	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74632872	18422	0	0
T13	13240	0	0	0
T39	11634	0	0	0
T42	0	4	0	0
T66	0	4801	0	0
T127	2449	3	0	0
T128	1497	0	0	0
T152	0	7	0	0
T153	0	2	0	0
T154	0	1	0	0
T155	0	6	0	0
T156	0	6	0	0
T157	0	8	0	0
T158	1736	0	0	0
T159	1034	0	0	0
T160	878	0	0	0
T161	1688	0	0	0
T162	1121	0	0	0
T163	1408	0	0	0
T164	0	5	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74632872	24776	0	0
T2	98232	0	0	0
T3	6224	0	0	0
T4	36329	0	0	0
T21	1301	24	0	0
T22	1064	0	0	0
T23	2221	0	0	0
T32	236643	0	0	0
T33	1128	0	0	0
T34	1291	0	0	0
T37	1416	0	0	0
T39	0	43	0	0
T73	0	55	0	0
T76	0	44	0	0
T77	0	21	0	0
T125	0	39	0	0
T161	0	32	0	0
T165	0	51	0	0
T166	0	8	0	0
T167	0	14	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74632872	18035	0	0
T13	13240	0	0	0
T14	128433	0	0	0
T39	11634	20	0	0
T66	0	4487	0	0
T68	0	4025	0	0
T70	0	947	0	0
T77	7701	8	0	0
T91	0	42	0	0
T121	0	11	0	0
T129	1902	0	0	0
T152	2413	0	0	0
T162	1121	0	0	0
T163	1408	0	0	0
T168	0	65	0	0
T169	0	40	0	0
T170	0	31	0	0
T171	2305	0	0	0
T172	1543	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74632872	27125	0	0
T13	13240	0	0	0
T39	11634	0	0	0
T42	0	261	0	0
T66	0	6145	0	0
T127	2449	112	0	0
T128	1497	0	0	0
T152	0	112	0	0
T153	0	110	0	0
T154	0	119	0	0
T155	0	109	0	0
T156	0	114	0	0
T157	0	116	0	0
T158	1736	0	0	0
T159	1034	0	0	0
T160	878	0	0	0
T161	1688	0	0	0
T162	1121	0	0	0
T163	1408	0	0	0
T164	0	114	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74632872	19810	0	0
T58	0	14	0	0
T66	464998	5626	0	0
T68	0	4340	0	0
T70	0	1055	0	0
T80	0	6	0	0
T110	0	7	0	0
T151	0	15	0	0
T173	0	1104	0	0
T174	0	5409	0	0
T175	0	15	0	0
T176	3338	0	0	0
T177	1789	0	0	0
T178	59513	0	0	0
T179	226801	0	0	0
T180	1650	0	0	0
T181	1792	0	0	0
T182	197146	0	0	0
T183	2224	0	0	0
T184	1813	0	0	0