Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T8,T19,T21
1	1	Covered	T8,T25,T19

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	206049359	2692	0	0
g_div2.Div2Whole_A	206049359	3186	0	0
g_div4.Div4Stepped_A	102223923	2622	0	0
g_div4.Div4Whole_A	102223923	3023	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206049359	2692	0	0
T1	134047	0	0	0
T5	78011	0	0	0
T8	5530	4	0	0
T12	0	40	0	0
T19	3977	5	0	0
T20	1623	0	0	0
T21	0	5	0	0
T23	0	7	0	0
T24	1714	0	0	0
T25	3844	0	0	0
T26	2067	0	0	0
T27	2282	0	0	0
T28	1920	0	0	0
T34	0	6	0	0
T73	0	6	0	0
T122	0	2	0	0
T123	0	2	0	0
T124	0	9	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206049359	3186	0	0
T1	134047	0	0	0
T5	78011	0	0	0
T8	5530	4	0	0
T12	0	40	0	0
T19	3977	6	0	0
T20	1623	0	0	0
T21	0	5	0	0
T23	0	11	0	0
T24	1714	0	0	0
T25	3844	1	0	0
T26	2067	0	0	0
T27	2282	0	0	0
T28	1920	0	0	0
T34	0	6	0	0
T73	0	7	0	0
T122	0	2	0	0
T123	0	2	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102223923	2622	0	0
T1	66991	0	0	0
T5	38959	0	0	0
T8	2993	4	0	0
T12	0	40	0	0
T19	2048	4	0	0
T20	792	0	0	0
T21	0	5	0	0
T23	0	7	0	0
T24	838	0	0	0
T25	1860	0	0	0
T26	987	0	0	0
T27	1088	0	0	0
T28	948	0	0	0
T34	0	6	0	0
T73	0	5	0	0
T122	0	2	0	0
T123	0	2	0	0
T124	0	9	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102223923	3023	0	0
T1	66991	0	0	0
T5	38959	0	0	0
T8	2993	4	0	0
T12	0	40	0	0
T19	2048	6	0	0
T20	792	0	0	0
T21	0	5	0	0
T23	0	10	0	0
T24	838	0	0	0
T25	1860	1	0	0
T26	987	0	0	0
T27	1088	0	0	0
T28	948	0	0	0
T34	0	6	0	0
T73	0	7	0	0
T122	0	2	0	0
T123	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T8,T19,T21
1	1	Covered	T8,T25,T19

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	206049359	2692	0	0
g_div2.Div2Whole_A	206049359	3186	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206049359	2692	0	0
T1	134047	0	0	0
T5	78011	0	0	0
T8	5530	4	0	0
T12	0	40	0	0
T19	3977	5	0	0
T20	1623	0	0	0
T21	0	5	0	0
T23	0	7	0	0
T24	1714	0	0	0
T25	3844	0	0	0
T26	2067	0	0	0
T27	2282	0	0	0
T28	1920	0	0	0
T34	0	6	0	0
T73	0	6	0	0
T122	0	2	0	0
T123	0	2	0	0
T124	0	9	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206049359	3186	0	0
T1	134047	0	0	0
T5	78011	0	0	0
T8	5530	4	0	0
T12	0	40	0	0
T19	3977	6	0	0
T20	1623	0	0	0
T21	0	5	0	0
T23	0	11	0	0
T24	1714	0	0	0
T25	3844	1	0	0
T26	2067	0	0	0
T27	2282	0	0	0
T28	1920	0	0	0
T34	0	6	0	0
T73	0	7	0	0
T122	0	2	0	0
T123	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T8,T19,T21
1	1	Covered	T8,T25,T19

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	102223923	2622	0	0
g_div4.Div4Whole_A	102223923	3023	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102223923	2622	0	0
T1	66991	0	0	0
T5	38959	0	0	0
T8	2993	4	0	0
T12	0	40	0	0
T19	2048	4	0	0
T20	792	0	0	0
T21	0	5	0	0
T23	0	7	0	0
T24	838	0	0	0
T25	1860	0	0	0
T26	987	0	0	0
T27	1088	0	0	0
T28	948	0	0	0
T34	0	6	0	0
T73	0	5	0	0
T122	0	2	0	0
T123	0	2	0	0
T124	0	9	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102223923	3023	0	0
T1	66991	0	0	0
T5	38959	0	0	0
T8	2993	4	0	0
T12	0	40	0	0
T19	2048	6	0	0
T20	792	0	0	0
T21	0	5	0	0
T23	0	10	0	0
T24	838	0	0	0
T25	1860	1	0	0
T26	987	0	0	0
T27	1088	0	0	0
T28	948	0	0	0
T34	0	6	0	0
T73	0	7	0	0
T122	0	2	0	0
T123	0	2	0	0