Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	221144529	422	0	0
StatusRise_A	221144529	422	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221144529	422	0	0
T1	259725	0	0	0
T2	294696	0	0	0
T3	18672	0	0	0
T4	108987	0	0	0
T5	83445	0	0	0
T19	6210	0	0	0
T20	2943	8	0	0
T21	3903	0	0	0
T22	3192	7	0	0
T28	3180	6	0	0
T37	0	2	0	0
T159	0	1	0	0
T160	0	7	0	0
T163	0	7	0	0
T185	0	11	0	0
T186	0	14	0	0
T187	0	11	0	0
T188	0	8	0	0
T189	0	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221144529	422	0	0
T1	259725	0	0	0
T2	294696	0	0	0
T3	18672	0	0	0
T4	108987	0	0	0
T5	83445	0	0	0
T19	6210	0	0	0
T20	2943	8	0	0
T21	3903	0	0	0
T22	3192	7	0	0
T28	3180	6	0	0
T37	0	2	0	0
T159	0	1	0	0
T160	0	7	0	0
T163	0	7	0	0
T185	0	11	0	0
T186	0	14	0	0
T187	0	11	0	0
T188	0	8	0	0
T189	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	73714843	130	0	0
StatusRise_A	73714843	130	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73714843	130	0	0
T1	86575	0	0	0
T2	98232	0	0	0
T3	6224	0	0	0
T4	36329	0	0	0
T5	27815	0	0	0
T19	2070	0	0	0
T20	981	1	0	0
T21	1301	0	0	0
T22	1064	2	0	0
T28	1060	2	0	0
T160	0	2	0	0
T163	0	2	0	0
T185	0	4	0	0
T186	0	4	0	0
T187	0	4	0	0
T188	0	5	0	0
T189	0	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73714843	130	0	0
T1	86575	0	0	0
T2	98232	0	0	0
T3	6224	0	0	0
T4	36329	0	0	0
T5	27815	0	0	0
T19	2070	0	0	0
T20	981	1	0	0
T21	1301	0	0	0
T22	1064	2	0	0
T28	1060	2	0	0
T160	0	2	0	0
T163	0	2	0	0
T185	0	4	0	0
T186	0	4	0	0
T187	0	4	0	0
T188	0	5	0	0
T189	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	73714843	138	0	0
StatusRise_A	73714843	138	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73714843	138	0	0
T1	86575	0	0	0
T2	98232	0	0	0
T3	6224	0	0	0
T4	36329	0	0	0
T5	27815	0	0	0
T19	2070	0	0	0
T20	981	3	0	0
T21	1301	0	0	0
T22	1064	3	0	0
T28	1060	2	0	0
T37	0	1	0	0
T160	0	3	0	0
T163	0	2	0	0
T185	0	4	0	0
T186	0	5	0	0
T187	0	4	0	0
T188	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73714843	138	0	0
T1	86575	0	0	0
T2	98232	0	0	0
T3	6224	0	0	0
T4	36329	0	0	0
T5	27815	0	0	0
T19	2070	0	0	0
T20	981	3	0	0
T21	1301	0	0	0
T22	1064	3	0	0
T28	1060	2	0	0
T37	0	1	0	0
T160	0	3	0	0
T163	0	2	0	0
T185	0	4	0	0
T186	0	5	0	0
T187	0	4	0	0
T188	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	73714843	154	0	0
StatusRise_A	73714843	154	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73714843	154	0	0
T1	86575	0	0	0
T2	98232	0	0	0
T3	6224	0	0	0
T4	36329	0	0	0
T5	27815	0	0	0
T19	2070	0	0	0
T20	981	4	0	0
T21	1301	0	0	0
T22	1064	2	0	0
T28	1060	2	0	0
T37	0	1	0	0
T159	0	1	0	0
T160	0	2	0	0
T163	0	3	0	0
T185	0	3	0	0
T186	0	5	0	0
T187	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73714843	154	0	0
T1	86575	0	0	0
T2	98232	0	0	0
T3	6224	0	0	0
T4	36329	0	0	0
T5	27815	0	0	0
T19	2070	0	0	0
T20	981	4	0	0
T21	1301	0	0	0
T22	1064	2	0	0
T28	1060	2	0	0
T37	0	1	0	0
T159	0	1	0	0
T160	0	2	0	0
T163	0	3	0	0
T185	0	3	0	0
T186	0	5	0	0
T187	0	3	0	0