Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T20,T4
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	30182	0	0
CgEnOn_A	2147483647	21756	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	30182	0	0
T1	1507928	3	0	0
T2	930021	0	0	0
T3	262459	0	0	0
T4	634542	0	0	0
T5	451340	0	0	0
T6	84043	13	0	0
T7	7855	3	0	0
T8	35824	3	0	0
T12	0	41	0	0
T19	44972	3	0	0
T20	7791	16	0	0
T21	47233	0	0	0
T22	22060	17	0	0
T24	10962	3	0	0
T25	24572	3	0	0
T26	13188	5	0	0
T27	14557	40	0	0
T28	21276	21	0	0
T37	0	5	0	0
T72	0	3	0	0
T160	0	15	0	0
T163	0	10	0	0
T185	0	20	0	0
T186	0	25	0	0
T187	0	20	0	0
T188	0	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21756	0	0
T1	1507928	0	0	0
T2	1362938	0	0	0
T3	262459	0	0	0
T4	920808	0	0	0
T5	641194	0	0	0
T6	54640	20	0	0
T7	5120	0	0	0
T8	23040	0	0	0
T12	0	174	0	0
T19	44972	0	0	0
T20	11424	26	0	0
T21	69326	0	0	0
T22	32324	28	0	0
T24	7136	1	0	0
T25	16016	0	0	0
T26	8608	7	0	0
T27	14557	37	0	0
T28	21276	20	0	0
T29	0	37	0	0
T37	0	8	0	0
T43	0	5	0	0
T72	0	4	0	0
T74	0	6	0	0
T126	0	3	0	0
T160	0	15	0	0
T163	0	10	0	0
T185	0	20	0	0
T186	0	25	0	0
T187	0	20	0	0
T188	0	15	0	0
T190	0	13	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T20,T4
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	102223519	141	0	0
CgEnOn_A	102223519	141	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102223519	141	0	0
T1	66990	0	0	0
T2	96163	0	0	0
T3	27131	0	0	0
T4	45527	0	0	0
T5	38958	0	0	0
T19	2047	0	0	0
T20	792	3	0	0
T21	5121	0	0	0
T22	2297	3	0	0
T28	947	2	0	0
T37	0	1	0	0
T160	0	3	0	0
T163	0	2	0	0
T185	0	4	0	0
T186	0	5	0	0
T187	0	4	0	0
T188	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102223519	141	0	0
T1	66990	0	0	0
T2	96163	0	0	0
T3	27131	0	0	0
T4	45527	0	0	0
T5	38958	0	0	0
T19	2047	0	0	0
T20	792	3	0	0
T21	5121	0	0	0
T22	2297	3	0	0
T28	947	2	0	0
T37	0	1	0	0
T160	0	3	0	0
T163	0	2	0	0
T185	0	4	0	0
T186	0	5	0	0
T187	0	4	0	0
T188	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T20,T4
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	51111378	141	0	0
CgEnOn_A	51111378	141	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51111378	141	0	0
T1	33495	0	0	0
T2	48081	0	0	0
T3	13566	0	0	0
T4	22763	0	0	0
T5	19479	0	0	0
T19	1024	0	0	0
T20	396	3	0	0
T21	2561	0	0	0
T22	1149	3	0	0
T28	474	2	0	0
T37	0	1	0	0
T160	0	3	0	0
T163	0	2	0	0
T185	0	4	0	0
T186	0	5	0	0
T187	0	4	0	0
T188	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51111378	141	0	0
T1	33495	0	0	0
T2	48081	0	0	0
T3	13566	0	0	0
T4	22763	0	0	0
T5	19479	0	0	0
T19	1024	0	0	0
T20	396	3	0	0
T21	2561	0	0	0
T22	1149	3	0	0
T28	474	2	0	0
T37	0	1	0	0
T160	0	3	0	0
T163	0	2	0	0
T185	0	4	0	0
T186	0	5	0	0
T187	0	4	0	0
T188	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T20,T4
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	51111378	141	0	0
CgEnOn_A	51111378	141	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51111378	141	0	0
T1	33495	0	0	0
T2	48081	0	0	0
T3	13566	0	0	0
T4	22763	0	0	0
T5	19479	0	0	0
T19	1024	0	0	0
T20	396	3	0	0
T21	2561	0	0	0
T22	1149	3	0	0
T28	474	2	0	0
T37	0	1	0	0
T160	0	3	0	0
T163	0	2	0	0
T185	0	4	0	0
T186	0	5	0	0
T187	0	4	0	0
T188	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51111378	141	0	0
T1	33495	0	0	0
T2	48081	0	0	0
T3	13566	0	0	0
T4	22763	0	0	0
T5	19479	0	0	0
T19	1024	0	0	0
T20	396	3	0	0
T21	2561	0	0	0
T22	1149	3	0	0
T28	474	2	0	0
T37	0	1	0	0
T160	0	3	0	0
T163	0	2	0	0
T185	0	4	0	0
T186	0	5	0	0
T187	0	4	0	0
T188	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T20,T4
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	51111378	141	0	0
CgEnOn_A	51111378	141	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51111378	141	0	0
T1	33495	0	0	0
T2	48081	0	0	0
T3	13566	0	0	0
T4	22763	0	0	0
T5	19479	0	0	0
T19	1024	0	0	0
T20	396	3	0	0
T21	2561	0	0	0
T22	1149	3	0	0
T28	474	2	0	0
T37	0	1	0	0
T160	0	3	0	0
T163	0	2	0	0
T185	0	4	0	0
T186	0	5	0	0
T187	0	4	0	0
T188	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51111378	141	0	0
T1	33495	0	0	0
T2	48081	0	0	0
T3	13566	0	0	0
T4	22763	0	0	0
T5	19479	0	0	0
T19	1024	0	0	0
T20	396	3	0	0
T21	2561	0	0	0
T22	1149	3	0	0
T28	474	2	0	0
T37	0	1	0	0
T160	0	3	0	0
T163	0	2	0	0
T185	0	4	0	0
T186	0	5	0	0
T187	0	4	0	0
T188	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T20,T4
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	206048960	141	0	0
CgEnOn_A	206048960	138	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206048960	141	0	0
T1	134046	0	0	0
T2	192446	0	0	0
T3	54314	0	0	0
T4	145315	0	0	0
T5	78010	0	0	0
T19	3977	0	0	0
T20	1622	3	0	0
T21	9607	0	0	0
T22	4619	3	0	0
T28	1919	2	0	0
T37	0	1	0	0
T160	0	3	0	0
T163	0	2	0	0
T185	0	4	0	0
T186	0	5	0	0
T187	0	4	0	0
T188	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206048960	138	0	0
T1	134046	0	0	0
T2	192446	0	0	0
T3	54314	0	0	0
T4	145315	0	0	0
T5	78010	0	0	0
T19	3977	0	0	0
T20	1622	3	0	0
T21	9607	0	0	0
T22	4619	3	0	0
T28	1919	2	0	0
T37	0	1	0	0
T160	0	3	0	0
T163	0	2	0	0
T185	0	4	0	0
T186	0	5	0	0
T187	0	4	0	0
T188	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T20,T4
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	220511385	130	0	0
CgEnOn_A	220511385	130	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220511385	130	0	0
T1	139637	0	0	0
T2	200471	0	0	0
T3	56579	0	0	0
T4	151375	0	0	0
T5	111264	0	0	0
T19	4142	0	0	0
T20	1683	1	0	0
T21	10009	0	0	0
T22	4749	2	0	0
T28	1951	2	0	0
T160	0	2	0	0
T163	0	2	0	0
T185	0	4	0	0
T186	0	4	0	0
T187	0	4	0	0
T188	0	5	0	0
T189	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220511385	130	0	0
T1	139637	0	0	0
T2	200471	0	0	0
T3	56579	0	0	0
T4	151375	0	0	0
T5	111264	0	0	0
T19	4142	0	0	0
T20	1683	1	0	0
T21	10009	0	0	0
T22	4749	2	0	0
T28	1951	2	0	0
T160	0	2	0	0
T163	0	2	0	0
T185	0	4	0	0
T186	0	4	0	0
T187	0	4	0	0
T188	0	5	0	0
T189	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T20,T4
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	220511385	130	0	0
CgEnOn_A	220511385	130	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220511385	130	0	0
T1	139637	0	0	0
T2	200471	0	0	0
T3	56579	0	0	0
T4	151375	0	0	0
T5	111264	0	0	0
T19	4142	0	0	0
T20	1683	1	0	0
T21	10009	0	0	0
T22	4749	2	0	0
T28	1951	2	0	0
T160	0	2	0	0
T163	0	2	0	0
T185	0	4	0	0
T186	0	4	0	0
T187	0	4	0	0
T188	0	5	0	0
T189	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220511385	130	0	0
T1	139637	0	0	0
T2	200471	0	0	0
T3	56579	0	0	0
T4	151375	0	0	0
T5	111264	0	0	0
T19	4142	0	0	0
T20	1683	1	0	0
T21	10009	0	0	0
T22	4749	2	0	0
T28	1951	2	0	0
T160	0	2	0	0
T163	0	2	0	0
T185	0	4	0	0
T186	0	4	0	0
T187	0	4	0	0
T188	0	5	0	0
T189	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T20,T4
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	105848508	155	0	0
CgEnOn_A	105848508	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105848508	155	0	0
T1	67027	0	0	0
T2	96227	0	0	0
T3	27158	0	0	0
T4	72661	0	0	0
T5	53407	0	0	0
T19	1988	0	0	0
T20	823	4	0	0
T21	4804	0	0	0
T22	2199	2	0	0
T28	971	2	0	0
T37	0	1	0	0
T159	0	1	0	0
T160	0	2	0	0
T163	0	3	0	0
T185	0	3	0	0
T186	0	5	0	0
T187	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105848508	154	0	0
T1	67027	0	0	0
T2	96227	0	0	0
T3	27158	0	0	0
T4	72661	0	0	0
T5	53407	0	0	0
T19	1988	0	0	0
T20	823	4	0	0
T21	4804	0	0	0
T22	2199	2	0	0
T28	971	2	0	0
T37	0	1	0	0
T159	0	1	0	0
T160	0	2	0	0
T163	0	3	0	0
T185	0	3	0	0
T186	0	5	0	0
T187	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T20,T22
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	51111378	4978	0	0
CgEnOn_A	51111378	2874	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51111378	4978	0	0
T1	33495	1	0	0
T6	3245	1	0	0
T7	298	1	0	0
T8	1496	1	0	0
T19	1024	1	0	0
T24	419	1	0	0
T25	930	1	0	0
T26	493	1	0	0
T27	544	14	0	0
T28	474	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51111378	2874	0	0
T1	33495	0	0	0
T2	48081	0	0	0
T4	22763	0	0	0
T5	19479	0	0	0
T12	0	32	0	0
T19	1024	0	0	0
T20	396	3	0	0
T21	2561	0	0	0
T22	1149	3	0	0
T27	544	13	0	0
T28	474	2	0	0
T29	0	6	0	0
T37	0	1	0	0
T43	0	1	0	0
T74	0	2	0	0
T190	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T20,T22
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	102223519	4980	0	0
CgEnOn_A	102223519	2876	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102223519	4980	0	0
T1	66990	1	0	0
T6	6489	1	0	0
T7	595	1	0	0
T8	2993	1	0	0
T19	2047	1	0	0
T24	837	1	0	0
T25	1860	1	0	0
T26	987	1	0	0
T27	1087	15	0	0
T28	947	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102223519	2876	0	0
T1	66990	0	0	0
T2	96163	0	0	0
T4	45527	0	0	0
T5	38958	0	0	0
T12	0	34	0	0
T19	2047	0	0	0
T20	792	3	0	0
T21	5121	0	0	0
T22	2297	3	0	0
T27	1087	14	0	0
T28	947	2	0	0
T29	0	7	0	0
T37	0	1	0	0
T43	0	1	0	0
T74	0	2	0	0
T190	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T20,T22
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	206048960	4970	0	0
CgEnOn_A	206048960	2863	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206048960	4970	0	0
T1	134046	1	0	0
T6	13113	1	0	0
T7	1228	1	0	0
T8	5530	1	0	0
T19	3977	1	0	0
T24	1713	1	0	0
T25	3844	1	0	0
T26	2067	1	0	0
T27	2281	11	0	0
T28	1919	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206048960	2863	0	0
T1	134046	0	0	0
T2	192446	0	0	0
T4	145315	0	0	0
T5	78010	0	0	0
T12	0	32	0	0
T19	3977	0	0	0
T20	1622	3	0	0
T21	9607	0	0	0
T22	4619	3	0	0
T27	2281	10	0	0
T28	1919	2	0	0
T29	0	6	0	0
T37	0	1	0	0
T43	0	1	0	0
T74	0	2	0	0
T190	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T20,T22
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	105848508	4974	0	0
CgEnOn_A	105848508	2867	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105848508	4974	0	0
T1	67027	1	0	0
T6	6556	1	0	0
T7	614	1	0	0
T8	2765	1	0	0
T19	1988	1	0	0
T24	857	1	0	0
T25	1922	1	0	0
T26	1033	1	0	0
T27	1141	14	0	0
T28	971	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105848508	2867	0	0
T1	67027	0	0	0
T2	96227	0	0	0
T4	72661	0	0	0
T5	53407	0	0	0
T12	0	32	0	0
T19	1988	0	0	0
T20	823	4	0	0
T21	4804	0	0	0
T22	2199	2	0	0
T27	1141	13	0	0
T28	971	2	0	0
T29	0	5	0	0
T37	0	1	0	0
T43	0	1	0	0
T74	0	2	0	0
T190	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T20,T4
1	0	Covered	T6,T26,T12
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	220511385	2248	0	0
CgEnOn_A	220511385	2248	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220511385	2248	0	0
T1	139637	0	0	0
T6	13660	10	0	0
T7	1280	0	0	0
T8	5760	0	0	0
T12	0	41	0	0
T19	4142	0	0	0
T20	0	1	0	0
T22	0	2	0	0
T24	1784	0	0	0
T25	4004	0	0	0
T26	2152	2	0	0
T27	2376	0	0	0
T28	1951	2	0	0
T29	0	10	0	0
T43	0	1	0	0
T72	0	3	0	0
T126	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220511385	2248	0	0
T1	139637	0	0	0
T6	13660	10	0	0
T7	1280	0	0	0
T8	5760	0	0	0
T12	0	41	0	0
T19	4142	0	0	0
T20	0	1	0	0
T22	0	2	0	0
T24	1784	0	0	0
T25	4004	0	0	0
T26	2152	2	0	0
T27	2376	0	0	0
T28	1951	2	0	0
T29	0	10	0	0
T43	0	1	0	0
T72	0	3	0	0
T126	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T20,T4
1	0	Covered	T6,T24,T26
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	220511385	2359	0	0
CgEnOn_A	220511385	2359	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220511385	2359	0	0
T1	139637	0	0	0
T6	13660	10	0	0
T7	1280	0	0	0
T8	5760	0	0	0
T12	0	35	0	0
T19	4142	0	0	0
T20	0	1	0	0
T22	0	2	0	0
T24	1784	1	0	0
T25	4004	0	0	0
T26	2152	5	0	0
T27	2376	0	0	0
T28	1951	2	0	0
T29	0	8	0	0
T43	0	1	0	0
T72	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220511385	2359	0	0
T1	139637	0	0	0
T6	13660	10	0	0
T7	1280	0	0	0
T8	5760	0	0	0
T12	0	35	0	0
T19	4142	0	0	0
T20	0	1	0	0
T22	0	2	0	0
T24	1784	1	0	0
T25	4004	0	0	0
T26	2152	5	0	0
T27	2376	0	0	0
T28	1951	2	0	0
T29	0	8	0	0
T43	0	1	0	0
T72	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T20,T4
1	0	Covered	T6,T24,T26
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	220511385	2271	0	0
CgEnOn_A	220511385	2271	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220511385	2271	0	0
T1	139637	0	0	0
T6	13660	7	0	0
T7	1280	0	0	0
T8	5760	0	0	0
T12	0	36	0	0
T19	4142	0	0	0
T20	0	1	0	0
T22	0	2	0	0
T24	1784	1	0	0
T25	4004	0	0	0
T26	2152	4	0	0
T27	2376	0	0	0
T28	1951	2	0	0
T29	0	9	0	0
T43	0	1	0	0
T72	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220511385	2271	0	0
T1	139637	0	0	0
T6	13660	7	0	0
T7	1280	0	0	0
T8	5760	0	0	0
T12	0	36	0	0
T19	4142	0	0	0
T20	0	1	0	0
T22	0	2	0	0
T24	1784	1	0	0
T25	4004	0	0	0
T26	2152	4	0	0
T27	2376	0	0	0
T28	1951	2	0	0
T29	0	9	0	0
T43	0	1	0	0
T72	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T20,T4
1	0	Covered	T6,T24,T26
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	220511385	2282	0	0
CgEnOn_A	220511385	2282	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220511385	2282	0	0
T1	139637	0	0	0
T6	13660	9	0	0
T7	1280	0	0	0
T8	5760	0	0	0
T12	0	33	0	0
T19	4142	0	0	0
T20	0	1	0	0
T22	0	2	0	0
T24	1784	2	0	0
T25	4004	0	0	0
T26	2152	5	0	0
T27	2376	0	0	0
T28	1951	2	0	0
T29	0	9	0	0
T43	0	1	0	0
T72	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220511385	2282	0	0
T1	139637	0	0	0
T6	13660	9	0	0
T7	1280	0	0	0
T8	5760	0	0	0
T12	0	33	0	0
T19	4142	0	0	0
T20	0	1	0	0
T22	0	2	0	0
T24	1784	2	0	0
T25	4004	0	0	0
T26	2152	5	0	0
T27	2376	0	0	0
T28	1951	2	0	0
T29	0	9	0	0
T43	0	1	0	0
T72	0	2	0	0