Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

143067402

1

T5

2106

T6

2190

T7

1988

auto[1]

262078

1

T26

684

T27

348

T28

104

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

143050528

1

T5

1978

T6

2190

T7

1988

auto[1]

278952

1

T5

128

T26

552

T27

248

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

142976048

1

T5

1978

T6

2190

T7

1988

auto[1]

353432

1

T5

128

T26

446

T27

168

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

137167760

1

T5

42

T6

2190

T7

1988

auto[1]

6161720

1

T5

2064

T26

3660

T27

2056

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

81905086

1

T5

2106

T6

1948

T7

1988

auto[1]

61424394

1

T6

242

T25

16

T26

678

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

77155728

1

T5

42

T6

1948

T7

1988

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

59752326

1

T6

242

T25

16

T26

192

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

19392

1

T27

4

T29

28

T18

64

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

4526

1

T26

76

T28

16

T22

8

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

4341742

1

T5

1936

T26

2910

T27

1854

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

1596630

1

T26

250

T29

158

T18

298

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

29280

1

T26

52

T27

40

T29

34

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

7844

1

T18

34

T19

26

T3

20

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

30580

1

T26

10

T27

6

T28

68

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

936

1

T26

6

T29

20

T12

16

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

8170

1

T27

80

T3

58

T35

38

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2400

1

T26

114

T12

86

T164

50

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

6804

1

T26

34

T27

66

T29

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

1998

1

T26

8

T18

28

T12

172

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

13502

1

T26

118

T27

96

T29

58

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4190

1

T12

172

T41

250

T68

290

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

45850

1

T26

2

T29

22

T18

20

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

3220

1

T27

40

T22

62

T111

12

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

22752

1

T26

56

T29

102

T18

136

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

6138

1

T27

128

T11

80

T12

92

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

18636

1

T26

4

T29

20

T18

26

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

4252

1

T26

22

T29

2

T18

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

33796

1

T26

100

T18

88

T19

100

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

8416

1

T29

46

T18

56

T22

70

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

71716

1

T26

42

T28

26

T29

34

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

4284

1

T28

2

T29

14

T19

16

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

30866

1

T26

58

T29

156

T19

104

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

8876

1

T28

88

T29

106

T22

72

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

26210

1

T5

128

T26

42

T29

34

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

6490

1

T26

10

T29

12

T18

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

50062

1

T26

110

T29

206

T18

48

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

11868

1

T29

44

T18

86

T19

50