Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total694010
Category 0694010


Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total694010
Severity 0694010


Summary for Assertions
NUMBERPERCENT
Total Number694100.00
Uncovered152.16
Success67997.84
Failure00.00
Incomplete223.17
Without Attempts00.00


Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered660.00
All Matches440.00
First Matches440.00


Detail Report for Assertions

Assertions Uncovered:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.u_io_div2_meas.u_meas.MaxWidth_A 00109955818000
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq 007203217000
tb.dut.u_io_div4_meas.u_meas.MaxWidth_A 0054977509000
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq 007203217000
tb.dut.u_io_meas.u_meas.MaxWidth_A 00221350909000
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq 007203217000
tb.dut.u_main_meas.u_meas.MaxWidth_A 00236483738000
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq 007203217000
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A 0011119020000979
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A 005559468400979
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A 0022391064000979
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A 0023915023000979
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A 0011465787200979
tb.dut.u_usb_meas.u_meas.MaxWidth_A 00113377980000
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq 007203217000

Assertions Success:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.AlertsKnownO_A 00729016417084691600
tb.dut.AllClkBypReqKnownO_A 00729016417084691600
tb.dut.CgEnKnownO_A 00729016417084691600
tb.dut.ClocksKownO_A 00729016417084691600
tb.dut.FpvSecCmClkMainAesCountCheck_A 00729016417700
tb.dut.FpvSecCmClkMainHmacCountCheck_A 00729016418200
tb.dut.FpvSecCmClkMainKmacCountCheck_A 00729016417900
tb.dut.FpvSecCmClkMainOtbnCountCheck_A 00729016418200
tb.dut.FpvSecCmRegWeOnehotCheck_A 00729016419000
tb.dut.IoClkBypReqKnownO_A 00729016417084691600
tb.dut.JitterEnableKnownO_A 00729016417084691600
tb.dut.LcCtrlClkBypAckKnownO_A 00729016417084691600
tb.dut.PwrMgrKnownO_A 00729016417084691600
tb.dut.TlAReadyKnownO_A 00729016417084691600
tb.dut.TlDValidKnownO_A 00729016417084691600
tb.dut.clkmgr_aes_trans_sva_if.TransStart_A 00236484165228900
tb.dut.clkmgr_aes_trans_sva_if.TransStop_A 00236484165117100
tb.dut.clkmgr_aon_cg_aon_peri.CgEn_A 0077477400
tb.dut.clkmgr_aon_cg_aon_powerup.CgEn_A 0077477400
tb.dut.clkmgr_aon_cg_aon_secure.CgEn_A 0077477400
tb.dut.clkmgr_aon_cg_aon_timers.CgEn_A 0077477400
tb.dut.clkmgr_aon_cg_io_div2_powerup.CgEn_A 0077477400
tb.dut.clkmgr_aon_cg_io_div4_powerup.CgEn_A 0077477400
tb.dut.clkmgr_aon_cg_io_powerup.CgEn_A 0077477400
tb.dut.clkmgr_aon_cg_main_powerup.CgEn_A 0077477400
tb.dut.clkmgr_aon_cg_usb_powerup.CgEn_A 0077477400
tb.dut.clkmgr_cg_io_div2_infra.CgEnOff_A 0010995581813400
tb.dut.clkmgr_cg_io_div2_infra.CgEnOn_A 0010995581813400
tb.dut.clkmgr_cg_io_div2_peri.CgEnOff_A 00109955818570300
tb.dut.clkmgr_cg_io_div2_peri.CgEnOn_A 00109955818351600
tb.dut.clkmgr_cg_io_div4_infra.CgEnOff_A 005497750913400
tb.dut.clkmgr_cg_io_div4_infra.CgEnOn_A 005497750913400
tb.dut.clkmgr_cg_io_div4_peri.CgEnOff_A 0054977509568400
tb.dut.clkmgr_cg_io_div4_peri.CgEnOn_A 0054977509349700
tb.dut.clkmgr_cg_io_div4_secure.CgEnOff_A 005497750913400
tb.dut.clkmgr_cg_io_div4_secure.CgEnOn_A 005497750913400
tb.dut.clkmgr_cg_io_div4_timers.CgEnOff_A 005497750913400
tb.dut.clkmgr_cg_io_div4_timers.CgEnOn_A 005497750913400
tb.dut.clkmgr_cg_io_infra.CgEnOff_A 0022135090913400
tb.dut.clkmgr_cg_io_infra.CgEnOn_A 0022135090913200
tb.dut.clkmgr_cg_io_peri.CgEnOff_A 00221350909572000
tb.dut.clkmgr_cg_io_peri.CgEnOn_A 00221350909353100
tb.dut.clkmgr_cg_main_aes.CgEnOff_A 00236483738243900
tb.dut.clkmgr_cg_main_aes.CgEnOn_A 00236483738243800
tb.dut.clkmgr_cg_main_hmac.CgEnOff_A 00236483738247600
tb.dut.clkmgr_cg_main_hmac.CgEnOn_A 00236483738247500
tb.dut.clkmgr_cg_main_infra.CgEnOff_A 0023648373815000
tb.dut.clkmgr_cg_main_infra.CgEnOn_A 0023648373814900
tb.dut.clkmgr_cg_main_kmac.CgEnOff_A 00236483738249000
tb.dut.clkmgr_cg_main_kmac.CgEnOn_A 00236483738248900
tb.dut.clkmgr_cg_main_otbn.CgEnOff_A 00236483738246200
tb.dut.clkmgr_cg_main_otbn.CgEnOn_A 00236483738246100
tb.dut.clkmgr_cg_main_secure.CgEnOff_A 0023648373815000
tb.dut.clkmgr_cg_main_secure.CgEnOn_A 0023648373814900
tb.dut.clkmgr_cg_usb_infra.CgEnOff_A 0011337798015800
tb.dut.clkmgr_cg_usb_infra.CgEnOn_A 0011337798015500
tb.dut.clkmgr_cg_usb_peri.CgEnOff_A 00113377980574400
tb.dut.clkmgr_cg_usb_peri.CgEnOn_A 00113377980355500
tb.dut.clkmgr_csr_assert.TlulOOBAddrErr_A 0073828701192399300
tb.dut.clkmgr_csr_assert.clk_enables_rd_A 00738287012075400
tb.dut.clkmgr_csr_assert.clk_hints_rd_A 00738287011851300
tb.dut.clkmgr_csr_assert.extclk_ctrl_rd_A 00738287012285800
tb.dut.clkmgr_csr_assert.extclk_ctrl_regwen_rd_A 00738287011656900
tb.dut.clkmgr_csr_assert.jitter_enable_rd_A 00738287012786300
tb.dut.clkmgr_csr_assert.jitter_regwen_rd_A 00738287011825200
tb.dut.clkmgr_div2_sva_if.g_div2.Div2Stepped_A 00221351331287900
tb.dut.clkmgr_div2_sva_if.g_div2.Div2Whole_A 00221351331334700
tb.dut.clkmgr_div4_sva_if.g_div4.Div4Stepped_A 00109956206282600
tb.dut.clkmgr_div4_sva_if.g_div4.Div4Whole_A 00109956206319400
tb.dut.clkmgr_extclk_sva_if.AllClkBypReqFall_A 0072901641259100
tb.dut.clkmgr_extclk_sva_if.AllClkBypReqRise_A 0072901641259100
tb.dut.clkmgr_extclk_sva_if.HiSpeedSelFall_A 0072901641152500
tb.dut.clkmgr_extclk_sva_if.HiSpeedSelRise_A 0072901641152500
tb.dut.clkmgr_extclk_sva_if.IoClkBypReqFall_A 0072901641329900
tb.dut.clkmgr_extclk_sva_if.IoClkBypReqRise_A 0072901641329900
tb.dut.clkmgr_hmac_trans_sva_if.TransStart_A 00236484165232600
tb.dut.clkmgr_hmac_trans_sva_if.TransStop_A 00236484165119600
tb.dut.clkmgr_io_div2_peri_sva_if.GateClose_A 00109956206234300
tb.dut.clkmgr_io_div2_peri_sva_if.GateOpen_A 00109956206396800
tb.dut.clkmgr_io_div4_peri_sva_if.GateClose_A 0054977893220800
tb.dut.clkmgr_io_div4_peri_sva_if.GateOpen_A 0054977893383300
tb.dut.clkmgr_io_peri_sva_if.GateClose_A 00221351331233900
tb.dut.clkmgr_io_peri_sva_if.GateOpen_A 00221351331396500
tb.dut.clkmgr_kmac_trans_sva_if.TransStart_A 00236484165234000
tb.dut.clkmgr_kmac_trans_sva_if.TransStop_A 00236484165123600
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if.CtrlEnOn_A 0072901641585000
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if.CtrlEnOn_A 0072901641782200
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if.CtrlEnOn_A 00729016411165000
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if.CtrlEnOn_A 0072901641569800
tb.dut.clkmgr_lost_calib_regwen_sva_if.RegwenOff_A 007290164111170118055
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if.CtrlEnOn_A 0072901641785600
tb.dut.clkmgr_otbn_trans_sva_if.TransStart_A 00236484165231200
tb.dut.clkmgr_otbn_trans_sva_if.TransStop_A 00236484165120900
tb.dut.clkmgr_pwrmgr_io_sva_if.StatusFall_A 007290164113200
tb.dut.clkmgr_pwrmgr_io_sva_if.StatusRise_A 007290164113200
tb.dut.clkmgr_pwrmgr_main_sva_if.StatusFall_A 007290164114900
tb.dut.clkmgr_pwrmgr_main_sva_if.StatusRise_A 007290164114900
tb.dut.clkmgr_pwrmgr_usb_sva_if.StatusFall_A 007290164115500
tb.dut.clkmgr_pwrmgr_usb_sva_if.StatusRise_A 007290164115500
tb.dut.clkmgr_sec_cm_checker_assert.AllClkBypReqFalse_A 00729016417076486200
tb.dut.clkmgr_sec_cm_checker_assert.AllClkBypReqTrue_A 00729016417986500
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqFalse_A 00729016417070931002322
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqTrue_A 007290164113103900
tb.dut.clkmgr_sec_cm_checker_assert.LcClkBypAckFalse_A 00729016417077070400
tb.dut.clkmgr_sec_cm_checker_assert.LcClkBypAckTrue_A 00729016417402300
tb.dut.clkmgr_usb_peri_sva_if.GateClose_A 00113378376237500
tb.dut.clkmgr_usb_peri_sva_if.GateOpen_A 00113378376400100
tb.dut.tlul_assert_device.aKnown_A 0073828701802640300
tb.dut.tlul_assert_device.aKnown_AKnownEnable 00738287017166474000
tb.dut.tlul_assert_device.aReadyKnown_A 00738287017166474000
tb.dut.tlul_assert_device.dKnown_A 0073828701821568300
tb.dut.tlul_assert_device.dKnown_AKnownEnable 00738287017166474000
tb.dut.tlul_assert_device.dReadyKnown_A 00738287017166474000
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[202].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[203].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[204].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[205].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[206].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[207].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[208].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[209].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[20].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[210].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[211].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[212].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[213].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[214].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[215].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[216].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[217].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[218].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[219].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[21].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[220].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[221].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[222].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[223].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[224].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[225].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[226].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[227].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[228].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[229].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[22].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[230].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[231].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[232].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[233].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[234].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[235].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[236].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[237].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[238].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[239].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[23].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[240].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[241].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[242].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[243].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[244].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[245].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[246].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[247].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[248].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[249].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[24].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[250].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[251].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[252].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[253].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[254].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[255].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[25].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[28].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[2].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[31].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[33].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[34].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[35].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[36].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[37].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[38].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[39].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A 0097997900
tb.dut.tlul_assert_device.gen_device.aDataKnown_M 0073829320656584100
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A 0073828701103858300
tb.dut.tlul_assert_device.gen_device.contigMask_M 007382932022646400
tb.dut.tlul_assert_device.gen_device.dDataKnown_A 007382932013177800
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A 0073828701115102800
tb.dut.tlul_assert_device.gen_device.legalAParam_M 0073829320802640300
tb.dut.tlul_assert_device.gen_device.legalDParam_A 0073829320821568300
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M 0073829320802640300
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A 0073829320821568300
tb.dut.tlul_assert_device.gen_device.respOpcode_A 0073829320821568300
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A 0073829320821568300
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A 007382870162062000
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A 007382870147010200
tb.dut.tlul_assert_device.p_dbw.TlDbw_A 0097997900
tb.dut.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A 0077477400
tb.dut.u_calib_rdy_sync.OutputsKnown_A 00729016417084691600
tb.dut.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A 00729016417084016002322
tb.dut.u_clk_io_div2_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A 0077477400
tb.dut.u_clk_io_div2_peri_scanmode_sync.OutputsKnown_A 00729016417084691600
tb.dut.u_clk_io_div2_peri_scanmode_sync.gen_no_flops.OutputDelay_A 00729016417084691600
tb.dut.u_clk_io_div4_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A 0077477400
tb.dut.u_clk_io_div4_peri_scanmode_sync.OutputsKnown_A 00729016417084691600
tb.dut.u_clk_io_div4_peri_scanmode_sync.gen_no_flops.OutputDelay_A 00729016417084691600
tb.dut.u_clk_io_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A 0077477400
tb.dut.u_clk_io_peri_scanmode_sync.OutputsKnown_A 00729016417084691600
tb.dut.u_clk_io_peri_scanmode_sync.gen_no_flops.OutputDelay_A 00729016417084691600
tb.dut.u_clk_main_aes_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A 0077477400
tb.dut.u_clk_main_aes_trans.u_idle_sync.OutputsKnown_A 0023648373823274637700
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A 0023648373823273973202322
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A 002364837382113600
tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender.OutputsKnown_A 0023648373823274637700
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0077477400
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.OutputsKnown_A 0023648373823274637700
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A 0023648373823274637700
tb.dut.u_clk_main_hmac_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A 0077477400
tb.dut.u_clk_main_hmac_trans.u_idle_sync.OutputsKnown_A 0023648373823274637700
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A 0023648373823273973202322
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A 002364837382085400
tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender.OutputsKnown_A 0023648373823274637700
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0077477400
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.OutputsKnown_A 0023648373823274637700
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A 0023648373823274637700
tb.dut.u_clk_main_kmac_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A 0077477400
tb.dut.u_clk_main_kmac_trans.u_idle_sync.OutputsKnown_A 0023648373823274637700
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A 0023648373823273973202322
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A 002364837382089600
tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender.OutputsKnown_A 0023648373823274637700
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0077477400
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.OutputsKnown_A 0023648373823274637700
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A 0023648373823274637700
tb.dut.u_clk_main_otbn_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A 0077477400
tb.dut.u_clk_main_otbn_trans.u_idle_sync.OutputsKnown_A 0023648373823274637700
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A 0023648373823273973202322
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A 002364837382093000
tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender.OutputsKnown_A 0023648373823274637700
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0077477400
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.OutputsKnown_A 0023648373823274637700
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A 0023648373823274637700
tb.dut.u_clk_usb_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A 0077477400
tb.dut.u_clk_usb_peri_scanmode_sync.OutputsKnown_A 00729016417084691600
tb.dut.u_clk_usb_peri_scanmode_sync.gen_no_flops.OutputDelay_A 00729016417084691600
tb.dut.u_clkmgr_byp.u_all_ack_sync.NumCopiesMustBeGreaterZero_A 0077477400
tb.dut.u_clkmgr_byp.u_all_ack_sync.OutputsKnown_A 00729016417084691600
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A 00729016417084016002322
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A 00729016411250800
tb.dut.u_clkmgr_byp.u_all_byp_req.OutputsKnown_A 00729016417084691600
tb.dut.u_clkmgr_byp.u_en_sync.NumCopiesMustBeGreaterZero_A 0077477400
tb.dut.u_clkmgr_byp.u_en_sync.OutputsKnown_A 00729016417084691600
tb.dut.u_clkmgr_byp.u_en_sync.gen_flops.OutputDelay_A 00729016417084016002322
tb.dut.u_clkmgr_byp.u_hi_speed_sel.OutputsKnown_A 00729016417084691600
tb.dut.u_clkmgr_byp.u_io_ack_sync.NumCopiesMustBeGreaterZero_A 0077477400
tb.dut.u_clkmgr_byp.u_io_ack_sync.OutputsKnown_A 00729016417084691600
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A 00729016417084016002322
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A 00729016411101000
tb.dut.u_clkmgr_byp.u_io_byp_req.OutputsKnown_A 00729016417084691600
tb.dut.u_clkmgr_byp.u_lc_byp_req.NumCopiesMustBeGreaterZero_A 0077477400
tb.dut.u_clkmgr_byp.u_lc_byp_req.OutputsKnown_A 00729016417084691600
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_flops.OutputDelay_A 00729016417084016002322
tb.dut.u_io_div2_div_scanmode_sync.NumCopiesMustBeGreaterZero_A 0077477400
tb.dut.u_io_div2_div_scanmode_sync.OutputsKnown_A 00729016417084691600
tb.dut.u_io_div2_div_scanmode_sync.gen_no_flops.OutputDelay_A 00729016417084691600
tb.dut.u_io_div2_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A 0077477400
tb.dut.u_io_div2_meas.u_calib_rdy_sync.OutputsKnown_A 00729016417084691600
tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A 00729016417084016002322
tb.dut.u_io_div2_meas.u_err_sync.SyncReqAckAckNeedsReq 0072901641167100
tb.dut.u_io_div2_meas.u_err_sync.SyncReqAckHoldReq 00109955818167100
tb.dut.u_io_div2_meas.u_meas.RefCntVal_A 0077477400
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq 00109955818159227400
tb.dut.u_io_div2_meas.u_meas.gen_timeout_assert.ClkRatios_A 0077477400
tb.dut.u_io_div2_meas.u_meas.u_sync_ref.DstPulseCheck_A 001099558185280100
tb.dut.u_io_div2_meas.u_meas.u_sync_ref.SrcPulseCheck_M 0071187425254500
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0077477400
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.OutputsKnown_A 0010995581810995581800
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A 0010995581810995581800
tb.dut.u_io_div4_div_scanmode_sync.NumCopiesMustBeGreaterZero_A 0077477400
tb.dut.u_io_div4_div_scanmode_sync.OutputsKnown_A 00729016417084691600
tb.dut.u_io_div4_div_scanmode_sync.gen_no_flops.OutputDelay_A 00729016417084691600
tb.dut.u_io_div4_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A 0077477400
tb.dut.u_io_div4_meas.u_calib_rdy_sync.OutputsKnown_A 00729016417084691600
tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A 00729016417084016002322
tb.dut.u_io_div4_meas.u_err_sync.SyncReqAckAckNeedsReq 0072901641169300
tb.dut.u_io_div4_meas.u_err_sync.SyncReqAckHoldReq 0054977509169300
tb.dut.u_io_div4_meas.u_meas.RefCntVal_A 0077477400
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq 0054977509151920300
tb.dut.u_io_div4_meas.u_meas.gen_timeout_assert.ClkRatios_A 0077477400
tb.dut.u_io_div4_meas.u_meas.u_sync_ref.DstPulseCheck_A 00549775095222100
tb.dut.u_io_div4_meas.u_meas.u_sync_ref.SrcPulseCheck_M 0071187425196600
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0077477400
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.OutputsKnown_A 00549775095497750900
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A 00549775095497750900
tb.dut.u_io_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A 0077477400
tb.dut.u_io_meas.u_calib_rdy_sync.OutputsKnown_A 00729016417084691600
tb.dut.u_io_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A 00729016417084016002322
tb.dut.u_io_meas.u_err_sync.SyncReqAckAckNeedsReq 0072901641192100
tb.dut.u_io_meas.u_err_sync.SyncReqAckHoldReq 00221350909192100
tb.dut.u_io_meas.u_meas.RefCntVal_A 0077477400
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq 00221350909159239400
tb.dut.u_io_meas.u_meas.gen_timeout_assert.ClkRatios_A 0077477400
tb.dut.u_io_meas.u_meas.u_sync_ref.DstPulseCheck_A 002213509095305600
tb.dut.u_io_meas.u_meas.u_sync_ref.SrcPulseCheck_M 0071187425280000
tb.dut.u_io_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0077477400
tb.dut.u_io_root_ctrl.u_scanmode_sync.OutputsKnown_A 0022135090921954910800
tb.dut.u_io_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A 0022135090921954910800
tb.dut.u_io_step_down_req_sync.NumCopiesMustBeGreaterZero_A 0077477400
tb.dut.u_io_step_down_req_sync.OutputsKnown_A 0022135090921776884200
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputDelay_A 0022135090921776227502322
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A 002213509091810700
tb.dut.u_main_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A 0077477400
tb.dut.u_main_meas.u_calib_rdy_sync.OutputsKnown_A 00729016417084691600
tb.dut.u_main_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A 00729016417084016002322
tb.dut.u_main_meas.u_err_sync.SyncReqAckAckNeedsReq 0072901641153400
tb.dut.u_main_meas.u_err_sync.SyncReqAckHoldReq 00236483738153400
tb.dut.u_main_meas.u_meas.RefCntVal_A 0077477400
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq 00236483738159465000
tb.dut.u_main_meas.u_meas.gen_timeout_assert.ClkRatios_A 0077477400
tb.dut.u_main_meas.u_meas.u_sync_ref.DstPulseCheck_A 002364837386307700
tb.dut.u_main_meas.u_meas.u_sync_ref.SrcPulseCheck_M 0070934386251100
tb.dut.u_main_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0077477400
tb.dut.u_main_root_ctrl.u_scanmode_sync.OutputsKnown_A 0023648373823460466600
tb.dut.u_main_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A 0023648373823460466600
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.DivEven_A 0077477400
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic.selKnown0 0010977508810977431400
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic.selKnown1 0022135090922135013500
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic.selKnown0 0010995581810995504400
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic.selKnown1 0022135090922135013500
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.DivEven_A 0077477400
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic.selKnown0 00549775095497673500
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic.selKnown1 0022135090922135013500
tb.dut.u_prim_mubi4_sender_clk_io_div2_infra.OutputsKnown_A 0010995581810906521600
tb.dut.u_prim_mubi4_sender_clk_io_div2_peri.OutputsKnown_A 0010995581810906521600
tb.dut.u_prim_mubi4_sender_clk_io_div4_infra.OutputsKnown_A 00549775095453226900
tb.dut.u_prim_mubi4_sender_clk_io_div4_peri.OutputsKnown_A 00549775095453226900
tb.dut.u_prim_mubi4_sender_clk_io_div4_secure.OutputsKnown_A 00549775095453226900
tb.dut.u_prim_mubi4_sender_clk_io_div4_timers.OutputsKnown_A 00549775095453226900
tb.dut.u_prim_mubi4_sender_clk_io_infra.OutputsKnown_A 0022135090921776884200
tb.dut.u_prim_mubi4_sender_clk_io_peri.OutputsKnown_A 0022135090921776884200
tb.dut.u_prim_mubi4_sender_clk_main_infra.OutputsKnown_A 0023648373823274637700
tb.dut.u_prim_mubi4_sender_clk_main_secure.OutputsKnown_A 0023648373823274637700
tb.dut.u_prim_mubi4_sender_clk_usb_infra.OutputsKnown_A 0011337798011158797600
tb.dut.u_prim_mubi4_sender_clk_usb_peri.OutputsKnown_A 0011337798011158797600
tb.dut.u_reg.en2addrHit 007382870144852100
tb.dut.u_reg.reAfterRv 007382870144852100
tb.dut.u_reg.rePulse 007382870112413900
tb.dut.u_reg.u_chk.PayLoadWidthCheck 0097997900
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.BusySrcReqChk_A 00738287016874300
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.DstReqKnown_A 0011119020011025382500
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.SrcAckBusyChk_A 00738287011451100
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.SrcBusyKnown_A 00738287017166474000
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A 0011119020064000
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq 00738287011515100
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq 001111902001450700
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A 001111902001451100
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M 00738287011451100
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.BusySrcReqChk_A 007382870110014000
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.DstReqKnown_A 0011119020011025382500
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A 00738287012025300
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.SrcBusyKnown_A 00738287017166474000
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 00738287012025000
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 001111902002026100
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A 001111902002025800
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M 00738287012027900
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A 0097997900
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A 0011119020011025382500
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A 00738287013100
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M 001111902003100
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A 0097997900
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A 0011119020011025382500
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A 00738287013100
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M 001111902003100
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.BusySrcReqChk_A 007382870110766000
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.DstReqKnown_A 00555946845512659600
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.SrcAckBusyChk_A 00738287011451100
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.SrcBusyKnown_A 00738287017166474000
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A 005559468464000
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq 00738287011515100
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq 00555946841444800
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A 00555946841451100
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M 00738287011451100
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.BusySrcReqChk_A 007382870115717600
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.DstReqKnown_A 00555946845512659600
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A 00738287012007800
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.SrcBusyKnown_A 00738287017166474000
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 00738287012007700
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00555946842008200
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A 00555946842007900
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M 00738287012010600
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A 0097997900
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A 00555946845512659600
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A 00738287013100
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M 00555946843100
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A 0097997900
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A 00555946845512659600
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A 00738287013100
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M 00555946843100
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.BusySrcReqChk_A 00738287014836700
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.DstReqKnown_A 0022391064022014610400
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.SrcAckBusyChk_A 00738287011451100
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.SrcBusyKnown_A 00738287017166474000
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A 0022391064064000
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq 00738287011515100
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq 002239106401451100
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A 002239106401451100
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M 00738287011451100
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.BusySrcReqChk_A 00738287017004100
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.DstReqKnown_A 0022391064022014610400
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A 00738287012022000
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.SrcBusyKnown_A 00738287017166474000
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 00738287012021800
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 002239106402022900
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A 002239106402022200
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M 00738287012023900
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A 0097997900
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A 0022391064022014610400
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A 00738287012700
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M 002239106402700
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A 0097997900
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A 0022391064022014610400
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A 00738287013000
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M 002239106403000
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.BusySrcReqChk_A 00738287014743300
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.DstReqKnown_A 0023915023023522278000
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.SrcAckBusyChk_A 00738287011451100
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.SrcBusyKnown_A 00738287017166474000
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A 0023915023064000
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq 00738287011515100
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq 002391502301451100
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A 002391502301451100
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M 00738287011451100
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.BusySrcReqChk_A 00738287016811000
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.DstReqKnown_A 0023915023023522278000
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A 00738287012003800
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.SrcBusyKnown_A 00738287017166474000
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 00738287012003400
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 002391502302004800
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A 002391502302004200
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M 00738287012005900
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A 0097997900
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A 0023915023023522278000
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A 00738287013100
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M 002391502303100
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A 0097997900
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A 0023915023023522278000
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A 00738287013300
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M 002391502303300
tb.dut.u_reg.u_reg_if.AllowedLatency_A 0097997900
tb.dut.u_reg.u_reg_if.MatchedWidthAssert 0097997900
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A 0097997900
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 0097997900
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 0097997900
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A 0097997900
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck 0097997900
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.BusySrcReqChk_A 00738287016653600
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.DstReqKnown_A 0011465787211277667800
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.SrcAckBusyChk_A 00738287011399900
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.SrcBusyKnown_A 00738287017166474000
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A 0011465787264000
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq 00738287011463900
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq 001146578721386400
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A 001146578721405700
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M 00738287011451100
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.BusySrcReqChk_A 00738287019834200
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.DstReqKnown_A 0011465787211277667800
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A 00738287011983700
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.SrcBusyKnown_A 00738287017166474000
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 00738287011979400
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 001146578721999900
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A 001146578721996200
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M 00738287012019400
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A 0097997900
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A 0011465787211277667800
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A 00738287013300
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M 001146578723300
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A 0097997900
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A 0011465787211277667800
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A 00738287013500
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M 001146578723500
tb.dut.u_reg.wePulse 007382870132438200
tb.dut.u_usb_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A 0077477400
tb.dut.u_usb_meas.u_calib_rdy_sync.OutputsKnown_A 00729016417084691600
tb.dut.u_usb_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A 00729016417084016002322
tb.dut.u_usb_meas.u_err_sync.SyncReqAckAckNeedsReq 0072901641158000
tb.dut.u_usb_meas.u_err_sync.SyncReqAckHoldReq 00113377980158000
tb.dut.u_usb_meas.u_meas.RefCntVal_A 0077477400
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq 00113377980159444000
tb.dut.u_usb_meas.u_meas.gen_timeout_assert.ClkRatios_A 0077477400
tb.dut.u_usb_meas.u_meas.u_sync_ref.DstPulseCheck_A 001133779806171700
tb.dut.u_usb_meas.u_meas.u_sync_ref.SrcPulseCheck_M 0071784626122000
tb.dut.u_usb_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0077477400
tb.dut.u_usb_root_ctrl.u_scanmode_sync.OutputsKnown_A 0011337798011247768600
tb.dut.u_usb_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011337798011247768600

Assertions Incomplete:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.clkmgr_lost_calib_regwen_sva_if.RegwenOff_A 007290164111170118055
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqFalse_A 00729016417070931002322
tb.dut.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A 00729016417084016002322
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A 0023648373823273973202322
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A 0023648373823273973202322
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A 0023648373823273973202322
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A 0023648373823273973202322
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A 00729016417084016002322
tb.dut.u_clkmgr_byp.u_en_sync.gen_flops.OutputDelay_A 00729016417084016002322
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A 00729016417084016002322
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_flops.OutputDelay_A 00729016417084016002322
tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A 00729016417084016002322
tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A 00729016417084016002322
tb.dut.u_io_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A 00729016417084016002322
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputDelay_A 0022135090921776227502322
tb.dut.u_main_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A 00729016417084016002322
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A 0011119020000979
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A 005559468400979
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A 0022391064000979
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A 0023915023000979
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A 0011465787200979
tb.dut.u_usb_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A 00729016417084016002322


Detail Report for Cover Sequences

Cover Sequences Uncovered:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 0073829320000
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0073829320000
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 0073829320000
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 0073829320000
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 0073829320000
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 0073829320000

Cover Sequences All Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0073829320962796270
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 0073829320450745070
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 007382932014745147450
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 00738293209251392513755

Cover Sequences First Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0073829320962796270
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 0073829320450745070
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 007382932014745147450
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 00738293209251392513755

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