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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80


Total test records in report: 979
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T804 /workspace/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.1579990362 Jul 24 07:09:23 PM PDT 24 Jul 24 07:09:24 PM PDT 24 86446626 ps
T805 /workspace/coverage/default/37.clkmgr_alert_test.3422710903 Jul 24 07:09:21 PM PDT 24 Jul 24 07:09:23 PM PDT 24 57751494 ps
T806 /workspace/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.2711677920 Jul 24 07:09:18 PM PDT 24 Jul 24 07:09:19 PM PDT 24 12322570 ps
T807 /workspace/coverage/default/32.clkmgr_frequency_timeout.3425525769 Jul 24 07:09:19 PM PDT 24 Jul 24 07:09:21 PM PDT 24 135359221 ps
T808 /workspace/coverage/default/43.clkmgr_alert_test.3304644326 Jul 24 07:09:39 PM PDT 24 Jul 24 07:09:40 PM PDT 24 18005590 ps
T809 /workspace/coverage/default/14.clkmgr_div_intersig_mubi.2652658586 Jul 24 07:08:35 PM PDT 24 Jul 24 07:08:36 PM PDT 24 43151811 ps
T810 /workspace/coverage/default/48.clkmgr_idle_intersig_mubi.1840373923 Jul 24 07:09:53 PM PDT 24 Jul 24 07:09:59 PM PDT 24 15054649 ps
T811 /workspace/coverage/default/10.clkmgr_clk_status.154831293 Jul 24 07:08:21 PM PDT 24 Jul 24 07:08:22 PM PDT 24 16861707 ps
T812 /workspace/coverage/default/8.clkmgr_extclk.3862514881 Jul 24 07:08:19 PM PDT 24 Jul 24 07:08:20 PM PDT 24 13224219 ps
T813 /workspace/coverage/default/26.clkmgr_extclk.224874835 Jul 24 07:09:02 PM PDT 24 Jul 24 07:09:03 PM PDT 24 73278986 ps
T814 /workspace/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.1609349375 Jul 24 07:08:40 PM PDT 24 Jul 24 07:08:41 PM PDT 24 23760008 ps
T815 /workspace/coverage/default/28.clkmgr_clk_status.251604535 Jul 24 07:09:16 PM PDT 24 Jul 24 07:09:17 PM PDT 24 135004634 ps
T816 /workspace/coverage/default/18.clkmgr_stress_all_with_rand_reset.1906562867 Jul 24 07:08:34 PM PDT 24 Jul 24 07:18:29 PM PDT 24 124442479691 ps
T817 /workspace/coverage/default/20.clkmgr_idle_intersig_mubi.1758116676 Jul 24 07:08:42 PM PDT 24 Jul 24 07:08:43 PM PDT 24 25123756 ps
T818 /workspace/coverage/default/0.clkmgr_smoke.3677869543 Jul 24 07:07:55 PM PDT 24 Jul 24 07:07:57 PM PDT 24 50717769 ps
T819 /workspace/coverage/default/34.clkmgr_extclk.2258366838 Jul 24 07:09:16 PM PDT 24 Jul 24 07:09:17 PM PDT 24 18243594 ps
T820 /workspace/coverage/default/25.clkmgr_smoke.256744203 Jul 24 07:08:55 PM PDT 24 Jul 24 07:08:56 PM PDT 24 73198974 ps
T821 /workspace/coverage/default/28.clkmgr_trans.3310853755 Jul 24 07:09:13 PM PDT 24 Jul 24 07:09:14 PM PDT 24 42789258 ps
T822 /workspace/coverage/default/22.clkmgr_peri.4138331948 Jul 24 07:08:43 PM PDT 24 Jul 24 07:08:44 PM PDT 24 18470026 ps
T823 /workspace/coverage/default/7.clkmgr_smoke.548634210 Jul 24 07:08:14 PM PDT 24 Jul 24 07:08:15 PM PDT 24 76075329 ps
T824 /workspace/coverage/default/30.clkmgr_frequency.1327029624 Jul 24 07:09:13 PM PDT 24 Jul 24 07:09:17 PM PDT 24 708879712 ps
T825 /workspace/coverage/default/3.clkmgr_peri.932932053 Jul 24 07:08:00 PM PDT 24 Jul 24 07:08:01 PM PDT 24 18250291 ps
T826 /workspace/coverage/default/6.clkmgr_alert_test.1573854947 Jul 24 07:08:09 PM PDT 24 Jul 24 07:08:10 PM PDT 24 39820677 ps
T827 /workspace/coverage/default/38.clkmgr_trans.3907502365 Jul 24 07:09:33 PM PDT 24 Jul 24 07:09:34 PM PDT 24 37613806 ps
T828 /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.111448572 Jul 24 07:03:10 PM PDT 24 Jul 24 07:03:11 PM PDT 24 49365087 ps
T829 /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.2555818785 Jul 24 07:02:45 PM PDT 24 Jul 24 07:02:46 PM PDT 24 18593979 ps
T56 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.3525385701 Jul 24 07:03:01 PM PDT 24 Jul 24 07:03:03 PM PDT 24 143371157 ps
T101 /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.4242661987 Jul 24 07:02:37 PM PDT 24 Jul 24 07:02:41 PM PDT 24 208280128 ps
T102 /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.312856464 Jul 24 07:03:07 PM PDT 24 Jul 24 07:03:09 PM PDT 24 71817897 ps
T154 /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.98918886 Jul 24 07:02:36 PM PDT 24 Jul 24 07:02:41 PM PDT 24 277256232 ps
T95 /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.832666911 Jul 24 07:03:01 PM PDT 24 Jul 24 07:03:05 PM PDT 24 436284773 ps
T830 /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.1208248687 Jul 24 07:02:44 PM PDT 24 Jul 24 07:02:45 PM PDT 24 17395071 ps
T831 /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.504678319 Jul 24 07:03:01 PM PDT 24 Jul 24 07:03:02 PM PDT 24 11294351 ps
T832 /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.2438275009 Jul 24 07:02:56 PM PDT 24 Jul 24 07:02:57 PM PDT 24 16954186 ps
T57 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.2075036017 Jul 24 07:02:37 PM PDT 24 Jul 24 07:02:39 PM PDT 24 86745113 ps
T58 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.1340845673 Jul 24 07:02:32 PM PDT 24 Jul 24 07:02:34 PM PDT 24 78676400 ps
T833 /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.1053900224 Jul 24 07:03:15 PM PDT 24 Jul 24 07:03:16 PM PDT 24 22241041 ps
T834 /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.3830292532 Jul 24 07:03:17 PM PDT 24 Jul 24 07:03:19 PM PDT 24 27813267 ps
T84 /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.2565058474 Jul 24 07:03:06 PM PDT 24 Jul 24 07:03:07 PM PDT 24 19897424 ps
T85 /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.1045677901 Jul 24 07:02:55 PM PDT 24 Jul 24 07:02:56 PM PDT 24 18259101 ps
T61 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.1843962281 Jul 24 07:03:01 PM PDT 24 Jul 24 07:03:04 PM PDT 24 93387861 ps
T835 /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.565150863 Jul 24 07:03:26 PM PDT 24 Jul 24 07:03:27 PM PDT 24 41175032 ps
T96 /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.885827075 Jul 24 07:02:47 PM PDT 24 Jul 24 07:02:49 PM PDT 24 107648818 ps
T836 /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.1249496282 Jul 24 07:02:30 PM PDT 24 Jul 24 07:02:34 PM PDT 24 301109008 ps
T837 /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.4085985443 Jul 24 07:02:40 PM PDT 24 Jul 24 07:02:41 PM PDT 24 18072901 ps
T838 /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.2180263736 Jul 24 07:02:38 PM PDT 24 Jul 24 07:02:39 PM PDT 24 28085688 ps
T839 /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.1422000599 Jul 24 07:03:17 PM PDT 24 Jul 24 07:03:18 PM PDT 24 22194888 ps
T97 /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.2787301869 Jul 24 07:02:55 PM PDT 24 Jul 24 07:02:57 PM PDT 24 69358893 ps
T840 /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.3040447479 Jul 24 07:03:17 PM PDT 24 Jul 24 07:03:17 PM PDT 24 53998021 ps
T841 /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.2296019823 Jul 24 07:03:09 PM PDT 24 Jul 24 07:03:13 PM PDT 24 138151569 ps
T109 /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.3121082652 Jul 24 07:03:02 PM PDT 24 Jul 24 07:03:05 PM PDT 24 284546822 ps
T62 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.2611422268 Jul 24 07:03:01 PM PDT 24 Jul 24 07:03:04 PM PDT 24 96038366 ps
T842 /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.1413081238 Jul 24 07:02:55 PM PDT 24 Jul 24 07:02:57 PM PDT 24 79365321 ps
T65 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.474360305 Jul 24 07:02:48 PM PDT 24 Jul 24 07:02:51 PM PDT 24 175267446 ps
T63 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.2232793903 Jul 24 07:02:42 PM PDT 24 Jul 24 07:02:44 PM PDT 24 70988763 ps
T843 /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.1394373531 Jul 24 07:02:37 PM PDT 24 Jul 24 07:02:39 PM PDT 24 73077276 ps
T86 /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.866799527 Jul 24 07:02:55 PM PDT 24 Jul 24 07:02:56 PM PDT 24 66122885 ps
T64 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.673897038 Jul 24 07:03:07 PM PDT 24 Jul 24 07:03:09 PM PDT 24 224691771 ps
T107 /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.1724609006 Jul 24 07:02:40 PM PDT 24 Jul 24 07:02:42 PM PDT 24 322759024 ps
T844 /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.1767975962 Jul 24 07:03:18 PM PDT 24 Jul 24 07:03:19 PM PDT 24 26670946 ps
T66 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.1839720459 Jul 24 07:02:34 PM PDT 24 Jul 24 07:02:37 PM PDT 24 158537837 ps
T87 /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.1435001050 Jul 24 07:03:02 PM PDT 24 Jul 24 07:03:03 PM PDT 24 18629457 ps
T845 /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.2562729415 Jul 24 07:03:01 PM PDT 24 Jul 24 07:03:03 PM PDT 24 24572273 ps
T846 /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.1674743879 Jul 24 07:02:56 PM PDT 24 Jul 24 07:02:57 PM PDT 24 20094554 ps
T59 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.2357611276 Jul 24 07:02:51 PM PDT 24 Jul 24 07:02:53 PM PDT 24 201140640 ps
T847 /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.2998305580 Jul 24 07:03:16 PM PDT 24 Jul 24 07:03:17 PM PDT 24 34307214 ps
T60 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.2200684878 Jul 24 07:03:07 PM PDT 24 Jul 24 07:03:09 PM PDT 24 280725976 ps
T848 /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.2242533475 Jul 24 07:03:16 PM PDT 24 Jul 24 07:03:17 PM PDT 24 30983993 ps
T849 /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.3008782825 Jul 24 07:03:06 PM PDT 24 Jul 24 07:03:09 PM PDT 24 83751066 ps
T850 /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.1399867462 Jul 24 07:02:35 PM PDT 24 Jul 24 07:02:36 PM PDT 24 39473329 ps
T851 /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.327174374 Jul 24 07:03:01 PM PDT 24 Jul 24 07:03:04 PM PDT 24 101888383 ps
T852 /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.3258165216 Jul 24 07:02:55 PM PDT 24 Jul 24 07:02:56 PM PDT 24 15575629 ps
T853 /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.2415139897 Jul 24 07:03:01 PM PDT 24 Jul 24 07:03:02 PM PDT 24 166535807 ps
T854 /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.204866086 Jul 24 07:02:34 PM PDT 24 Jul 24 07:02:35 PM PDT 24 47093198 ps
T855 /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.437209460 Jul 24 07:02:55 PM PDT 24 Jul 24 07:03:04 PM PDT 24 1347818487 ps
T856 /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.4247664496 Jul 24 07:02:55 PM PDT 24 Jul 24 07:02:57 PM PDT 24 31318026 ps
T857 /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.1238535178 Jul 24 07:02:48 PM PDT 24 Jul 24 07:02:51 PM PDT 24 340158440 ps
T858 /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.1416947976 Jul 24 07:02:40 PM PDT 24 Jul 24 07:02:42 PM PDT 24 185572808 ps
T134 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.3908951372 Jul 24 07:03:03 PM PDT 24 Jul 24 07:03:05 PM PDT 24 151329158 ps
T859 /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.3637145358 Jul 24 07:02:34 PM PDT 24 Jul 24 07:02:36 PM PDT 24 33537349 ps
T860 /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.3530877458 Jul 24 07:02:42 PM PDT 24 Jul 24 07:02:44 PM PDT 24 21957337 ps
T861 /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.4014963469 Jul 24 07:02:35 PM PDT 24 Jul 24 07:02:36 PM PDT 24 38328563 ps
T163 /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.4006427580 Jul 24 07:02:54 PM PDT 24 Jul 24 07:02:56 PM PDT 24 115954054 ps
T862 /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.1766567157 Jul 24 07:03:09 PM PDT 24 Jul 24 07:03:11 PM PDT 24 68931710 ps
T863 /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.2970509678 Jul 24 07:02:43 PM PDT 24 Jul 24 07:02:46 PM PDT 24 244114654 ps
T864 /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.3316510138 Jul 24 07:03:00 PM PDT 24 Jul 24 07:03:02 PM PDT 24 56469929 ps
T865 /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.2416108853 Jul 24 07:03:16 PM PDT 24 Jul 24 07:03:17 PM PDT 24 10780127 ps
T866 /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.111233664 Jul 24 07:02:49 PM PDT 24 Jul 24 07:02:52 PM PDT 24 149154055 ps
T867 /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.3151474762 Jul 24 07:03:17 PM PDT 24 Jul 24 07:03:18 PM PDT 24 144830323 ps
T126 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.1251355203 Jul 24 07:02:42 PM PDT 24 Jul 24 07:02:45 PM PDT 24 217258671 ps
T868 /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.927083602 Jul 24 07:02:34 PM PDT 24 Jul 24 07:02:35 PM PDT 24 46356984 ps
T869 /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.2712601586 Jul 24 07:03:10 PM PDT 24 Jul 24 07:03:11 PM PDT 24 61843560 ps
T870 /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.3533149674 Jul 24 07:02:53 PM PDT 24 Jul 24 07:02:54 PM PDT 24 55325512 ps
T871 /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.1185508726 Jul 24 07:02:35 PM PDT 24 Jul 24 07:02:52 PM PDT 24 3659153188 ps
T122 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.1802559584 Jul 24 07:03:01 PM PDT 24 Jul 24 07:03:02 PM PDT 24 50122210 ps
T872 /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.3454426981 Jul 24 07:02:42 PM PDT 24 Jul 24 07:02:43 PM PDT 24 34836622 ps
T108 /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.3445604382 Jul 24 07:03:01 PM PDT 24 Jul 24 07:03:03 PM PDT 24 330508782 ps
T873 /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.3201384192 Jul 24 07:02:54 PM PDT 24 Jul 24 07:02:56 PM PDT 24 46308807 ps
T99 /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.4121711193 Jul 24 07:02:56 PM PDT 24 Jul 24 07:02:59 PM PDT 24 121632638 ps
T874 /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.725699687 Jul 24 07:02:36 PM PDT 24 Jul 24 07:02:43 PM PDT 24 277242732 ps
T875 /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.3619759666 Jul 24 07:03:17 PM PDT 24 Jul 24 07:03:18 PM PDT 24 13922293 ps
T876 /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.277376119 Jul 24 07:02:47 PM PDT 24 Jul 24 07:02:50 PM PDT 24 83261599 ps
T877 /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.2469703402 Jul 24 07:03:07 PM PDT 24 Jul 24 07:03:09 PM PDT 24 100275280 ps
T878 /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.2768815104 Jul 24 07:02:37 PM PDT 24 Jul 24 07:02:38 PM PDT 24 31299581 ps
T879 /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.4188693106 Jul 24 07:02:54 PM PDT 24 Jul 24 07:02:54 PM PDT 24 26239913 ps
T117 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.3476586408 Jul 24 07:03:01 PM PDT 24 Jul 24 07:03:03 PM PDT 24 155561743 ps
T127 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.3602618914 Jul 24 07:02:50 PM PDT 24 Jul 24 07:02:52 PM PDT 24 346742916 ps
T880 /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.931694615 Jul 24 07:02:34 PM PDT 24 Jul 24 07:02:35 PM PDT 24 13228543 ps
T881 /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.3835298380 Jul 24 07:03:10 PM PDT 24 Jul 24 07:03:11 PM PDT 24 18941417 ps
T882 /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.1123282044 Jul 24 07:03:02 PM PDT 24 Jul 24 07:03:04 PM PDT 24 85191436 ps
T883 /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.270579798 Jul 24 07:03:17 PM PDT 24 Jul 24 07:03:18 PM PDT 24 45986429 ps
T884 /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.2284380874 Jul 24 07:03:16 PM PDT 24 Jul 24 07:03:17 PM PDT 24 13578122 ps
T103 /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.1157787293 Jul 24 07:03:08 PM PDT 24 Jul 24 07:03:10 PM PDT 24 143749712 ps
T110 /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.3612713043 Jul 24 07:03:00 PM PDT 24 Jul 24 07:03:04 PM PDT 24 203217866 ps
T885 /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.1585497534 Jul 24 07:03:15 PM PDT 24 Jul 24 07:03:17 PM PDT 24 39589441 ps
T886 /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.3836847821 Jul 24 07:02:50 PM PDT 24 Jul 24 07:02:51 PM PDT 24 55244855 ps
T887 /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.1709494306 Jul 24 07:04:59 PM PDT 24 Jul 24 07:04:59 PM PDT 24 20086279 ps
T118 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.1774547994 Jul 24 07:02:50 PM PDT 24 Jul 24 07:02:54 PM PDT 24 217201828 ps
T888 /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.3080661676 Jul 24 07:02:54 PM PDT 24 Jul 24 07:02:55 PM PDT 24 39231966 ps
T889 /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.3242920960 Jul 24 07:02:35 PM PDT 24 Jul 24 07:02:38 PM PDT 24 139921795 ps
T890 /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.3741828922 Jul 24 07:02:49 PM PDT 24 Jul 24 07:02:50 PM PDT 24 53222597 ps
T891 /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.4020307713 Jul 24 07:02:55 PM PDT 24 Jul 24 07:02:56 PM PDT 24 27126532 ps
T892 /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.887173295 Jul 24 07:03:15 PM PDT 24 Jul 24 07:03:15 PM PDT 24 11566479 ps
T128 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.4245038900 Jul 24 07:02:28 PM PDT 24 Jul 24 07:02:30 PM PDT 24 180993022 ps
T893 /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.644049371 Jul 24 07:02:42 PM PDT 24 Jul 24 07:02:44 PM PDT 24 33419595 ps
T894 /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.114851312 Jul 24 07:03:01 PM PDT 24 Jul 24 07:03:03 PM PDT 24 89365684 ps
T895 /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.4264326254 Jul 24 07:03:02 PM PDT 24 Jul 24 07:03:04 PM PDT 24 101178831 ps
T896 /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.1873698436 Jul 24 07:03:16 PM PDT 24 Jul 24 07:03:17 PM PDT 24 13899113 ps
T897 /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.1421716383 Jul 24 07:02:35 PM PDT 24 Jul 24 07:02:37 PM PDT 24 95507168 ps
T898 /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.3156905199 Jul 24 07:02:36 PM PDT 24 Jul 24 07:02:37 PM PDT 24 35165683 ps
T119 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.826067967 Jul 24 07:02:29 PM PDT 24 Jul 24 07:02:32 PM PDT 24 253114174 ps
T899 /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.1916382347 Jul 24 07:03:02 PM PDT 24 Jul 24 07:03:04 PM PDT 24 58072567 ps
T900 /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.1601991162 Jul 24 07:02:56 PM PDT 24 Jul 24 07:02:57 PM PDT 24 62639938 ps
T901 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.4052276604 Jul 24 07:02:35 PM PDT 24 Jul 24 07:02:37 PM PDT 24 89211677 ps
T902 /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.3143814884 Jul 24 07:02:36 PM PDT 24 Jul 24 07:02:38 PM PDT 24 103329939 ps
T903 /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.2877117780 Jul 24 07:02:50 PM PDT 24 Jul 24 07:02:51 PM PDT 24 20559620 ps
T904 /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.1256391403 Jul 24 07:03:18 PM PDT 24 Jul 24 07:03:19 PM PDT 24 41811173 ps
T120 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.921382121 Jul 24 07:02:42 PM PDT 24 Jul 24 07:02:45 PM PDT 24 167151973 ps
T905 /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.2317882422 Jul 24 07:02:44 PM PDT 24 Jul 24 07:02:45 PM PDT 24 17491166 ps
T906 /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.2279561149 Jul 24 07:02:42 PM PDT 24 Jul 24 07:02:45 PM PDT 24 32719331 ps
T907 /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.2668153245 Jul 24 07:02:35 PM PDT 24 Jul 24 07:02:37 PM PDT 24 41552291 ps
T908 /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.3615250009 Jul 24 07:02:43 PM PDT 24 Jul 24 07:02:44 PM PDT 24 22228583 ps
T909 /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.2465056652 Jul 24 07:03:07 PM PDT 24 Jul 24 07:03:10 PM PDT 24 115355078 ps
T910 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.3202500310 Jul 24 07:02:56 PM PDT 24 Jul 24 07:02:58 PM PDT 24 71464986 ps
T911 /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.354043549 Jul 24 07:03:18 PM PDT 24 Jul 24 07:03:19 PM PDT 24 32784103 ps
T912 /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.874954385 Jul 24 07:03:09 PM PDT 24 Jul 24 07:03:10 PM PDT 24 41591210 ps
T913 /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.3055640953 Jul 24 07:02:52 PM PDT 24 Jul 24 07:02:53 PM PDT 24 27666310 ps
T914 /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.3133824753 Jul 24 07:02:47 PM PDT 24 Jul 24 07:02:50 PM PDT 24 171544521 ps
T915 /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.2686260237 Jul 24 07:02:36 PM PDT 24 Jul 24 07:02:37 PM PDT 24 21307265 ps
T916 /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.1779679694 Jul 24 07:02:44 PM PDT 24 Jul 24 07:02:45 PM PDT 24 151030377 ps
T917 /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.1364398551 Jul 24 07:02:51 PM PDT 24 Jul 24 07:02:53 PM PDT 24 127841732 ps
T136 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.3377484073 Jul 24 07:03:01 PM PDT 24 Jul 24 07:03:02 PM PDT 24 65265700 ps
T918 /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.1347580373 Jul 24 07:02:37 PM PDT 24 Jul 24 07:02:38 PM PDT 24 18201751 ps
T919 /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.1474884621 Jul 24 07:02:53 PM PDT 24 Jul 24 07:02:54 PM PDT 24 102713195 ps
T121 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.3096941934 Jul 24 07:02:56 PM PDT 24 Jul 24 07:02:57 PM PDT 24 55805520 ps
T920 /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.3028369905 Jul 24 07:03:17 PM PDT 24 Jul 24 07:03:18 PM PDT 24 21096615 ps
T137 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.1304669923 Jul 24 07:03:03 PM PDT 24 Jul 24 07:03:05 PM PDT 24 185995633 ps
T130 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.3934829986 Jul 24 07:03:08 PM PDT 24 Jul 24 07:03:12 PM PDT 24 472753158 ps
T921 /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.800009356 Jul 24 07:02:38 PM PDT 24 Jul 24 07:02:39 PM PDT 24 11618022 ps
T922 /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.1761023579 Jul 24 07:03:08 PM PDT 24 Jul 24 07:03:09 PM PDT 24 42246873 ps
T923 /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.2688031459 Jul 24 07:02:42 PM PDT 24 Jul 24 07:02:44 PM PDT 24 27701561 ps
T924 /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.630556731 Jul 24 07:02:53 PM PDT 24 Jul 24 07:02:54 PM PDT 24 40967441 ps
T131 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.709838351 Jul 24 07:02:54 PM PDT 24 Jul 24 07:02:55 PM PDT 24 96480210 ps
T925 /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.3076132889 Jul 24 07:03:15 PM PDT 24 Jul 24 07:03:16 PM PDT 24 24879610 ps
T926 /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.260074683 Jul 24 07:03:17 PM PDT 24 Jul 24 07:03:18 PM PDT 24 19156253 ps
T927 /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.188981618 Jul 24 07:03:17 PM PDT 24 Jul 24 07:03:18 PM PDT 24 20033288 ps
T928 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.3848322808 Jul 24 07:02:49 PM PDT 24 Jul 24 07:02:51 PM PDT 24 251504419 ps
T104 /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.352957018 Jul 24 07:03:10 PM PDT 24 Jul 24 07:03:13 PM PDT 24 261188859 ps
T929 /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.3845923827 Jul 24 07:02:53 PM PDT 24 Jul 24 07:02:54 PM PDT 24 16227794 ps
T930 /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.3887257644 Jul 24 07:03:00 PM PDT 24 Jul 24 07:03:02 PM PDT 24 106326390 ps
T931 /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.1118899841 Jul 24 07:03:16 PM PDT 24 Jul 24 07:03:17 PM PDT 24 36881159 ps
T932 /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.3684415470 Jul 24 07:03:06 PM PDT 24 Jul 24 07:03:07 PM PDT 24 75572475 ps
T106 /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.67131643 Jul 24 07:02:38 PM PDT 24 Jul 24 07:02:40 PM PDT 24 128913557 ps
T933 /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.4195645390 Jul 24 07:02:35 PM PDT 24 Jul 24 07:02:37 PM PDT 24 389688118 ps
T129 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.3698728319 Jul 24 07:03:14 PM PDT 24 Jul 24 07:03:15 PM PDT 24 69817271 ps
T934 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.3118309997 Jul 24 07:02:40 PM PDT 24 Jul 24 07:02:43 PM PDT 24 95388668 ps
T935 /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.4175470624 Jul 24 07:02:42 PM PDT 24 Jul 24 07:02:43 PM PDT 24 16016659 ps
T936 /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.4140341560 Jul 24 07:02:36 PM PDT 24 Jul 24 07:02:38 PM PDT 24 201538257 ps
T937 /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.3883423073 Jul 24 07:03:16 PM PDT 24 Jul 24 07:03:17 PM PDT 24 15217006 ps
T938 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.2062871577 Jul 24 07:02:44 PM PDT 24 Jul 24 07:02:48 PM PDT 24 756841061 ps
T939 /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.3300623297 Jul 24 07:02:34 PM PDT 24 Jul 24 07:02:35 PM PDT 24 35786382 ps
T940 /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.3189852412 Jul 24 07:03:09 PM PDT 24 Jul 24 07:03:10 PM PDT 24 29607298 ps
T105 /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.2537541025 Jul 24 07:02:41 PM PDT 24 Jul 24 07:02:45 PM PDT 24 250957978 ps
T941 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.584333177 Jul 24 07:02:50 PM PDT 24 Jul 24 07:02:52 PM PDT 24 176488241 ps
T942 /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.4271103505 Jul 24 07:02:35 PM PDT 24 Jul 24 07:02:36 PM PDT 24 26303950 ps
T943 /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.876962942 Jul 24 07:02:56 PM PDT 24 Jul 24 07:02:57 PM PDT 24 67380732 ps
T944 /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.3233989161 Jul 24 07:03:01 PM PDT 24 Jul 24 07:03:02 PM PDT 24 24087813 ps
T945 /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.1779368842 Jul 24 07:03:17 PM PDT 24 Jul 24 07:03:18 PM PDT 24 20028923 ps
T946 /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.2464359437 Jul 24 07:03:07 PM PDT 24 Jul 24 07:03:08 PM PDT 24 15310218 ps
T947 /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.2414901551 Jul 24 07:02:36 PM PDT 24 Jul 24 07:02:38 PM PDT 24 66115397 ps
T948 /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.1671013173 Jul 24 07:03:14 PM PDT 24 Jul 24 07:03:15 PM PDT 24 32133143 ps
T949 /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.1904346791 Jul 24 07:03:07 PM PDT 24 Jul 24 07:03:08 PM PDT 24 89163972 ps
T950 /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.2399711105 Jul 24 07:03:18 PM PDT 24 Jul 24 07:03:19 PM PDT 24 12284576 ps
T951 /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.2352961149 Jul 24 07:02:43 PM PDT 24 Jul 24 07:02:45 PM PDT 24 57222741 ps
T135 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.2037547595 Jul 24 07:02:38 PM PDT 24 Jul 24 07:02:40 PM PDT 24 155675128 ps
T952 /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.3319087474 Jul 24 07:02:42 PM PDT 24 Jul 24 07:02:43 PM PDT 24 156895914 ps
T953 /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.426015335 Jul 24 07:03:01 PM PDT 24 Jul 24 07:03:02 PM PDT 24 22868630 ps
T954 /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.199023118 Jul 24 07:03:14 PM PDT 24 Jul 24 07:03:15 PM PDT 24 11057069 ps
T955 /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.3952274080 Jul 24 07:02:49 PM PDT 24 Jul 24 07:02:50 PM PDT 24 58511104 ps
T956 /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.1704873064 Jul 24 07:03:04 PM PDT 24 Jul 24 07:03:08 PM PDT 24 497924388 ps
T957 /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.1812933056 Jul 24 07:02:36 PM PDT 24 Jul 24 07:02:41 PM PDT 24 770680483 ps
T123 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.3437794911 Jul 24 07:03:07 PM PDT 24 Jul 24 07:03:09 PM PDT 24 189533236 ps
T958 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.2261877571 Jul 24 07:02:55 PM PDT 24 Jul 24 07:02:58 PM PDT 24 102866537 ps
T959 /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.3139905579 Jul 24 07:03:17 PM PDT 24 Jul 24 07:03:18 PM PDT 24 31088949 ps
T960 /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.444179597 Jul 24 07:02:36 PM PDT 24 Jul 24 07:02:37 PM PDT 24 57867273 ps
T961 /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.1103275080 Jul 24 07:02:59 PM PDT 24 Jul 24 07:03:01 PM PDT 24 32485936 ps
T962 /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.1515614008 Jul 24 07:02:34 PM PDT 24 Jul 24 07:02:37 PM PDT 24 94002926 ps
T963 /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.3677747210 Jul 24 07:03:01 PM PDT 24 Jul 24 07:03:02 PM PDT 24 38711692 ps
T124 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.3456857692 Jul 24 07:03:01 PM PDT 24 Jul 24 07:03:06 PM PDT 24 1168684780 ps
T125 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.4162919346 Jul 24 07:02:44 PM PDT 24 Jul 24 07:02:46 PM PDT 24 272612637 ps
T964 /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.3747593555 Jul 24 07:03:07 PM PDT 24 Jul 24 07:03:08 PM PDT 24 21070214 ps
T965 /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.4100197517 Jul 24 07:03:08 PM PDT 24 Jul 24 07:03:08 PM PDT 24 12603050 ps
T966 /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.1134943024 Jul 24 07:02:50 PM PDT 24 Jul 24 07:02:52 PM PDT 24 32683391 ps
T967 /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.1772337660 Jul 24 07:03:01 PM PDT 24 Jul 24 07:03:04 PM PDT 24 120847398 ps
T968 /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.1124141067 Jul 24 07:03:17 PM PDT 24 Jul 24 07:03:18 PM PDT 24 31752356 ps
T969 /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.3613537316 Jul 24 07:02:47 PM PDT 24 Jul 24 07:02:51 PM PDT 24 348852272 ps
T970 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.3873833377 Jul 24 07:03:08 PM PDT 24 Jul 24 07:03:10 PM PDT 24 62496270 ps
T971 /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.2534519861 Jul 24 07:02:54 PM PDT 24 Jul 24 07:02:56 PM PDT 24 81092480 ps
T972 /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.4167447944 Jul 24 07:03:01 PM PDT 24 Jul 24 07:03:03 PM PDT 24 69654247 ps
T973 /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.703411754 Jul 24 07:02:55 PM PDT 24 Jul 24 07:02:56 PM PDT 24 41187377 ps
T974 /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.1741626455 Jul 24 07:02:48 PM PDT 24 Jul 24 07:02:49 PM PDT 24 82545378 ps
T975 /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.886915999 Jul 24 07:02:43 PM PDT 24 Jul 24 07:02:44 PM PDT 24 67508822 ps
T132 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.3628118286 Jul 24 07:02:45 PM PDT 24 Jul 24 07:02:48 PM PDT 24 158805030 ps
T976 /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.537296105 Jul 24 07:02:49 PM PDT 24 Jul 24 07:02:50 PM PDT 24 23232157 ps
T133 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.3938085874 Jul 24 07:02:52 PM PDT 24 Jul 24 07:02:55 PM PDT 24 149316564 ps
T977 /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.613549638 Jul 24 07:02:36 PM PDT 24 Jul 24 07:02:37 PM PDT 24 35397372 ps
T100 /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.2717648337 Jul 24 07:02:42 PM PDT 24 Jul 24 07:02:46 PM PDT 24 123990742 ps
T978 /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.980494723 Jul 24 07:03:17 PM PDT 24 Jul 24 07:03:18 PM PDT 24 20939250 ps
T979 /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.2335808693 Jul 24 07:02:48 PM PDT 24 Jul 24 07:02:49 PM PDT 24 30286487 ps

Test location /workspace/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.973499260
Short name T27
Test name
Test status
Simulation time 56483254 ps
CPU time 0.89 seconds
Started Jul 24 07:08:08 PM PDT 24
Finished Jul 24 07:08:09 PM PDT 24
Peak memory 200420 kb
Host smart-2cb70a48-ab80-41b6-bb0e-b6fd36260edf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973499260 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_clk_handshake_intersig_mubi.973499260
Directory /workspace/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_stress_all_with_rand_reset.2876498509
Short name T11
Test name
Test status
Simulation time 61709195670 ps
CPU time 373.86 seconds
Started Jul 24 07:08:57 PM PDT 24
Finished Jul 24 07:15:11 PM PDT 24
Peak memory 217224 kb
Host smart-0418072e-d931-487e-ac35-862946ab1705
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2876498509 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all_with_rand_reset.2876498509
Directory /workspace/24.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.clkmgr_stress_all.4122582581
Short name T3
Test name
Test status
Simulation time 2962244395 ps
CPU time 23.98 seconds
Started Jul 24 07:08:48 PM PDT 24
Finished Jul 24 07:09:13 PM PDT 24
Peak memory 200676 kb
Host smart-908b2f18-34d9-479c-b751-781d1ef6430f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122582581 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_stress_all.4122582581
Directory /workspace/23.clkmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.2357611276
Short name T59
Test name
Test status
Simulation time 201140640 ps
CPU time 1.91 seconds
Started Jul 24 07:02:51 PM PDT 24
Finished Jul 24 07:02:53 PM PDT 24
Peak memory 209360 kb
Host smart-c7d38dcc-bcdd-4a37-a8da-a90d3867b302
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357611276 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 6.clkmgr_shadow_reg_errors.2357611276
Directory /workspace/6.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/8.clkmgr_regwen.1197730661
Short name T8
Test name
Test status
Simulation time 1236397497 ps
CPU time 6.86 seconds
Started Jul 24 07:08:08 PM PDT 24
Finished Jul 24 07:08:15 PM PDT 24
Peak memory 200680 kb
Host smart-0f099c34-caa1-40bf-845e-90cd2e51d74c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197730661 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.1197730661
Directory /workspace/8.clkmgr_regwen/latest

Test location /workspace/coverage/default/41.clkmgr_clk_status.3680744041
Short name T7
Test name
Test status
Simulation time 61060803 ps
CPU time 0.84 seconds
Started Jul 24 07:09:31 PM PDT 24
Finished Jul 24 07:09:33 PM PDT 24
Peak memory 199620 kb
Host smart-11519a23-4089-4b58-98d7-79630003ad32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680744041 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.3680744041
Directory /workspace/41.clkmgr_clk_status/latest

Test location /workspace/coverage/default/0.clkmgr_sec_cm.4275791156
Short name T42
Test name
Test status
Simulation time 156859541 ps
CPU time 2.15 seconds
Started Jul 24 07:07:55 PM PDT 24
Finished Jul 24 07:07:58 PM PDT 24
Peak memory 215856 kb
Host smart-8ab8b3a5-cccb-4b13-84ca-8d73be13cd96
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275791156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmg
r_sec_cm.4275791156
Directory /workspace/0.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/32.clkmgr_alert_test.307075613
Short name T24
Test name
Test status
Simulation time 42732327 ps
CPU time 0.87 seconds
Started Jul 24 07:09:16 PM PDT 24
Finished Jul 24 07:09:17 PM PDT 24
Peak memory 200532 kb
Host smart-2e324e09-65a2-41c1-81fd-cdfd8b7fee23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307075613 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkm
gr_alert_test.307075613
Directory /workspace/32.clkmgr_alert_test/latest

Test location /workspace/coverage/default/1.clkmgr_idle_intersig_mubi.3709099038
Short name T281
Test name
Test status
Simulation time 52548104 ps
CPU time 0.92 seconds
Started Jul 24 07:07:57 PM PDT 24
Finished Jul 24 07:07:58 PM PDT 24
Peak memory 200472 kb
Host smart-07dcb48c-2b79-4343-a84a-c1022ff042a4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709099038 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_idle_intersig_mubi.3709099038
Directory /workspace/1.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.1839720459
Short name T66
Test name
Test status
Simulation time 158537837 ps
CPU time 3 seconds
Started Jul 24 07:02:34 PM PDT 24
Finished Jul 24 07:02:37 PM PDT 24
Peak memory 209364 kb
Host smart-25717c0e-21ee-4900-94f1-15e42ae5928e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839720459 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors_with_csr_rw.1839720459
Directory /workspace/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.832666911
Short name T95
Test name
Test status
Simulation time 436284773 ps
CPU time 3.68 seconds
Started Jul 24 07:03:01 PM PDT 24
Finished Jul 24 07:03:05 PM PDT 24
Peak memory 200916 kb
Host smart-c4d7a595-ff7f-4368-97b3-4f6fe80ff0d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832666911 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.clkmgr_tl_intg_err.832666911
Directory /workspace/8.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/15.clkmgr_stress_all_with_rand_reset.3999242729
Short name T12
Test name
Test status
Simulation time 33441564215 ps
CPU time 210.85 seconds
Started Jul 24 07:08:33 PM PDT 24
Finished Jul 24 07:12:04 PM PDT 24
Peak memory 209168 kb
Host smart-19b93f89-c80a-411f-99f3-fc2b526c0503
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3999242729 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all_with_rand_reset.3999242729
Directory /workspace/15.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.3445604382
Short name T108
Test name
Test status
Simulation time 330508782 ps
CPU time 2.25 seconds
Started Jul 24 07:03:01 PM PDT 24
Finished Jul 24 07:03:03 PM PDT 24
Peak memory 200892 kb
Host smart-9be7ff95-50d4-4748-a102-3458eabd8562
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445604382 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.clkmgr_tl_intg_err.3445604382
Directory /workspace/14.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.clkmgr_regwen.929185439
Short name T166
Test name
Test status
Simulation time 1346871115 ps
CPU time 4.47 seconds
Started Jul 24 07:08:36 PM PDT 24
Finished Jul 24 07:08:40 PM PDT 24
Peak memory 200628 kb
Host smart-a464af14-1ebb-45e7-b3c9-dbca0787ac0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929185439 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.929185439
Directory /workspace/16.clkmgr_regwen/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.1340845673
Short name T58
Test name
Test status
Simulation time 78676400 ps
CPU time 1.45 seconds
Started Jul 24 07:02:32 PM PDT 24
Finished Jul 24 07:02:34 PM PDT 24
Peak memory 201016 kb
Host smart-101fe08d-ced4-439e-8d5e-cdce1bf7600d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340845673 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 1.clkmgr_shadow_reg_errors.1340845673
Directory /workspace/1.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.1774547994
Short name T118
Test name
Test status
Simulation time 217201828 ps
CPU time 2.97 seconds
Started Jul 24 07:02:50 PM PDT 24
Finished Jul 24 07:02:54 PM PDT 24
Peak memory 201272 kb
Host smart-1af248ee-7b83-4d58-8fde-53bcc1785a71
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774547994 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors_with_csr_rw.1774547994
Directory /workspace/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.990911902
Short name T93
Test name
Test status
Simulation time 22077190 ps
CPU time 0.83 seconds
Started Jul 24 07:07:58 PM PDT 24
Finished Jul 24 07:07:59 PM PDT 24
Peak memory 200440 kb
Host smart-999d8c96-63eb-44b8-822d-6fc2c02777b8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990911902 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_clk_handshake_intersig_mubi.990911902
Directory /workspace/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.4245038900
Short name T128
Test name
Test status
Simulation time 180993022 ps
CPU time 1.66 seconds
Started Jul 24 07:02:28 PM PDT 24
Finished Jul 24 07:02:30 PM PDT 24
Peak memory 200992 kb
Host smart-eae43616-d586-4bd5-959f-9ac2a4848ad2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245038900 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 0.clkmgr_shadow_reg_errors.4245038900
Directory /workspace/0.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.3456857692
Short name T124
Test name
Test status
Simulation time 1168684780 ps
CPU time 4.48 seconds
Started Jul 24 07:03:01 PM PDT 24
Finished Jul 24 07:03:06 PM PDT 24
Peak memory 201080 kb
Host smart-544f3db2-76b5-421e-80b3-ba196b83f9d7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456857692 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 15.clkmgr_shadow_reg_errors.3456857692
Directory /workspace/15.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.352957018
Short name T104
Test name
Test status
Simulation time 261188859 ps
CPU time 2.81 seconds
Started Jul 24 07:03:10 PM PDT 24
Finished Jul 24 07:03:13 PM PDT 24
Peak memory 200924 kb
Host smart-4de15d51-3d98-4e05-8010-2baa60c09a37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352957018 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.clkmgr_tl_intg_err.352957018
Directory /workspace/19.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.2232793903
Short name T63
Test name
Test status
Simulation time 70988763 ps
CPU time 1.35 seconds
Started Jul 24 07:02:42 PM PDT 24
Finished Jul 24 07:02:44 PM PDT 24
Peak memory 200972 kb
Host smart-91aa8019-e7a2-43b2-a853-34ecbf3988b2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232793903 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 4.clkmgr_shadow_reg_errors.2232793903
Directory /workspace/4.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/18.clkmgr_stress_all_with_rand_reset.1906562867
Short name T816
Test name
Test status
Simulation time 124442479691 ps
CPU time 594.54 seconds
Started Jul 24 07:08:34 PM PDT 24
Finished Jul 24 07:18:29 PM PDT 24
Peak memory 217200 kb
Host smart-d335cc7b-19e7-4731-92f4-0f98b6fdc7db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1906562867 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all_with_rand_reset.1906562867
Directory /workspace/18.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.67131643
Short name T106
Test name
Test status
Simulation time 128913557 ps
CPU time 1.61 seconds
Started Jul 24 07:02:38 PM PDT 24
Finished Jul 24 07:02:40 PM PDT 24
Peak memory 200916 kb
Host smart-607121b3-686e-4cca-88bd-6ea23cc77d56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67131643 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.clkmgr_tl_intg_err.67131643
Directory /workspace/1.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.4121711193
Short name T99
Test name
Test status
Simulation time 121632638 ps
CPU time 2.49 seconds
Started Jul 24 07:02:56 PM PDT 24
Finished Jul 24 07:02:59 PM PDT 24
Peak memory 200852 kb
Host smart-8dd2e713-072b-4253-bbfb-774aa3f176a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121711193 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.clkmgr_tl_intg_err.4121711193
Directory /workspace/11.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.2787301869
Short name T97
Test name
Test status
Simulation time 69358893 ps
CPU time 1.64 seconds
Started Jul 24 07:02:55 PM PDT 24
Finished Jul 24 07:02:57 PM PDT 24
Peak memory 200896 kb
Host smart-927cece2-d78d-4e2d-9f6f-f59383ba890c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787301869 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.clkmgr_tl_intg_err.2787301869
Directory /workspace/12.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.4140341560
Short name T936
Test name
Test status
Simulation time 201538257 ps
CPU time 1.62 seconds
Started Jul 24 07:02:36 PM PDT 24
Finished Jul 24 07:02:38 PM PDT 24
Peak memory 200744 kb
Host smart-a3835975-17a2-4b82-9460-caec8753b0c6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140341560 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_aliasing.4140341560
Directory /workspace/0.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.4242661987
Short name T101
Test name
Test status
Simulation time 208280128 ps
CPU time 3.58 seconds
Started Jul 24 07:02:37 PM PDT 24
Finished Jul 24 07:02:41 PM PDT 24
Peak memory 200748 kb
Host smart-6e512cb4-da67-405a-88d2-724688045ed8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242661987 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_bit_bash.4242661987
Directory /workspace/0.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.1399867462
Short name T850
Test name
Test status
Simulation time 39473329 ps
CPU time 0.92 seconds
Started Jul 24 07:02:35 PM PDT 24
Finished Jul 24 07:02:36 PM PDT 24
Peak memory 200740 kb
Host smart-24fc500f-5b39-4696-b75d-3c58e1449ffc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399867462 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_hw_reset.1399867462
Directory /workspace/0.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.613549638
Short name T977
Test name
Test status
Simulation time 35397372 ps
CPU time 1.1 seconds
Started Jul 24 07:02:36 PM PDT 24
Finished Jul 24 07:02:37 PM PDT 24
Peak memory 200884 kb
Host smart-ac3c6cb0-bf8b-4c91-b187-714675460422
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613549638 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_mem_rw_with_rand_reset.613549638
Directory /workspace/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.1347580373
Short name T918
Test name
Test status
Simulation time 18201751 ps
CPU time 0.86 seconds
Started Jul 24 07:02:37 PM PDT 24
Finished Jul 24 07:02:38 PM PDT 24
Peak memory 200780 kb
Host smart-6056d000-19a6-4044-b16a-45a51b5b9c8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347580373 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
clkmgr_csr_rw.1347580373
Directory /workspace/0.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.4271103505
Short name T942
Test name
Test status
Simulation time 26303950 ps
CPU time 0.67 seconds
Started Jul 24 07:02:35 PM PDT 24
Finished Jul 24 07:02:36 PM PDT 24
Peak memory 199272 kb
Host smart-a523baca-77b0-4b54-9592-67101c8ff4e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271103505 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_intr_test.4271103505
Directory /workspace/0.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.4195645390
Short name T933
Test name
Test status
Simulation time 389688118 ps
CPU time 2.39 seconds
Started Jul 24 07:02:35 PM PDT 24
Finished Jul 24 07:02:37 PM PDT 24
Peak memory 200912 kb
Host smart-0be3e2d3-9dea-4ccd-97c8-efb8474360a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195645390 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.clkmgr_same_csr_outstanding.4195645390
Directory /workspace/0.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.826067967
Short name T119
Test name
Test status
Simulation time 253114174 ps
CPU time 2.97 seconds
Started Jul 24 07:02:29 PM PDT 24
Finished Jul 24 07:02:32 PM PDT 24
Peak memory 209416 kb
Host smart-59b3279e-eb61-4986-9097-cfe8586be301
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826067967 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors_with_csr_rw.826067967
Directory /workspace/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.1249496282
Short name T836
Test name
Test status
Simulation time 301109008 ps
CPU time 3.63 seconds
Started Jul 24 07:02:30 PM PDT 24
Finished Jul 24 07:02:34 PM PDT 24
Peak memory 200872 kb
Host smart-c65775ad-fa6d-463a-b1ae-7a68495cf0b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249496282 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_tl_errors.1249496282
Directory /workspace/0.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.3242920960
Short name T889
Test name
Test status
Simulation time 139921795 ps
CPU time 2.01 seconds
Started Jul 24 07:02:35 PM PDT 24
Finished Jul 24 07:02:38 PM PDT 24
Peak memory 200860 kb
Host smart-09c7e021-34fe-4fbb-abc5-7d32e4485b82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242920960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.clkmgr_tl_intg_err.3242920960
Directory /workspace/0.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.2414901551
Short name T947
Test name
Test status
Simulation time 66115397 ps
CPU time 1.72 seconds
Started Jul 24 07:02:36 PM PDT 24
Finished Jul 24 07:02:38 PM PDT 24
Peak memory 200764 kb
Host smart-bf241441-8d3a-45f5-b62e-e011b8392452
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414901551 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_aliasing.2414901551
Directory /workspace/1.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.98918886
Short name T154
Test name
Test status
Simulation time 277256232 ps
CPU time 4.55 seconds
Started Jul 24 07:02:36 PM PDT 24
Finished Jul 24 07:02:41 PM PDT 24
Peak memory 200952 kb
Host smart-80799b2d-8646-4404-a556-a340ff7d00b4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98918886 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.clkmgr_csr_bit_bash.98918886
Directory /workspace/1.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.2686260237
Short name T915
Test name
Test status
Simulation time 21307265 ps
CPU time 0.87 seconds
Started Jul 24 07:02:36 PM PDT 24
Finished Jul 24 07:02:37 PM PDT 24
Peak memory 200732 kb
Host smart-6a6d79e3-1c20-474a-a790-e3709354f28f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686260237 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_hw_reset.2686260237
Directory /workspace/1.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.3637145358
Short name T859
Test name
Test status
Simulation time 33537349 ps
CPU time 1.73 seconds
Started Jul 24 07:02:34 PM PDT 24
Finished Jul 24 07:02:36 PM PDT 24
Peak memory 200884 kb
Host smart-2136d2a3-5c95-4bea-a191-ded9891224cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637145358 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_mem_rw_with_rand_reset.3637145358
Directory /workspace/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.2768815104
Short name T878
Test name
Test status
Simulation time 31299581 ps
CPU time 0.86 seconds
Started Jul 24 07:02:37 PM PDT 24
Finished Jul 24 07:02:38 PM PDT 24
Peak memory 200720 kb
Host smart-0ec1e1bb-6b08-47bb-a300-d0a184d4a6c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768815104 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
clkmgr_csr_rw.2768815104
Directory /workspace/1.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.2180263736
Short name T838
Test name
Test status
Simulation time 28085688 ps
CPU time 0.75 seconds
Started Jul 24 07:02:38 PM PDT 24
Finished Jul 24 07:02:39 PM PDT 24
Peak memory 199280 kb
Host smart-19c8ce4a-227a-461e-9906-a77c66a81eb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180263736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_intr_test.2180263736
Directory /workspace/1.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.1416947976
Short name T858
Test name
Test status
Simulation time 185572808 ps
CPU time 1.81 seconds
Started Jul 24 07:02:40 PM PDT 24
Finished Jul 24 07:02:42 PM PDT 24
Peak memory 200856 kb
Host smart-ea9817c4-2bd1-405f-b6c7-f34000df28ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416947976 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.clkmgr_same_csr_outstanding.1416947976
Directory /workspace/1.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.4052276604
Short name T901
Test name
Test status
Simulation time 89211677 ps
CPU time 1.86 seconds
Started Jul 24 07:02:35 PM PDT 24
Finished Jul 24 07:02:37 PM PDT 24
Peak memory 209296 kb
Host smart-2ccbd583-fb72-4996-8f2c-340a794554d3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052276604 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors_with_csr_rw.4052276604
Directory /workspace/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.1515614008
Short name T962
Test name
Test status
Simulation time 94002926 ps
CPU time 2.77 seconds
Started Jul 24 07:02:34 PM PDT 24
Finished Jul 24 07:02:37 PM PDT 24
Peak memory 200884 kb
Host smart-67e8d069-3757-4844-8e62-02ae63d68f3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515614008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_tl_errors.1515614008
Directory /workspace/1.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.2438275009
Short name T832
Test name
Test status
Simulation time 16954186 ps
CPU time 0.93 seconds
Started Jul 24 07:02:56 PM PDT 24
Finished Jul 24 07:02:57 PM PDT 24
Peak memory 200832 kb
Host smart-63a0776e-dd31-4497-82a5-03ef60376377
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438275009 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_mem_rw_with_rand_reset.2438275009
Directory /workspace/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.3533149674
Short name T870
Test name
Test status
Simulation time 55325512 ps
CPU time 0.96 seconds
Started Jul 24 07:02:53 PM PDT 24
Finished Jul 24 07:02:54 PM PDT 24
Peak memory 200784 kb
Host smart-a6f6e6d5-60be-46a7-abd4-9da0a41e0f72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533149674 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.clkmgr_csr_rw.3533149674
Directory /workspace/10.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.2335808693
Short name T979
Test name
Test status
Simulation time 30286487 ps
CPU time 0.69 seconds
Started Jul 24 07:02:48 PM PDT 24
Finished Jul 24 07:02:49 PM PDT 24
Peak memory 199264 kb
Host smart-8d2b45a9-1dd8-47ff-b9f5-413ff37eac9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335808693 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl
kmgr_intr_test.2335808693
Directory /workspace/10.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.114851312
Short name T894
Test name
Test status
Simulation time 89365684 ps
CPU time 1.48 seconds
Started Jul 24 07:03:01 PM PDT 24
Finished Jul 24 07:03:03 PM PDT 24
Peak memory 200832 kb
Host smart-0e9624c4-b927-4f74-8935-d58bc8c70d50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114851312 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 10.clkmgr_same_csr_outstanding.114851312
Directory /workspace/10.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.3602618914
Short name T127
Test name
Test status
Simulation time 346742916 ps
CPU time 1.89 seconds
Started Jul 24 07:02:50 PM PDT 24
Finished Jul 24 07:02:52 PM PDT 24
Peak memory 200996 kb
Host smart-c0098ed9-250b-4d65-ad91-edebe6975a45
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602618914 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 10.clkmgr_shadow_reg_errors.3602618914
Directory /workspace/10.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.3848322808
Short name T928
Test name
Test status
Simulation time 251504419 ps
CPU time 2.2 seconds
Started Jul 24 07:02:49 PM PDT 24
Finished Jul 24 07:02:51 PM PDT 24
Peak memory 209356 kb
Host smart-25361db8-f0e3-4a2c-86b4-71afc910a032
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848322808 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors_with_csr_rw.3848322808
Directory /workspace/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.3133824753
Short name T914
Test name
Test status
Simulation time 171544521 ps
CPU time 2.97 seconds
Started Jul 24 07:02:47 PM PDT 24
Finished Jul 24 07:02:50 PM PDT 24
Peak memory 200856 kb
Host smart-af82bbf6-a9ed-4414-9bbe-ffa92f9627a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133824753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl
kmgr_tl_errors.3133824753
Directory /workspace/10.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.1364398551
Short name T917
Test name
Test status
Simulation time 127841732 ps
CPU time 1.74 seconds
Started Jul 24 07:02:51 PM PDT 24
Finished Jul 24 07:02:53 PM PDT 24
Peak memory 200944 kb
Host smart-42a314b5-89f6-4ab4-889d-0127468cb861
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364398551 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.clkmgr_tl_intg_err.1364398551
Directory /workspace/10.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.703411754
Short name T973
Test name
Test status
Simulation time 41187377 ps
CPU time 1.03 seconds
Started Jul 24 07:02:55 PM PDT 24
Finished Jul 24 07:02:56 PM PDT 24
Peak memory 200864 kb
Host smart-51c52d9b-021c-40a0-b018-9411e3a69079
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703411754 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_mem_rw_with_rand_reset.703411754
Directory /workspace/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.3080661676
Short name T888
Test name
Test status
Simulation time 39231966 ps
CPU time 0.85 seconds
Started Jul 24 07:02:54 PM PDT 24
Finished Jul 24 07:02:55 PM PDT 24
Peak memory 200740 kb
Host smart-eadd21f4-b702-472e-813e-04d255d72387
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080661676 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.clkmgr_csr_rw.3080661676
Directory /workspace/11.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.630556731
Short name T924
Test name
Test status
Simulation time 40967441 ps
CPU time 0.73 seconds
Started Jul 24 07:02:53 PM PDT 24
Finished Jul 24 07:02:54 PM PDT 24
Peak memory 199460 kb
Host smart-58c8a774-0507-4c12-82d5-d074f7017a7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630556731 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clk
mgr_intr_test.630556731
Directory /workspace/11.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.866799527
Short name T86
Test name
Test status
Simulation time 66122885 ps
CPU time 1.04 seconds
Started Jul 24 07:02:55 PM PDT 24
Finished Jul 24 07:02:56 PM PDT 24
Peak memory 200756 kb
Host smart-f7416e2f-f8e0-4e35-86b8-750739b6060c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866799527 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 11.clkmgr_same_csr_outstanding.866799527
Directory /workspace/11.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.3202500310
Short name T910
Test name
Test status
Simulation time 71464986 ps
CPU time 1.49 seconds
Started Jul 24 07:02:56 PM PDT 24
Finished Jul 24 07:02:58 PM PDT 24
Peak memory 201020 kb
Host smart-f20a9fdb-e912-40cd-a2e8-8a63d29fe553
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202500310 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 11.clkmgr_shadow_reg_errors.3202500310
Directory /workspace/11.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.3096941934
Short name T121
Test name
Test status
Simulation time 55805520 ps
CPU time 1.68 seconds
Started Jul 24 07:02:56 PM PDT 24
Finished Jul 24 07:02:57 PM PDT 24
Peak memory 217404 kb
Host smart-5614941b-b2a1-4c9a-ab58-d3ae57f6f5d5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096941934 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors_with_csr_rw.3096941934
Directory /workspace/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.2534519861
Short name T971
Test name
Test status
Simulation time 81092480 ps
CPU time 1.63 seconds
Started Jul 24 07:02:54 PM PDT 24
Finished Jul 24 07:02:56 PM PDT 24
Peak memory 200900 kb
Host smart-a4ad2d8f-497a-47e9-81b1-c9fbe6703b2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534519861 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_tl_errors.2534519861
Directory /workspace/11.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.1413081238
Short name T842
Test name
Test status
Simulation time 79365321 ps
CPU time 1.62 seconds
Started Jul 24 07:02:55 PM PDT 24
Finished Jul 24 07:02:57 PM PDT 24
Peak memory 200836 kb
Host smart-b781cc7b-c055-4475-9dda-584338b9e6ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413081238 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_mem_rw_with_rand_reset.1413081238
Directory /workspace/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.3258165216
Short name T852
Test name
Test status
Simulation time 15575629 ps
CPU time 0.78 seconds
Started Jul 24 07:02:55 PM PDT 24
Finished Jul 24 07:02:56 PM PDT 24
Peak memory 200672 kb
Host smart-c4392a43-f359-4595-b293-e44247fe9ddf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258165216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.clkmgr_csr_rw.3258165216
Directory /workspace/12.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.1601991162
Short name T900
Test name
Test status
Simulation time 62639938 ps
CPU time 0.78 seconds
Started Jul 24 07:02:56 PM PDT 24
Finished Jul 24 07:02:57 PM PDT 24
Peak memory 199300 kb
Host smart-0d4069e1-3e3b-40d6-963a-3bfea87ab4a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601991162 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl
kmgr_intr_test.1601991162
Directory /workspace/12.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.1474884621
Short name T919
Test name
Test status
Simulation time 102713195 ps
CPU time 1.1 seconds
Started Jul 24 07:02:53 PM PDT 24
Finished Jul 24 07:02:54 PM PDT 24
Peak memory 200732 kb
Host smart-2b28124c-424e-4ab5-ab93-d4c8b64b6a63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474884621 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 12.clkmgr_same_csr_outstanding.1474884621
Directory /workspace/12.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.2261877571
Short name T958
Test name
Test status
Simulation time 102866537 ps
CPU time 1.94 seconds
Started Jul 24 07:02:55 PM PDT 24
Finished Jul 24 07:02:58 PM PDT 24
Peak memory 209312 kb
Host smart-8360cf35-3a4c-4b57-98c8-379be4f5b145
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261877571 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 12.clkmgr_shadow_reg_errors.2261877571
Directory /workspace/12.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.3525385701
Short name T56
Test name
Test status
Simulation time 143371157 ps
CPU time 2.2 seconds
Started Jul 24 07:03:01 PM PDT 24
Finished Jul 24 07:03:03 PM PDT 24
Peak memory 217512 kb
Host smart-b3e748ca-1883-4813-8efe-392c97126cac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525385701 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors_with_csr_rw.3525385701
Directory /workspace/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.1772337660
Short name T967
Test name
Test status
Simulation time 120847398 ps
CPU time 2.17 seconds
Started Jul 24 07:03:01 PM PDT 24
Finished Jul 24 07:03:04 PM PDT 24
Peak memory 200872 kb
Host smart-a575e843-d036-41c8-8b88-b5c2d3a967b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772337660 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl
kmgr_tl_errors.1772337660
Directory /workspace/12.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.1103275080
Short name T961
Test name
Test status
Simulation time 32485936 ps
CPU time 1.11 seconds
Started Jul 24 07:02:59 PM PDT 24
Finished Jul 24 07:03:01 PM PDT 24
Peak memory 200848 kb
Host smart-3702902a-86e1-41d4-ae68-846234327c38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103275080 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_mem_rw_with_rand_reset.1103275080
Directory /workspace/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.1045677901
Short name T85
Test name
Test status
Simulation time 18259101 ps
CPU time 0.83 seconds
Started Jul 24 07:02:55 PM PDT 24
Finished Jul 24 07:02:56 PM PDT 24
Peak memory 200624 kb
Host smart-4d8295e5-f10c-41bc-b3cc-1b633ec95c9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045677901 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.clkmgr_csr_rw.1045677901
Directory /workspace/13.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.4188693106
Short name T879
Test name
Test status
Simulation time 26239913 ps
CPU time 0.7 seconds
Started Jul 24 07:02:54 PM PDT 24
Finished Jul 24 07:02:54 PM PDT 24
Peak memory 199320 kb
Host smart-287b549a-222a-4c49-9210-1a5cb8a61bca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188693106 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl
kmgr_intr_test.4188693106
Directory /workspace/13.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.3887257644
Short name T930
Test name
Test status
Simulation time 106326390 ps
CPU time 1.46 seconds
Started Jul 24 07:03:00 PM PDT 24
Finished Jul 24 07:03:02 PM PDT 24
Peak memory 200760 kb
Host smart-6c1c1373-265d-49e2-aacf-4b3f1414cc1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887257644 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 13.clkmgr_same_csr_outstanding.3887257644
Directory /workspace/13.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.1802559584
Short name T122
Test name
Test status
Simulation time 50122210 ps
CPU time 1.33 seconds
Started Jul 24 07:03:01 PM PDT 24
Finished Jul 24 07:03:02 PM PDT 24
Peak memory 200992 kb
Host smart-87c64805-3b08-433b-9de3-7a321d03e4ad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802559584 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 13.clkmgr_shadow_reg_errors.1802559584
Directory /workspace/13.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.1843962281
Short name T61
Test name
Test status
Simulation time 93387861 ps
CPU time 2.36 seconds
Started Jul 24 07:03:01 PM PDT 24
Finished Jul 24 07:03:04 PM PDT 24
Peak memory 201352 kb
Host smart-360aa565-eeaf-4679-8604-53d8e4016e6a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843962281 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors_with_csr_rw.1843962281
Directory /workspace/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.4247664496
Short name T856
Test name
Test status
Simulation time 31318026 ps
CPU time 1.83 seconds
Started Jul 24 07:02:55 PM PDT 24
Finished Jul 24 07:02:57 PM PDT 24
Peak memory 200876 kb
Host smart-4614bae2-9cc1-4072-af8a-4aed523462e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247664496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl
kmgr_tl_errors.4247664496
Directory /workspace/13.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.4006427580
Short name T163
Test name
Test status
Simulation time 115954054 ps
CPU time 1.64 seconds
Started Jul 24 07:02:54 PM PDT 24
Finished Jul 24 07:02:56 PM PDT 24
Peak memory 200864 kb
Host smart-0639e32e-81f1-491c-90d4-72ae1004278b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006427580 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.clkmgr_tl_intg_err.4006427580
Directory /workspace/13.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.2562729415
Short name T845
Test name
Test status
Simulation time 24572273 ps
CPU time 1 seconds
Started Jul 24 07:03:01 PM PDT 24
Finished Jul 24 07:03:03 PM PDT 24
Peak memory 200664 kb
Host smart-7733a3e5-04fc-4755-b26f-648c2befcfb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562729415 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_mem_rw_with_rand_reset.2562729415
Directory /workspace/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.1123282044
Short name T882
Test name
Test status
Simulation time 85191436 ps
CPU time 0.91 seconds
Started Jul 24 07:03:02 PM PDT 24
Finished Jul 24 07:03:04 PM PDT 24
Peak memory 200628 kb
Host smart-d3ce171c-434f-42d4-818e-1df382277ad3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123282044 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.clkmgr_csr_rw.1123282044
Directory /workspace/14.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.504678319
Short name T831
Test name
Test status
Simulation time 11294351 ps
CPU time 0.7 seconds
Started Jul 24 07:03:01 PM PDT 24
Finished Jul 24 07:03:02 PM PDT 24
Peak memory 199296 kb
Host smart-f7f3d5ba-8033-4b05-9e63-632f6a17d372
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504678319 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clk
mgr_intr_test.504678319
Directory /workspace/14.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.3316510138
Short name T864
Test name
Test status
Simulation time 56469929 ps
CPU time 1.37 seconds
Started Jul 24 07:03:00 PM PDT 24
Finished Jul 24 07:03:02 PM PDT 24
Peak memory 200928 kb
Host smart-231b5769-a16f-4db0-a4dd-5e19f290c423
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316510138 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 14.clkmgr_same_csr_outstanding.3316510138
Directory /workspace/14.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.1304669923
Short name T137
Test name
Test status
Simulation time 185995633 ps
CPU time 2.17 seconds
Started Jul 24 07:03:03 PM PDT 24
Finished Jul 24 07:03:05 PM PDT 24
Peak memory 217072 kb
Host smart-f297e037-9fdb-4b4e-af5c-7f623bfed2ef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304669923 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 14.clkmgr_shadow_reg_errors.1304669923
Directory /workspace/14.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.3908951372
Short name T134
Test name
Test status
Simulation time 151329158 ps
CPU time 2.1 seconds
Started Jul 24 07:03:03 PM PDT 24
Finished Jul 24 07:03:05 PM PDT 24
Peak memory 209296 kb
Host smart-23c39ef8-eee3-4198-81f5-066c605db0af
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908951372 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors_with_csr_rw.3908951372
Directory /workspace/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.1916382347
Short name T899
Test name
Test status
Simulation time 58072567 ps
CPU time 1.79 seconds
Started Jul 24 07:03:02 PM PDT 24
Finished Jul 24 07:03:04 PM PDT 24
Peak memory 200904 kb
Host smart-1a6e18db-5163-4917-b6f9-426f9849ab9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916382347 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl
kmgr_tl_errors.1916382347
Directory /workspace/14.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.4167447944
Short name T972
Test name
Test status
Simulation time 69654247 ps
CPU time 1.29 seconds
Started Jul 24 07:03:01 PM PDT 24
Finished Jul 24 07:03:03 PM PDT 24
Peak memory 200880 kb
Host smart-845b22b9-2b2d-469d-bbaf-3ca01b4a9416
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167447944 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_mem_rw_with_rand_reset.4167447944
Directory /workspace/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.426015335
Short name T953
Test name
Test status
Simulation time 22868630 ps
CPU time 0.78 seconds
Started Jul 24 07:03:01 PM PDT 24
Finished Jul 24 07:03:02 PM PDT 24
Peak memory 200664 kb
Host smart-b545352c-ca4c-4b36-a74f-4c160beb7e0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426015335 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
clkmgr_csr_rw.426015335
Directory /workspace/15.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.2415139897
Short name T853
Test name
Test status
Simulation time 166535807 ps
CPU time 1.04 seconds
Started Jul 24 07:03:01 PM PDT 24
Finished Jul 24 07:03:02 PM PDT 24
Peak memory 199352 kb
Host smart-23b0d98e-8f65-40de-8ca9-404bd71ffea6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415139897 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_intr_test.2415139897
Directory /workspace/15.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.4264326254
Short name T895
Test name
Test status
Simulation time 101178831 ps
CPU time 1.22 seconds
Started Jul 24 07:03:02 PM PDT 24
Finished Jul 24 07:03:04 PM PDT 24
Peak memory 200852 kb
Host smart-00bfdbd5-14d2-4ee0-a79f-c2e208c2d2d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264326254 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 15.clkmgr_same_csr_outstanding.4264326254
Directory /workspace/15.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.3476586408
Short name T117
Test name
Test status
Simulation time 155561743 ps
CPU time 1.99 seconds
Started Jul 24 07:03:01 PM PDT 24
Finished Jul 24 07:03:03 PM PDT 24
Peak memory 209332 kb
Host smart-e19e71b9-d46c-4cc8-94fa-1cb9a1bfb78c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476586408 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors_with_csr_rw.3476586408
Directory /workspace/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.1704873064
Short name T956
Test name
Test status
Simulation time 497924388 ps
CPU time 4.23 seconds
Started Jul 24 07:03:04 PM PDT 24
Finished Jul 24 07:03:08 PM PDT 24
Peak memory 200860 kb
Host smart-b7da4d79-acb3-4577-b897-94da4aab9164
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704873064 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_tl_errors.1704873064
Directory /workspace/15.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.3121082652
Short name T109
Test name
Test status
Simulation time 284546822 ps
CPU time 3.43 seconds
Started Jul 24 07:03:02 PM PDT 24
Finished Jul 24 07:03:05 PM PDT 24
Peak memory 200920 kb
Host smart-4b5c1a50-c612-4caa-b9be-000277c439d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121082652 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.clkmgr_tl_intg_err.3121082652
Directory /workspace/15.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.312856464
Short name T102
Test name
Test status
Simulation time 71817897 ps
CPU time 1.47 seconds
Started Jul 24 07:03:07 PM PDT 24
Finished Jul 24 07:03:09 PM PDT 24
Peak memory 200840 kb
Host smart-5df4d7fb-8bb1-4ace-bf8f-cfe91f8025fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312856464 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_mem_rw_with_rand_reset.312856464
Directory /workspace/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.1435001050
Short name T87
Test name
Test status
Simulation time 18629457 ps
CPU time 0.86 seconds
Started Jul 24 07:03:02 PM PDT 24
Finished Jul 24 07:03:03 PM PDT 24
Peak memory 200764 kb
Host smart-0641f6ff-f75a-4275-898f-1386f44607d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435001050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.clkmgr_csr_rw.1435001050
Directory /workspace/16.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.2464359437
Short name T946
Test name
Test status
Simulation time 15310218 ps
CPU time 0.69 seconds
Started Jul 24 07:03:07 PM PDT 24
Finished Jul 24 07:03:08 PM PDT 24
Peak memory 199296 kb
Host smart-1c631b3a-fb20-45b3-aee4-285d0a8a6c2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464359437 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_intr_test.2464359437
Directory /workspace/16.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.1761023579
Short name T922
Test name
Test status
Simulation time 42246873 ps
CPU time 1.04 seconds
Started Jul 24 07:03:08 PM PDT 24
Finished Jul 24 07:03:09 PM PDT 24
Peak memory 200756 kb
Host smart-25478a51-2088-4545-ae3a-2a33cc6ce3c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761023579 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 16.clkmgr_same_csr_outstanding.1761023579
Directory /workspace/16.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.3377484073
Short name T136
Test name
Test status
Simulation time 65265700 ps
CPU time 1.48 seconds
Started Jul 24 07:03:01 PM PDT 24
Finished Jul 24 07:03:02 PM PDT 24
Peak memory 201136 kb
Host smart-ed591e9b-5b83-4bc0-a709-153ab70ea0e0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377484073 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 16.clkmgr_shadow_reg_errors.3377484073
Directory /workspace/16.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.2611422268
Short name T62
Test name
Test status
Simulation time 96038366 ps
CPU time 2.54 seconds
Started Jul 24 07:03:01 PM PDT 24
Finished Jul 24 07:03:04 PM PDT 24
Peak memory 209360 kb
Host smart-e79258b2-de03-43f3-be9f-12b7ac76d796
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611422268 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors_with_csr_rw.2611422268
Directory /workspace/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.327174374
Short name T851
Test name
Test status
Simulation time 101888383 ps
CPU time 1.68 seconds
Started Jul 24 07:03:01 PM PDT 24
Finished Jul 24 07:03:04 PM PDT 24
Peak memory 200908 kb
Host smart-85491508-6450-41d1-abf2-d2c24d3a965a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327174374 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clk
mgr_tl_errors.327174374
Directory /workspace/16.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.3612713043
Short name T110
Test name
Test status
Simulation time 203217866 ps
CPU time 3.2 seconds
Started Jul 24 07:03:00 PM PDT 24
Finished Jul 24 07:03:04 PM PDT 24
Peak memory 200860 kb
Host smart-6550e9f2-6f00-4589-96e2-f1443176c8cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612713043 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.clkmgr_tl_intg_err.3612713043
Directory /workspace/16.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.3747593555
Short name T964
Test name
Test status
Simulation time 21070214 ps
CPU time 1.09 seconds
Started Jul 24 07:03:07 PM PDT 24
Finished Jul 24 07:03:08 PM PDT 24
Peak memory 200816 kb
Host smart-ddbf2a85-9a6c-49b4-9237-17da9f335d64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747593555 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_mem_rw_with_rand_reset.3747593555
Directory /workspace/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.874954385
Short name T912
Test name
Test status
Simulation time 41591210 ps
CPU time 0.88 seconds
Started Jul 24 07:03:09 PM PDT 24
Finished Jul 24 07:03:10 PM PDT 24
Peak memory 200780 kb
Host smart-4c304ab2-0a76-4c89-ab17-9831852d0695
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874954385 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
clkmgr_csr_rw.874954385
Directory /workspace/17.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.111448572
Short name T828
Test name
Test status
Simulation time 49365087 ps
CPU time 0.76 seconds
Started Jul 24 07:03:10 PM PDT 24
Finished Jul 24 07:03:11 PM PDT 24
Peak memory 199300 kb
Host smart-fcaddd12-078c-44d5-a12c-81efa620da6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111448572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clk
mgr_intr_test.111448572
Directory /workspace/17.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.2469703402
Short name T877
Test name
Test status
Simulation time 100275280 ps
CPU time 1.17 seconds
Started Jul 24 07:03:07 PM PDT 24
Finished Jul 24 07:03:09 PM PDT 24
Peak memory 200796 kb
Host smart-8d2aff90-b38d-44af-a99a-9b31e5f9565a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469703402 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 17.clkmgr_same_csr_outstanding.2469703402
Directory /workspace/17.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.2200684878
Short name T60
Test name
Test status
Simulation time 280725976 ps
CPU time 2.03 seconds
Started Jul 24 07:03:07 PM PDT 24
Finished Jul 24 07:03:09 PM PDT 24
Peak memory 201096 kb
Host smart-881a1ca9-b35f-4932-b24f-ea0e615f20f0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200684878 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 17.clkmgr_shadow_reg_errors.2200684878
Directory /workspace/17.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.673897038
Short name T64
Test name
Test status
Simulation time 224691771 ps
CPU time 2.11 seconds
Started Jul 24 07:03:07 PM PDT 24
Finished Jul 24 07:03:09 PM PDT 24
Peak memory 209208 kb
Host smart-a0d314b0-cf69-4d19-a11e-be185759ffab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673897038 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors_with_csr_rw.673897038
Directory /workspace/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.3008782825
Short name T849
Test name
Test status
Simulation time 83751066 ps
CPU time 2.41 seconds
Started Jul 24 07:03:06 PM PDT 24
Finished Jul 24 07:03:09 PM PDT 24
Peak memory 200900 kb
Host smart-a52c5748-3752-40db-80d3-6d4a3f268774
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008782825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_tl_errors.3008782825
Directory /workspace/17.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.1766567157
Short name T862
Test name
Test status
Simulation time 68931710 ps
CPU time 1.73 seconds
Started Jul 24 07:03:09 PM PDT 24
Finished Jul 24 07:03:11 PM PDT 24
Peak memory 200924 kb
Host smart-605a42bb-bbe2-45ac-b0bd-86b9de7881fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766567157 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.clkmgr_tl_intg_err.1766567157
Directory /workspace/17.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.3835298380
Short name T881
Test name
Test status
Simulation time 18941417 ps
CPU time 0.95 seconds
Started Jul 24 07:03:10 PM PDT 24
Finished Jul 24 07:03:11 PM PDT 24
Peak memory 200732 kb
Host smart-7f950e4e-269c-4d4e-8b16-2ae8dccc160b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835298380 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_mem_rw_with_rand_reset.3835298380
Directory /workspace/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.2565058474
Short name T84
Test name
Test status
Simulation time 19897424 ps
CPU time 0.74 seconds
Started Jul 24 07:03:06 PM PDT 24
Finished Jul 24 07:03:07 PM PDT 24
Peak memory 200756 kb
Host smart-fa5922e4-7a4d-4b90-a55c-ad2fe4be40ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565058474 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.clkmgr_csr_rw.2565058474
Directory /workspace/18.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.4100197517
Short name T965
Test name
Test status
Simulation time 12603050 ps
CPU time 0.73 seconds
Started Jul 24 07:03:08 PM PDT 24
Finished Jul 24 07:03:08 PM PDT 24
Peak memory 199292 kb
Host smart-9456483d-868a-4ebf-8e5d-ac7fa3a97390
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100197517 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl
kmgr_intr_test.4100197517
Directory /workspace/18.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.1904346791
Short name T949
Test name
Test status
Simulation time 89163972 ps
CPU time 1.15 seconds
Started Jul 24 07:03:07 PM PDT 24
Finished Jul 24 07:03:08 PM PDT 24
Peak memory 200796 kb
Host smart-1b41920b-02f0-4607-84ff-889e8765ebb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904346791 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 18.clkmgr_same_csr_outstanding.1904346791
Directory /workspace/18.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.3437794911
Short name T123
Test name
Test status
Simulation time 189533236 ps
CPU time 1.79 seconds
Started Jul 24 07:03:07 PM PDT 24
Finished Jul 24 07:03:09 PM PDT 24
Peak memory 201152 kb
Host smart-c0898a41-2d89-4736-b9ba-93548233f583
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437794911 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 18.clkmgr_shadow_reg_errors.3437794911
Directory /workspace/18.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.3934829986
Short name T130
Test name
Test status
Simulation time 472753158 ps
CPU time 3.76 seconds
Started Jul 24 07:03:08 PM PDT 24
Finished Jul 24 07:03:12 PM PDT 24
Peak memory 209484 kb
Host smart-0c03fa62-7d30-48d4-82a8-45687a0297c8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934829986 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors_with_csr_rw.3934829986
Directory /workspace/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.2296019823
Short name T841
Test name
Test status
Simulation time 138151569 ps
CPU time 3.7 seconds
Started Jul 24 07:03:09 PM PDT 24
Finished Jul 24 07:03:13 PM PDT 24
Peak memory 200840 kb
Host smart-755fa1b6-98ad-4231-8510-d818a1d1eb61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296019823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl
kmgr_tl_errors.2296019823
Directory /workspace/18.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.1157787293
Short name T103
Test name
Test status
Simulation time 143749712 ps
CPU time 1.77 seconds
Started Jul 24 07:03:08 PM PDT 24
Finished Jul 24 07:03:10 PM PDT 24
Peak memory 200880 kb
Host smart-270d95e0-d0f2-48bb-aaab-34c8f55be5c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157787293 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.clkmgr_tl_intg_err.1157787293
Directory /workspace/18.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.3830292532
Short name T834
Test name
Test status
Simulation time 27813267 ps
CPU time 1.18 seconds
Started Jul 24 07:03:17 PM PDT 24
Finished Jul 24 07:03:19 PM PDT 24
Peak memory 200852 kb
Host smart-446e3897-11f8-4d05-9867-71a5a0109e78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830292532 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_mem_rw_with_rand_reset.3830292532
Directory /workspace/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.3684415470
Short name T932
Test name
Test status
Simulation time 75572475 ps
CPU time 1.02 seconds
Started Jul 24 07:03:06 PM PDT 24
Finished Jul 24 07:03:07 PM PDT 24
Peak memory 200740 kb
Host smart-fccc990f-25c2-4b19-b94b-f01d9cd63426
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684415470 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.clkmgr_csr_rw.3684415470
Directory /workspace/19.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.2712601586
Short name T869
Test name
Test status
Simulation time 61843560 ps
CPU time 0.8 seconds
Started Jul 24 07:03:10 PM PDT 24
Finished Jul 24 07:03:11 PM PDT 24
Peak memory 199272 kb
Host smart-0262a3e1-91e3-4a96-9b74-d44d694960c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712601586 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl
kmgr_intr_test.2712601586
Directory /workspace/19.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.1585497534
Short name T885
Test name
Test status
Simulation time 39589441 ps
CPU time 1.02 seconds
Started Jul 24 07:03:15 PM PDT 24
Finished Jul 24 07:03:17 PM PDT 24
Peak memory 200724 kb
Host smart-eb818bf1-98b3-420c-9f64-ad24e10218bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585497534 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 19.clkmgr_same_csr_outstanding.1585497534
Directory /workspace/19.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.3698728319
Short name T129
Test name
Test status
Simulation time 69817271 ps
CPU time 1.37 seconds
Started Jul 24 07:03:14 PM PDT 24
Finished Jul 24 07:03:15 PM PDT 24
Peak memory 201060 kb
Host smart-65f299fa-aa65-419f-933d-c56993f8665e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698728319 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 19.clkmgr_shadow_reg_errors.3698728319
Directory /workspace/19.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.3873833377
Short name T970
Test name
Test status
Simulation time 62496270 ps
CPU time 1.83 seconds
Started Jul 24 07:03:08 PM PDT 24
Finished Jul 24 07:03:10 PM PDT 24
Peak memory 209372 kb
Host smart-13e3519e-8558-4d3a-be4c-c3ea366ee04e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873833377 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors_with_csr_rw.3873833377
Directory /workspace/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.2465056652
Short name T909
Test name
Test status
Simulation time 115355078 ps
CPU time 3.08 seconds
Started Jul 24 07:03:07 PM PDT 24
Finished Jul 24 07:03:10 PM PDT 24
Peak memory 200892 kb
Host smart-e7501836-34a8-465b-95c6-6373857bd74b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465056652 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl
kmgr_tl_errors.2465056652
Directory /workspace/19.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.1421716383
Short name T897
Test name
Test status
Simulation time 95507168 ps
CPU time 1.33 seconds
Started Jul 24 07:02:35 PM PDT 24
Finished Jul 24 07:02:37 PM PDT 24
Peak memory 200792 kb
Host smart-fc488132-9378-4928-a6f1-3db5911a2ac4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421716383 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_aliasing.1421716383
Directory /workspace/2.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.725699687
Short name T874
Test name
Test status
Simulation time 277242732 ps
CPU time 6.93 seconds
Started Jul 24 07:02:36 PM PDT 24
Finished Jul 24 07:02:43 PM PDT 24
Peak memory 200948 kb
Host smart-84eddeec-c736-4081-9756-55bd4b1e6507
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725699687 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_csr_bit_bash.725699687
Directory /workspace/2.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.4085985443
Short name T837
Test name
Test status
Simulation time 18072901 ps
CPU time 0.81 seconds
Started Jul 24 07:02:40 PM PDT 24
Finished Jul 24 07:02:41 PM PDT 24
Peak memory 200744 kb
Host smart-d3109d30-c3ce-46dc-ad17-9a8d002f21bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085985443 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_hw_reset.4085985443
Directory /workspace/2.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.2668153245
Short name T907
Test name
Test status
Simulation time 41552291 ps
CPU time 1 seconds
Started Jul 24 07:02:35 PM PDT 24
Finished Jul 24 07:02:37 PM PDT 24
Peak memory 200912 kb
Host smart-8e83b1c5-a090-429a-9ed7-af2ebd7ebf95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668153245 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_mem_rw_with_rand_reset.2668153245
Directory /workspace/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.3189852412
Short name T940
Test name
Test status
Simulation time 29607298 ps
CPU time 0.83 seconds
Started Jul 24 07:03:09 PM PDT 24
Finished Jul 24 07:03:10 PM PDT 24
Peak memory 200716 kb
Host smart-eb1f779f-3654-4722-9313-28cdf64903aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189852412 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
clkmgr_csr_rw.3189852412
Directory /workspace/2.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.800009356
Short name T921
Test name
Test status
Simulation time 11618022 ps
CPU time 0.65 seconds
Started Jul 24 07:02:38 PM PDT 24
Finished Jul 24 07:02:39 PM PDT 24
Peak memory 199344 kb
Host smart-15438a4f-a578-4d73-a35d-3ab83c25c3ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800009356 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkm
gr_intr_test.800009356
Directory /workspace/2.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.3156905199
Short name T898
Test name
Test status
Simulation time 35165683 ps
CPU time 1.29 seconds
Started Jul 24 07:02:36 PM PDT 24
Finished Jul 24 07:02:37 PM PDT 24
Peak memory 200928 kb
Host smart-6dbe3eff-344a-4041-bbbd-d9fb04a2e63b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156905199 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.clkmgr_same_csr_outstanding.3156905199
Directory /workspace/2.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.2075036017
Short name T57
Test name
Test status
Simulation time 86745113 ps
CPU time 1.7 seconds
Started Jul 24 07:02:37 PM PDT 24
Finished Jul 24 07:02:39 PM PDT 24
Peak memory 201120 kb
Host smart-d2f0bb9e-1105-4edc-b2c6-9eab3ae706ad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075036017 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 2.clkmgr_shadow_reg_errors.2075036017
Directory /workspace/2.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.3118309997
Short name T934
Test name
Test status
Simulation time 95388668 ps
CPU time 2.41 seconds
Started Jul 24 07:02:40 PM PDT 24
Finished Jul 24 07:02:43 PM PDT 24
Peak memory 209300 kb
Host smart-02c6952c-de89-460f-a4bb-4c24e1a27f73
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118309997 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors_with_csr_rw.3118309997
Directory /workspace/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.1812933056
Short name T957
Test name
Test status
Simulation time 770680483 ps
CPU time 4.76 seconds
Started Jul 24 07:02:36 PM PDT 24
Finished Jul 24 07:02:41 PM PDT 24
Peak memory 200776 kb
Host smart-31f411ce-4424-4878-83dc-42c721749fbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812933056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk
mgr_tl_errors.1812933056
Directory /workspace/2.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.3143814884
Short name T902
Test name
Test status
Simulation time 103329939 ps
CPU time 2.44 seconds
Started Jul 24 07:02:36 PM PDT 24
Finished Jul 24 07:02:38 PM PDT 24
Peak memory 200928 kb
Host smart-cada826f-45c6-4fc9-a623-f1230665a1e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143814884 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.clkmgr_tl_intg_err.3143814884
Directory /workspace/2.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.2416108853
Short name T865
Test name
Test status
Simulation time 10780127 ps
CPU time 0.68 seconds
Started Jul 24 07:03:16 PM PDT 24
Finished Jul 24 07:03:17 PM PDT 24
Peak memory 199376 kb
Host smart-bfca32f2-7200-42c6-b209-233631ce4061
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416108853 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.cl
kmgr_intr_test.2416108853
Directory /workspace/20.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.980494723
Short name T978
Test name
Test status
Simulation time 20939250 ps
CPU time 0.7 seconds
Started Jul 24 07:03:17 PM PDT 24
Finished Jul 24 07:03:18 PM PDT 24
Peak memory 199296 kb
Host smart-9b05e9c7-82d0-4ba0-a9e5-28d383f2a9e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980494723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.clk
mgr_intr_test.980494723
Directory /workspace/21.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.1767975962
Short name T844
Test name
Test status
Simulation time 26670946 ps
CPU time 0.73 seconds
Started Jul 24 07:03:18 PM PDT 24
Finished Jul 24 07:03:19 PM PDT 24
Peak memory 199272 kb
Host smart-816d9aac-c8e8-4b69-bc7b-fbd07bff5316
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767975962 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.cl
kmgr_intr_test.1767975962
Directory /workspace/22.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.3139905579
Short name T959
Test name
Test status
Simulation time 31088949 ps
CPU time 0.72 seconds
Started Jul 24 07:03:17 PM PDT 24
Finished Jul 24 07:03:18 PM PDT 24
Peak memory 199312 kb
Host smart-6b9e8099-736b-427a-980d-f0cba68adf24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139905579 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.cl
kmgr_intr_test.3139905579
Directory /workspace/23.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.1256391403
Short name T904
Test name
Test status
Simulation time 41811173 ps
CPU time 0.74 seconds
Started Jul 24 07:03:18 PM PDT 24
Finished Jul 24 07:03:19 PM PDT 24
Peak memory 199332 kb
Host smart-78486685-1795-4ad1-b489-73acee665881
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256391403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.cl
kmgr_intr_test.1256391403
Directory /workspace/24.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.3883423073
Short name T937
Test name
Test status
Simulation time 15217006 ps
CPU time 0.67 seconds
Started Jul 24 07:03:16 PM PDT 24
Finished Jul 24 07:03:17 PM PDT 24
Peak memory 199344 kb
Host smart-2f9f5e10-bc5c-4fd6-9829-0d0c06c32df9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883423073 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.cl
kmgr_intr_test.3883423073
Directory /workspace/25.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.1118899841
Short name T931
Test name
Test status
Simulation time 36881159 ps
CPU time 0.73 seconds
Started Jul 24 07:03:16 PM PDT 24
Finished Jul 24 07:03:17 PM PDT 24
Peak memory 199332 kb
Host smart-b0e9bef6-ea44-4a63-9a61-c74a0112f3e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118899841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.cl
kmgr_intr_test.1118899841
Directory /workspace/26.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.3619759666
Short name T875
Test name
Test status
Simulation time 13922293 ps
CPU time 0.69 seconds
Started Jul 24 07:03:17 PM PDT 24
Finished Jul 24 07:03:18 PM PDT 24
Peak memory 199164 kb
Host smart-575201bc-a08a-4715-a647-0f966658594b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619759666 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.cl
kmgr_intr_test.3619759666
Directory /workspace/27.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.3040447479
Short name T840
Test name
Test status
Simulation time 53998021 ps
CPU time 0.76 seconds
Started Jul 24 07:03:17 PM PDT 24
Finished Jul 24 07:03:17 PM PDT 24
Peak memory 199268 kb
Host smart-a203f2e1-2ecf-48c0-be6a-49da9284d316
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040447479 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.cl
kmgr_intr_test.3040447479
Directory /workspace/28.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.260074683
Short name T926
Test name
Test status
Simulation time 19156253 ps
CPU time 0.66 seconds
Started Jul 24 07:03:17 PM PDT 24
Finished Jul 24 07:03:18 PM PDT 24
Peak memory 199244 kb
Host smart-6c620949-cdc7-4bca-bdb9-c1ebce35fce7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260074683 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.clk
mgr_intr_test.260074683
Directory /workspace/29.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.3300623297
Short name T939
Test name
Test status
Simulation time 35786382 ps
CPU time 1.21 seconds
Started Jul 24 07:02:34 PM PDT 24
Finished Jul 24 07:02:35 PM PDT 24
Peak memory 200716 kb
Host smart-30e248aa-62a5-4515-a776-368dc128d49b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300623297 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_aliasing.3300623297
Directory /workspace/3.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.1185508726
Short name T871
Test name
Test status
Simulation time 3659153188 ps
CPU time 16.95 seconds
Started Jul 24 07:02:35 PM PDT 24
Finished Jul 24 07:02:52 PM PDT 24
Peak memory 200948 kb
Host smart-752c528b-42e7-41e2-9495-e8f3a2f393dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185508726 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_bit_bash.1185508726
Directory /workspace/3.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.204866086
Short name T854
Test name
Test status
Simulation time 47093198 ps
CPU time 0.81 seconds
Started Jul 24 07:02:34 PM PDT 24
Finished Jul 24 07:02:35 PM PDT 24
Peak memory 200588 kb
Host smart-b215d3b7-6d6e-412d-91d4-f65548daaa08
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204866086 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_csr_hw_reset.204866086
Directory /workspace/3.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.2688031459
Short name T923
Test name
Test status
Simulation time 27701561 ps
CPU time 1.17 seconds
Started Jul 24 07:02:42 PM PDT 24
Finished Jul 24 07:02:44 PM PDT 24
Peak memory 200848 kb
Host smart-af5fa25a-ec94-4c56-8374-8e3e6dcdd196
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688031459 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_mem_rw_with_rand_reset.2688031459
Directory /workspace/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.4014963469
Short name T861
Test name
Test status
Simulation time 38328563 ps
CPU time 0.78 seconds
Started Jul 24 07:02:35 PM PDT 24
Finished Jul 24 07:02:36 PM PDT 24
Peak memory 200568 kb
Host smart-6b73be0c-0403-4d93-bac6-06f4c26ae0b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014963469 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
clkmgr_csr_rw.4014963469
Directory /workspace/3.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.931694615
Short name T880
Test name
Test status
Simulation time 13228543 ps
CPU time 0.67 seconds
Started Jul 24 07:02:34 PM PDT 24
Finished Jul 24 07:02:35 PM PDT 24
Peak memory 199296 kb
Host smart-006c4014-509d-4f4a-8c69-8f278311b4c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931694615 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkm
gr_intr_test.931694615
Directory /workspace/3.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.927083602
Short name T868
Test name
Test status
Simulation time 46356984 ps
CPU time 1.28 seconds
Started Jul 24 07:02:34 PM PDT 24
Finished Jul 24 07:02:35 PM PDT 24
Peak memory 200860 kb
Host smart-0eb36968-4c50-49c6-bf0e-9331174b0f28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927083602 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.clkmgr_same_csr_outstanding.927083602
Directory /workspace/3.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.2037547595
Short name T135
Test name
Test status
Simulation time 155675128 ps
CPU time 2.04 seconds
Started Jul 24 07:02:38 PM PDT 24
Finished Jul 24 07:02:40 PM PDT 24
Peak memory 201112 kb
Host smart-91a3630f-dd4b-484c-9d93-6ffcbcc2de84
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037547595 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 3.clkmgr_shadow_reg_errors.2037547595
Directory /workspace/3.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.1394373531
Short name T843
Test name
Test status
Simulation time 73077276 ps
CPU time 2.16 seconds
Started Jul 24 07:02:37 PM PDT 24
Finished Jul 24 07:02:39 PM PDT 24
Peak memory 200904 kb
Host smart-c33e13ee-aadc-40a5-b565-d2228b10059c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394373531 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk
mgr_tl_errors.1394373531
Directory /workspace/3.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.444179597
Short name T960
Test name
Test status
Simulation time 57867273 ps
CPU time 1.64 seconds
Started Jul 24 07:02:36 PM PDT 24
Finished Jul 24 07:02:37 PM PDT 24
Peak memory 200928 kb
Host smart-3218f570-51b2-49c1-94af-bc38833a879f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444179597 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.clkmgr_tl_intg_err.444179597
Directory /workspace/3.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.2242533475
Short name T848
Test name
Test status
Simulation time 30983993 ps
CPU time 0.72 seconds
Started Jul 24 07:03:16 PM PDT 24
Finished Jul 24 07:03:17 PM PDT 24
Peak memory 199292 kb
Host smart-2204dcae-4060-4cd4-949c-9f0415b15e60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242533475 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.cl
kmgr_intr_test.2242533475
Directory /workspace/30.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.199023118
Short name T954
Test name
Test status
Simulation time 11057069 ps
CPU time 0.68 seconds
Started Jul 24 07:03:14 PM PDT 24
Finished Jul 24 07:03:15 PM PDT 24
Peak memory 199256 kb
Host smart-9c173ce3-8555-41ab-b7b8-22d0197ac486
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199023118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.clk
mgr_intr_test.199023118
Directory /workspace/31.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.1124141067
Short name T968
Test name
Test status
Simulation time 31752356 ps
CPU time 0.72 seconds
Started Jul 24 07:03:17 PM PDT 24
Finished Jul 24 07:03:18 PM PDT 24
Peak memory 199532 kb
Host smart-cb1deb25-426f-43e7-b034-f6d4ab8a14e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124141067 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.cl
kmgr_intr_test.1124141067
Directory /workspace/32.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.3151474762
Short name T867
Test name
Test status
Simulation time 144830323 ps
CPU time 0.99 seconds
Started Jul 24 07:03:17 PM PDT 24
Finished Jul 24 07:03:18 PM PDT 24
Peak memory 199308 kb
Host smart-d8070956-5059-4f1a-b5f9-614edbb0d093
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151474762 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.cl
kmgr_intr_test.3151474762
Directory /workspace/33.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.2998305580
Short name T847
Test name
Test status
Simulation time 34307214 ps
CPU time 0.72 seconds
Started Jul 24 07:03:16 PM PDT 24
Finished Jul 24 07:03:17 PM PDT 24
Peak memory 199280 kb
Host smart-f326a435-f967-48d2-883c-fbf99f604fdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998305580 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.cl
kmgr_intr_test.2998305580
Directory /workspace/34.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.3028369905
Short name T920
Test name
Test status
Simulation time 21096615 ps
CPU time 0.66 seconds
Started Jul 24 07:03:17 PM PDT 24
Finished Jul 24 07:03:18 PM PDT 24
Peak memory 199312 kb
Host smart-50f41119-1dde-4126-829f-034b97a800f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028369905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.cl
kmgr_intr_test.3028369905
Directory /workspace/35.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.887173295
Short name T892
Test name
Test status
Simulation time 11566479 ps
CPU time 0.67 seconds
Started Jul 24 07:03:15 PM PDT 24
Finished Jul 24 07:03:15 PM PDT 24
Peak memory 199280 kb
Host smart-3f0640dd-a19c-46c3-b394-247d7b001e8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887173295 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.clk
mgr_intr_test.887173295
Directory /workspace/36.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.1422000599
Short name T839
Test name
Test status
Simulation time 22194888 ps
CPU time 0.67 seconds
Started Jul 24 07:03:17 PM PDT 24
Finished Jul 24 07:03:18 PM PDT 24
Peak memory 199292 kb
Host smart-47fd37ec-6b1a-4d17-801f-3d360553f596
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422000599 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.cl
kmgr_intr_test.1422000599
Directory /workspace/37.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.2399711105
Short name T950
Test name
Test status
Simulation time 12284576 ps
CPU time 0.67 seconds
Started Jul 24 07:03:18 PM PDT 24
Finished Jul 24 07:03:19 PM PDT 24
Peak memory 199268 kb
Host smart-117d87ca-6c8f-4198-9d34-269159ec76cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399711105 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.cl
kmgr_intr_test.2399711105
Directory /workspace/38.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.1779368842
Short name T945
Test name
Test status
Simulation time 20028923 ps
CPU time 0.71 seconds
Started Jul 24 07:03:17 PM PDT 24
Finished Jul 24 07:03:18 PM PDT 24
Peak memory 199372 kb
Host smart-dc920efb-48df-4e7c-bb15-1b6678459f5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779368842 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.cl
kmgr_intr_test.1779368842
Directory /workspace/39.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.3530877458
Short name T860
Test name
Test status
Simulation time 21957337 ps
CPU time 1.12 seconds
Started Jul 24 07:02:42 PM PDT 24
Finished Jul 24 07:02:44 PM PDT 24
Peak memory 200700 kb
Host smart-2c848216-0070-4c6b-8d6c-e1eb05b6544b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530877458 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_aliasing.3530877458
Directory /workspace/4.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.437209460
Short name T855
Test name
Test status
Simulation time 1347818487 ps
CPU time 9.02 seconds
Started Jul 24 07:02:55 PM PDT 24
Finished Jul 24 07:03:04 PM PDT 24
Peak memory 200848 kb
Host smart-d90eb209-c93e-44d4-a6e8-76bc2616e475
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437209460 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_csr_bit_bash.437209460
Directory /workspace/4.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.1208248687
Short name T830
Test name
Test status
Simulation time 17395071 ps
CPU time 0.84 seconds
Started Jul 24 07:02:44 PM PDT 24
Finished Jul 24 07:02:45 PM PDT 24
Peak memory 200760 kb
Host smart-62b5ca30-4d8a-44de-be2a-8449de4a8772
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208248687 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_hw_reset.1208248687
Directory /workspace/4.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.1779679694
Short name T916
Test name
Test status
Simulation time 151030377 ps
CPU time 1.56 seconds
Started Jul 24 07:02:44 PM PDT 24
Finished Jul 24 07:02:45 PM PDT 24
Peak memory 200924 kb
Host smart-2e2adabf-4a0a-443b-8102-ecad1e4e0070
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779679694 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_mem_rw_with_rand_reset.1779679694
Directory /workspace/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.4175470624
Short name T935
Test name
Test status
Simulation time 16016659 ps
CPU time 0.77 seconds
Started Jul 24 07:02:42 PM PDT 24
Finished Jul 24 07:02:43 PM PDT 24
Peak memory 200676 kb
Host smart-6cc7184c-69ef-4f9b-86ce-2d39d9568123
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175470624 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
clkmgr_csr_rw.4175470624
Directory /workspace/4.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.2877117780
Short name T903
Test name
Test status
Simulation time 20559620 ps
CPU time 0.69 seconds
Started Jul 24 07:02:50 PM PDT 24
Finished Jul 24 07:02:51 PM PDT 24
Peak memory 199304 kb
Host smart-d3a39993-09f8-4702-8641-c6b17a9b602e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877117780 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_intr_test.2877117780
Directory /workspace/4.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.886915999
Short name T975
Test name
Test status
Simulation time 67508822 ps
CPU time 1.13 seconds
Started Jul 24 07:02:43 PM PDT 24
Finished Jul 24 07:02:44 PM PDT 24
Peak memory 200796 kb
Host smart-e8e2d3db-3578-44ab-adda-78df134ca321
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886915999 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.clkmgr_same_csr_outstanding.886915999
Directory /workspace/4.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.921382121
Short name T120
Test name
Test status
Simulation time 167151973 ps
CPU time 2.58 seconds
Started Jul 24 07:02:42 PM PDT 24
Finished Jul 24 07:02:45 PM PDT 24
Peak memory 201332 kb
Host smart-ee852a83-fcb7-46d9-b764-46110c61310f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921382121 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors_with_csr_rw.921382121
Directory /workspace/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.3201384192
Short name T873
Test name
Test status
Simulation time 46308807 ps
CPU time 1.62 seconds
Started Jul 24 07:02:54 PM PDT 24
Finished Jul 24 07:02:56 PM PDT 24
Peak memory 200840 kb
Host smart-6070a8f2-4948-4a30-a803-b0a25bfb115f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201384192 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_tl_errors.3201384192
Directory /workspace/4.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.1724609006
Short name T107
Test name
Test status
Simulation time 322759024 ps
CPU time 2.1 seconds
Started Jul 24 07:02:40 PM PDT 24
Finished Jul 24 07:02:42 PM PDT 24
Peak memory 200860 kb
Host smart-63047521-56ec-457e-bc3d-102e239c9176
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724609006 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.clkmgr_tl_intg_err.1724609006
Directory /workspace/4.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.2284380874
Short name T884
Test name
Test status
Simulation time 13578122 ps
CPU time 0.71 seconds
Started Jul 24 07:03:16 PM PDT 24
Finished Jul 24 07:03:17 PM PDT 24
Peak memory 199264 kb
Host smart-2c9de24b-1954-4130-a964-98c1871d9196
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284380874 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.cl
kmgr_intr_test.2284380874
Directory /workspace/40.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.354043549
Short name T911
Test name
Test status
Simulation time 32784103 ps
CPU time 0.7 seconds
Started Jul 24 07:03:18 PM PDT 24
Finished Jul 24 07:03:19 PM PDT 24
Peak memory 199280 kb
Host smart-efd7a64f-461e-474e-b68c-ba4733822e18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354043549 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.clk
mgr_intr_test.354043549
Directory /workspace/41.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.188981618
Short name T927
Test name
Test status
Simulation time 20033288 ps
CPU time 0.71 seconds
Started Jul 24 07:03:17 PM PDT 24
Finished Jul 24 07:03:18 PM PDT 24
Peak memory 199272 kb
Host smart-5f09c1d4-dc8d-4940-89ad-e283fd1208f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188981618 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.clk
mgr_intr_test.188981618
Directory /workspace/42.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.270579798
Short name T883
Test name
Test status
Simulation time 45986429 ps
CPU time 0.77 seconds
Started Jul 24 07:03:17 PM PDT 24
Finished Jul 24 07:03:18 PM PDT 24
Peak memory 199284 kb
Host smart-b25dec29-4f17-49f6-b526-d203c906a482
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270579798 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.clk
mgr_intr_test.270579798
Directory /workspace/43.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.3076132889
Short name T925
Test name
Test status
Simulation time 24879610 ps
CPU time 0.68 seconds
Started Jul 24 07:03:15 PM PDT 24
Finished Jul 24 07:03:16 PM PDT 24
Peak memory 199320 kb
Host smart-84a7d0b5-6385-4dbd-86dd-ea395f4f2fd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076132889 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.cl
kmgr_intr_test.3076132889
Directory /workspace/44.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.1873698436
Short name T896
Test name
Test status
Simulation time 13899113 ps
CPU time 0.65 seconds
Started Jul 24 07:03:16 PM PDT 24
Finished Jul 24 07:03:17 PM PDT 24
Peak memory 199296 kb
Host smart-b9229e80-0045-4ae4-8a17-b7f6519166f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873698436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.cl
kmgr_intr_test.1873698436
Directory /workspace/45.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.1671013173
Short name T948
Test name
Test status
Simulation time 32133143 ps
CPU time 0.72 seconds
Started Jul 24 07:03:14 PM PDT 24
Finished Jul 24 07:03:15 PM PDT 24
Peak memory 199272 kb
Host smart-16331d05-67c7-4568-b2cf-bb7178a005d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671013173 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.cl
kmgr_intr_test.1671013173
Directory /workspace/46.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.1709494306
Short name T887
Test name
Test status
Simulation time 20086279 ps
CPU time 0.67 seconds
Started Jul 24 07:04:59 PM PDT 24
Finished Jul 24 07:04:59 PM PDT 24
Peak memory 199248 kb
Host smart-dfe94ab0-bc9d-47fb-a0a4-ee4d93f86d22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709494306 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.cl
kmgr_intr_test.1709494306
Directory /workspace/47.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.1053900224
Short name T833
Test name
Test status
Simulation time 22241041 ps
CPU time 0.67 seconds
Started Jul 24 07:03:15 PM PDT 24
Finished Jul 24 07:03:16 PM PDT 24
Peak memory 199144 kb
Host smart-523a9c8c-1076-49a0-bb6a-6b322fc062a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053900224 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.cl
kmgr_intr_test.1053900224
Directory /workspace/48.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.565150863
Short name T835
Test name
Test status
Simulation time 41175032 ps
CPU time 0.73 seconds
Started Jul 24 07:03:26 PM PDT 24
Finished Jul 24 07:03:27 PM PDT 24
Peak memory 199272 kb
Host smart-da5ee5d4-da2b-4e94-b136-c4f82a62428b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565150863 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.clk
mgr_intr_test.565150863
Directory /workspace/49.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.2352961149
Short name T951
Test name
Test status
Simulation time 57222741 ps
CPU time 1.17 seconds
Started Jul 24 07:02:43 PM PDT 24
Finished Jul 24 07:02:45 PM PDT 24
Peak memory 200792 kb
Host smart-3ce54e32-6644-48f9-824a-92144da453ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352961149 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_mem_rw_with_rand_reset.2352961149
Directory /workspace/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.2317882422
Short name T905
Test name
Test status
Simulation time 17491166 ps
CPU time 0.8 seconds
Started Jul 24 07:02:44 PM PDT 24
Finished Jul 24 07:02:45 PM PDT 24
Peak memory 200744 kb
Host smart-8ca41c88-d303-484f-937c-cb4ee6bb43bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317882422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
clkmgr_csr_rw.2317882422
Directory /workspace/5.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.2555818785
Short name T829
Test name
Test status
Simulation time 18593979 ps
CPU time 0.68 seconds
Started Jul 24 07:02:45 PM PDT 24
Finished Jul 24 07:02:46 PM PDT 24
Peak memory 199280 kb
Host smart-7b31ac37-963d-4678-9a69-b549d2545fdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555818785 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk
mgr_intr_test.2555818785
Directory /workspace/5.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.3319087474
Short name T952
Test name
Test status
Simulation time 156895914 ps
CPU time 1.57 seconds
Started Jul 24 07:02:42 PM PDT 24
Finished Jul 24 07:02:43 PM PDT 24
Peak memory 200780 kb
Host smart-66fccd2b-7597-4aec-951f-0d56426599eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319087474 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.clkmgr_same_csr_outstanding.3319087474
Directory /workspace/5.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.2062871577
Short name T938
Test name
Test status
Simulation time 756841061 ps
CPU time 3.48 seconds
Started Jul 24 07:02:44 PM PDT 24
Finished Jul 24 07:02:48 PM PDT 24
Peak memory 209296 kb
Host smart-8cdab96b-d886-4ecc-b2b9-2849a4062528
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062871577 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 5.clkmgr_shadow_reg_errors.2062871577
Directory /workspace/5.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.1251355203
Short name T126
Test name
Test status
Simulation time 217258671 ps
CPU time 2.96 seconds
Started Jul 24 07:02:42 PM PDT 24
Finished Jul 24 07:02:45 PM PDT 24
Peak memory 201444 kb
Host smart-ec4c74b0-4cc8-42d8-9e5e-a5dfed6def89
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251355203 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors_with_csr_rw.1251355203
Directory /workspace/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.2970509678
Short name T863
Test name
Test status
Simulation time 244114654 ps
CPU time 2.58 seconds
Started Jul 24 07:02:43 PM PDT 24
Finished Jul 24 07:02:46 PM PDT 24
Peak memory 200856 kb
Host smart-e5ca92e7-6ee9-4492-983a-0d8a6c6dcead
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970509678 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk
mgr_tl_errors.2970509678
Directory /workspace/5.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.2717648337
Short name T100
Test name
Test status
Simulation time 123990742 ps
CPU time 2.65 seconds
Started Jul 24 07:02:42 PM PDT 24
Finished Jul 24 07:02:46 PM PDT 24
Peak memory 200936 kb
Host smart-a2618f08-4543-42a4-834b-6ff9af1d2a6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717648337 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.clkmgr_tl_intg_err.2717648337
Directory /workspace/5.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.1134943024
Short name T966
Test name
Test status
Simulation time 32683391 ps
CPU time 0.9 seconds
Started Jul 24 07:02:50 PM PDT 24
Finished Jul 24 07:02:52 PM PDT 24
Peak memory 200768 kb
Host smart-3954e423-8fef-4f5a-8ad4-c34fee87b0bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134943024 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_mem_rw_with_rand_reset.1134943024
Directory /workspace/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.644049371
Short name T893
Test name
Test status
Simulation time 33419595 ps
CPU time 0.89 seconds
Started Jul 24 07:02:42 PM PDT 24
Finished Jul 24 07:02:44 PM PDT 24
Peak memory 200692 kb
Host smart-c9ecc7aa-af91-46ad-b77d-16c56c062b7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644049371 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.c
lkmgr_csr_rw.644049371
Directory /workspace/6.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.3615250009
Short name T908
Test name
Test status
Simulation time 22228583 ps
CPU time 0.71 seconds
Started Jul 24 07:02:43 PM PDT 24
Finished Jul 24 07:02:44 PM PDT 24
Peak memory 199284 kb
Host smart-ca03f5c2-19a7-48a0-8e8a-290a4b46a720
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615250009 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_intr_test.3615250009
Directory /workspace/6.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.3454426981
Short name T872
Test name
Test status
Simulation time 34836622 ps
CPU time 1.26 seconds
Started Jul 24 07:02:42 PM PDT 24
Finished Jul 24 07:02:43 PM PDT 24
Peak memory 200900 kb
Host smart-45f7e400-8b84-4594-bd5b-61d608798a4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454426981 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.clkmgr_same_csr_outstanding.3454426981
Directory /workspace/6.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.3628118286
Short name T132
Test name
Test status
Simulation time 158805030 ps
CPU time 2.9 seconds
Started Jul 24 07:02:45 PM PDT 24
Finished Jul 24 07:02:48 PM PDT 24
Peak memory 209352 kb
Host smart-9111bf55-f42f-424a-8baa-b24f14975ea5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628118286 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors_with_csr_rw.3628118286
Directory /workspace/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.2279561149
Short name T906
Test name
Test status
Simulation time 32719331 ps
CPU time 1.9 seconds
Started Jul 24 07:02:42 PM PDT 24
Finished Jul 24 07:02:45 PM PDT 24
Peak memory 200840 kb
Host smart-350b302c-3da6-4209-8ab0-c7dcbf9f6ffd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279561149 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_tl_errors.2279561149
Directory /workspace/6.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.2537541025
Short name T105
Test name
Test status
Simulation time 250957978 ps
CPU time 3.18 seconds
Started Jul 24 07:02:41 PM PDT 24
Finished Jul 24 07:02:45 PM PDT 24
Peak memory 200968 kb
Host smart-441c5475-d408-4bfb-aa56-a44b825a6c87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537541025 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.clkmgr_tl_intg_err.2537541025
Directory /workspace/6.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.1741626455
Short name T974
Test name
Test status
Simulation time 82545378 ps
CPU time 1.45 seconds
Started Jul 24 07:02:48 PM PDT 24
Finished Jul 24 07:02:49 PM PDT 24
Peak memory 200820 kb
Host smart-0fba74a2-68b1-4ec8-8c1f-7bbbed64edfc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741626455 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_mem_rw_with_rand_reset.1741626455
Directory /workspace/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.3952274080
Short name T955
Test name
Test status
Simulation time 58511104 ps
CPU time 0.95 seconds
Started Jul 24 07:02:49 PM PDT 24
Finished Jul 24 07:02:50 PM PDT 24
Peak memory 200788 kb
Host smart-fe4e8e29-ded7-4460-aaa6-aaeef3e25060
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952274080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
clkmgr_csr_rw.3952274080
Directory /workspace/7.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.3677747210
Short name T963
Test name
Test status
Simulation time 38711692 ps
CPU time 0.75 seconds
Started Jul 24 07:03:01 PM PDT 24
Finished Jul 24 07:03:02 PM PDT 24
Peak memory 199260 kb
Host smart-5838c265-9a17-422f-adc7-f34a41f7383f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677747210 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_intr_test.3677747210
Directory /workspace/7.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.3233989161
Short name T944
Test name
Test status
Simulation time 24087813 ps
CPU time 1.1 seconds
Started Jul 24 07:03:01 PM PDT 24
Finished Jul 24 07:03:02 PM PDT 24
Peak memory 200744 kb
Host smart-44a87b8e-edfe-449e-9e2b-6e483b66368f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233989161 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.clkmgr_same_csr_outstanding.3233989161
Directory /workspace/7.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.4162919346
Short name T125
Test name
Test status
Simulation time 272612637 ps
CPU time 2.32 seconds
Started Jul 24 07:02:44 PM PDT 24
Finished Jul 24 07:02:46 PM PDT 24
Peak memory 217464 kb
Host smart-af2298d8-1e9d-4246-80a6-85386e1e4f91
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162919346 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 7.clkmgr_shadow_reg_errors.4162919346
Directory /workspace/7.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.277376119
Short name T876
Test name
Test status
Simulation time 83261599 ps
CPU time 2.33 seconds
Started Jul 24 07:02:47 PM PDT 24
Finished Jul 24 07:02:50 PM PDT 24
Peak memory 200816 kb
Host smart-2ca85aaa-4581-4d90-8876-089f1ebb7180
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277376119 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkm
gr_tl_errors.277376119
Directory /workspace/7.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.3613537316
Short name T969
Test name
Test status
Simulation time 348852272 ps
CPU time 2.91 seconds
Started Jul 24 07:02:47 PM PDT 24
Finished Jul 24 07:02:51 PM PDT 24
Peak memory 200916 kb
Host smart-079cc51c-6175-43cb-ab26-ef0c928e38ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613537316 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.clkmgr_tl_intg_err.3613537316
Directory /workspace/7.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.3055640953
Short name T913
Test name
Test status
Simulation time 27666310 ps
CPU time 0.94 seconds
Started Jul 24 07:02:52 PM PDT 24
Finished Jul 24 07:02:53 PM PDT 24
Peak memory 200868 kb
Host smart-793e7b76-95e6-407e-a374-372e78f9d13f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055640953 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_mem_rw_with_rand_reset.3055640953
Directory /workspace/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.537296105
Short name T976
Test name
Test status
Simulation time 23232157 ps
CPU time 0.75 seconds
Started Jul 24 07:02:49 PM PDT 24
Finished Jul 24 07:02:50 PM PDT 24
Peak memory 200748 kb
Host smart-5338432b-a20a-42a5-994b-dea662a39988
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537296105 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.c
lkmgr_csr_rw.537296105
Directory /workspace/8.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.4020307713
Short name T891
Test name
Test status
Simulation time 27126532 ps
CPU time 0.74 seconds
Started Jul 24 07:02:55 PM PDT 24
Finished Jul 24 07:02:56 PM PDT 24
Peak memory 199296 kb
Host smart-8a9d95f0-f2e5-40a7-8265-e32ce060bfa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020307713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk
mgr_intr_test.4020307713
Directory /workspace/8.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.3741828922
Short name T890
Test name
Test status
Simulation time 53222597 ps
CPU time 1.23 seconds
Started Jul 24 07:02:49 PM PDT 24
Finished Jul 24 07:02:50 PM PDT 24
Peak memory 200700 kb
Host smart-f471af4c-accc-40ab-9ebb-cdd2949f0f85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741828922 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.clkmgr_same_csr_outstanding.3741828922
Directory /workspace/8.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.709838351
Short name T131
Test name
Test status
Simulation time 96480210 ps
CPU time 1.67 seconds
Started Jul 24 07:02:54 PM PDT 24
Finished Jul 24 07:02:55 PM PDT 24
Peak memory 201056 kb
Host smart-a8ca73ab-9e51-4898-9dc9-6351dfd0b0d8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709838351 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.clkmgr_shadow_reg_errors.709838351
Directory /workspace/8.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.474360305
Short name T65
Test name
Test status
Simulation time 175267446 ps
CPU time 3.11 seconds
Started Jul 24 07:02:48 PM PDT 24
Finished Jul 24 07:02:51 PM PDT 24
Peak memory 201404 kb
Host smart-067cb25f-ad74-4d88-90eb-5295ce43244d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474360305 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors_with_csr_rw.474360305
Directory /workspace/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.1238535178
Short name T857
Test name
Test status
Simulation time 340158440 ps
CPU time 3.45 seconds
Started Jul 24 07:02:48 PM PDT 24
Finished Jul 24 07:02:51 PM PDT 24
Peak memory 200904 kb
Host smart-93fea205-58c8-42fd-a0f7-53f2510a0ae1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238535178 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk
mgr_tl_errors.1238535178
Directory /workspace/8.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.876962942
Short name T943
Test name
Test status
Simulation time 67380732 ps
CPU time 0.95 seconds
Started Jul 24 07:02:56 PM PDT 24
Finished Jul 24 07:02:57 PM PDT 24
Peak memory 200740 kb
Host smart-e500a246-019d-4af4-822d-a709116db916
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876962942 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_mem_rw_with_rand_reset.876962942
Directory /workspace/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.3845923827
Short name T929
Test name
Test status
Simulation time 16227794 ps
CPU time 0.76 seconds
Started Jul 24 07:02:53 PM PDT 24
Finished Jul 24 07:02:54 PM PDT 24
Peak memory 200776 kb
Host smart-f095073a-05fc-4c08-a631-c717063be6bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845923827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
clkmgr_csr_rw.3845923827
Directory /workspace/9.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.1674743879
Short name T846
Test name
Test status
Simulation time 20094554 ps
CPU time 0.68 seconds
Started Jul 24 07:02:56 PM PDT 24
Finished Jul 24 07:02:57 PM PDT 24
Peak memory 199336 kb
Host smart-456bc53c-ab4d-402b-91b2-a353992c233b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674743879 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk
mgr_intr_test.1674743879
Directory /workspace/9.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.3836847821
Short name T886
Test name
Test status
Simulation time 55244855 ps
CPU time 1.05 seconds
Started Jul 24 07:02:50 PM PDT 24
Finished Jul 24 07:02:51 PM PDT 24
Peak memory 200784 kb
Host smart-a8ab80d1-e974-49d2-a520-ddfc16343101
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836847821 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.clkmgr_same_csr_outstanding.3836847821
Directory /workspace/9.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.584333177
Short name T941
Test name
Test status
Simulation time 176488241 ps
CPU time 1.92 seconds
Started Jul 24 07:02:50 PM PDT 24
Finished Jul 24 07:02:52 PM PDT 24
Peak memory 209332 kb
Host smart-950f2123-bb66-4d9c-b158-7da202481a3b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584333177 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.clkmgr_shadow_reg_errors.584333177
Directory /workspace/9.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.3938085874
Short name T133
Test name
Test status
Simulation time 149316564 ps
CPU time 3.02 seconds
Started Jul 24 07:02:52 PM PDT 24
Finished Jul 24 07:02:55 PM PDT 24
Peak memory 201412 kb
Host smart-5ac45fb7-511e-4365-81dc-e7a4b6f6a34c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938085874 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors_with_csr_rw.3938085874
Directory /workspace/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.111233664
Short name T866
Test name
Test status
Simulation time 149154055 ps
CPU time 2.25 seconds
Started Jul 24 07:02:49 PM PDT 24
Finished Jul 24 07:02:52 PM PDT 24
Peak memory 200840 kb
Host smart-44a5c91d-419a-4db9-8441-414c95e48739
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111233664 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkm
gr_tl_errors.111233664
Directory /workspace/9.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.885827075
Short name T96
Test name
Test status
Simulation time 107648818 ps
CPU time 1.74 seconds
Started Jul 24 07:02:47 PM PDT 24
Finished Jul 24 07:02:49 PM PDT 24
Peak memory 200856 kb
Host smart-dfe4ca6a-d1be-4fd7-8a54-61719f99a750
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885827075 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.clkmgr_tl_intg_err.885827075
Directory /workspace/9.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.clkmgr_alert_test.3378843591
Short name T782
Test name
Test status
Simulation time 14754572 ps
CPU time 0.75 seconds
Started Jul 24 07:07:55 PM PDT 24
Finished Jul 24 07:07:56 PM PDT 24
Peak memory 200544 kb
Host smart-787d377a-f669-46cb-a048-67ebd09e4158
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378843591 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkm
gr_alert_test.3378843591
Directory /workspace/0.clkmgr_alert_test/latest

Test location /workspace/coverage/default/0.clkmgr_clk_status.863675072
Short name T533
Test name
Test status
Simulation time 13662608 ps
CPU time 0.72 seconds
Started Jul 24 07:07:55 PM PDT 24
Finished Jul 24 07:07:56 PM PDT 24
Peak memory 200380 kb
Host smart-ce668613-50d3-4641-9df5-3b2cd65ec55f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863675072 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.863675072
Directory /workspace/0.clkmgr_clk_status/latest

Test location /workspace/coverage/default/0.clkmgr_div_intersig_mubi.190832860
Short name T188
Test name
Test status
Simulation time 54271736 ps
CPU time 0.91 seconds
Started Jul 24 07:07:55 PM PDT 24
Finished Jul 24 07:07:56 PM PDT 24
Peak memory 200500 kb
Host smart-0a627f29-633f-4d42-a620-d02364515e98
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190832860 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.clkmgr_div_intersig_mubi.190832860
Directory /workspace/0.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_extclk.2365000728
Short name T376
Test name
Test status
Simulation time 26084922 ps
CPU time 0.87 seconds
Started Jul 24 07:07:54 PM PDT 24
Finished Jul 24 07:07:55 PM PDT 24
Peak memory 200488 kb
Host smart-37388017-e03b-456a-943d-713ed0b3eb4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365000728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.2365000728
Directory /workspace/0.clkmgr_extclk/latest

Test location /workspace/coverage/default/0.clkmgr_frequency.1256937962
Short name T116
Test name
Test status
Simulation time 473073741 ps
CPU time 2.66 seconds
Started Jul 24 07:08:03 PM PDT 24
Finished Jul 24 07:08:06 PM PDT 24
Peak memory 200476 kb
Host smart-ab825f51-1e79-4c4b-8c08-2c085c435737
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256937962 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.1256937962
Directory /workspace/0.clkmgr_frequency/latest

Test location /workspace/coverage/default/0.clkmgr_frequency_timeout.2542322431
Short name T226
Test name
Test status
Simulation time 2162183515 ps
CPU time 9.36 seconds
Started Jul 24 07:08:01 PM PDT 24
Finished Jul 24 07:08:11 PM PDT 24
Peak memory 200788 kb
Host smart-96cc0d7d-f5ab-4aca-9a02-32422ceb97bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542322431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_ti
meout.2542322431
Directory /workspace/0.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/0.clkmgr_idle_intersig_mubi.3167713185
Short name T467
Test name
Test status
Simulation time 70339514 ps
CPU time 1.05 seconds
Started Jul 24 07:07:55 PM PDT 24
Finished Jul 24 07:07:57 PM PDT 24
Peak memory 200452 kb
Host smart-8c323a24-8c0f-490e-88e1-751711bc3047
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167713185 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_idle_intersig_mubi.3167713185
Directory /workspace/0.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.2958134694
Short name T749
Test name
Test status
Simulation time 21633344 ps
CPU time 0.85 seconds
Started Jul 24 07:08:00 PM PDT 24
Finished Jul 24 07:08:01 PM PDT 24
Peak memory 200492 kb
Host smart-8fd0a1de-9dbe-434d-afc1-0dbf0defa17e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958134694 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_lc_clk_byp_req_intersig_mubi.2958134694
Directory /workspace/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.3633079041
Short name T277
Test name
Test status
Simulation time 62606216 ps
CPU time 0.97 seconds
Started Jul 24 07:07:54 PM PDT 24
Finished Jul 24 07:07:56 PM PDT 24
Peak memory 200468 kb
Host smart-07659961-dcba-4364-a757-605515d1949d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633079041 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_lc_ctrl_intersig_mubi.3633079041
Directory /workspace/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_peri.2875508441
Short name T322
Test name
Test status
Simulation time 13824766 ps
CPU time 0.78 seconds
Started Jul 24 07:07:51 PM PDT 24
Finished Jul 24 07:07:52 PM PDT 24
Peak memory 200416 kb
Host smart-28baa362-813d-4563-86a2-028683c94b71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875508441 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.2875508441
Directory /workspace/0.clkmgr_peri/latest

Test location /workspace/coverage/default/0.clkmgr_regwen.435353692
Short name T589
Test name
Test status
Simulation time 376291109 ps
CPU time 2.6 seconds
Started Jul 24 07:07:55 PM PDT 24
Finished Jul 24 07:07:58 PM PDT 24
Peak memory 200520 kb
Host smart-f62c1518-e828-4f29-b831-de05df25dd0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435353692 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.435353692
Directory /workspace/0.clkmgr_regwen/latest

Test location /workspace/coverage/default/0.clkmgr_smoke.3677869543
Short name T818
Test name
Test status
Simulation time 50717769 ps
CPU time 0.92 seconds
Started Jul 24 07:07:55 PM PDT 24
Finished Jul 24 07:07:57 PM PDT 24
Peak memory 200352 kb
Host smart-c31cf45a-a3fc-42e0-9f4b-ac84737e850b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677869543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.3677869543
Directory /workspace/0.clkmgr_smoke/latest

Test location /workspace/coverage/default/0.clkmgr_stress_all.2738159353
Short name T465
Test name
Test status
Simulation time 3770470786 ps
CPU time 26.99 seconds
Started Jul 24 07:07:54 PM PDT 24
Finished Jul 24 07:08:21 PM PDT 24
Peak memory 200768 kb
Host smart-5c66e944-0c77-4a83-8c42-372b110412dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738159353 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_stress_all.2738159353
Directory /workspace/0.clkmgr_stress_all/latest

Test location /workspace/coverage/default/0.clkmgr_stress_all_with_rand_reset.3725979831
Short name T73
Test name
Test status
Simulation time 25371614761 ps
CPU time 373.81 seconds
Started Jul 24 07:07:56 PM PDT 24
Finished Jul 24 07:14:10 PM PDT 24
Peak memory 209104 kb
Host smart-04f34279-3fc0-4079-9a41-61cfed7854a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3725979831 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all_with_rand_reset.3725979831
Directory /workspace/0.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.clkmgr_trans.1728122741
Short name T719
Test name
Test status
Simulation time 99334955 ps
CPU time 1.18 seconds
Started Jul 24 07:07:57 PM PDT 24
Finished Jul 24 07:07:58 PM PDT 24
Peak memory 200452 kb
Host smart-3a5b1b81-6741-40ea-aceb-b05cc624f462
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728122741 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.1728122741
Directory /workspace/0.clkmgr_trans/latest

Test location /workspace/coverage/default/1.clkmgr_alert_test.2341438812
Short name T178
Test name
Test status
Simulation time 18804500 ps
CPU time 0.8 seconds
Started Jul 24 07:07:55 PM PDT 24
Finished Jul 24 07:07:56 PM PDT 24
Peak memory 200572 kb
Host smart-898dcaaa-dec2-4802-8586-84a679a26cb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341438812 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkm
gr_alert_test.2341438812
Directory /workspace/1.clkmgr_alert_test/latest

Test location /workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.2664878226
Short name T338
Test name
Test status
Simulation time 60217355 ps
CPU time 0.89 seconds
Started Jul 24 07:07:59 PM PDT 24
Finished Jul 24 07:08:00 PM PDT 24
Peak memory 200388 kb
Host smart-bdaa7f85-5808-4fc0-8236-f7140be3917e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664878226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_clk_handshake_intersig_mubi.2664878226
Directory /workspace/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_clk_status.2113560943
Short name T39
Test name
Test status
Simulation time 43514135 ps
CPU time 0.78 seconds
Started Jul 24 07:07:55 PM PDT 24
Finished Jul 24 07:07:56 PM PDT 24
Peak memory 199656 kb
Host smart-e49dc6fb-1652-4f2a-b86a-99e6fbe67e85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113560943 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.2113560943
Directory /workspace/1.clkmgr_clk_status/latest

Test location /workspace/coverage/default/1.clkmgr_div_intersig_mubi.3397648531
Short name T477
Test name
Test status
Simulation time 31128413 ps
CPU time 0.86 seconds
Started Jul 24 07:07:58 PM PDT 24
Finished Jul 24 07:07:59 PM PDT 24
Peak memory 200472 kb
Host smart-e59a4938-ddfe-46a4-bcd7-2e7b185a9273
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397648531 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_div_intersig_mubi.3397648531
Directory /workspace/1.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_extclk.1683379661
Short name T489
Test name
Test status
Simulation time 27191870 ps
CPU time 0.82 seconds
Started Jul 24 07:08:00 PM PDT 24
Finished Jul 24 07:08:01 PM PDT 24
Peak memory 200484 kb
Host smart-5dc02b1a-df64-4b36-afed-ae9af8037ff9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683379661 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.1683379661
Directory /workspace/1.clkmgr_extclk/latest

Test location /workspace/coverage/default/1.clkmgr_frequency.1643296880
Short name T463
Test name
Test status
Simulation time 855867679 ps
CPU time 4.29 seconds
Started Jul 24 07:08:03 PM PDT 24
Finished Jul 24 07:08:07 PM PDT 24
Peak memory 200472 kb
Host smart-ee2ebf82-5357-464b-bf1f-e210415fcb63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643296880 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.1643296880
Directory /workspace/1.clkmgr_frequency/latest

Test location /workspace/coverage/default/1.clkmgr_frequency_timeout.111716596
Short name T82
Test name
Test status
Simulation time 1220611863 ps
CPU time 8.84 seconds
Started Jul 24 07:07:56 PM PDT 24
Finished Jul 24 07:08:05 PM PDT 24
Peak memory 200544 kb
Host smart-3916fc2c-40ac-41c0-99f6-355eb78696f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111716596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_tim
eout.111716596
Directory /workspace/1.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.3965970152
Short name T427
Test name
Test status
Simulation time 20760491 ps
CPU time 0.84 seconds
Started Jul 24 07:07:58 PM PDT 24
Finished Jul 24 07:07:59 PM PDT 24
Peak memory 200452 kb
Host smart-c705874d-d884-47c2-aa1b-60e7e2b86936
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965970152 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_lc_clk_byp_req_intersig_mubi.3965970152
Directory /workspace/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.2248677324
Short name T231
Test name
Test status
Simulation time 38521180 ps
CPU time 0.97 seconds
Started Jul 24 07:07:58 PM PDT 24
Finished Jul 24 07:07:59 PM PDT 24
Peak memory 200492 kb
Host smart-2b73a305-8681-4f29-94e8-429837903699
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248677324 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_lc_ctrl_intersig_mubi.2248677324
Directory /workspace/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_peri.1741142516
Short name T536
Test name
Test status
Simulation time 22554037 ps
CPU time 0.84 seconds
Started Jul 24 07:07:59 PM PDT 24
Finished Jul 24 07:08:00 PM PDT 24
Peak memory 200480 kb
Host smart-5abcb18c-fdfb-4e5c-9dba-ced96327300a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741142516 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.1741142516
Directory /workspace/1.clkmgr_peri/latest

Test location /workspace/coverage/default/1.clkmgr_regwen.2000822208
Short name T9
Test name
Test status
Simulation time 1085633417 ps
CPU time 6.05 seconds
Started Jul 24 07:08:01 PM PDT 24
Finished Jul 24 07:08:07 PM PDT 24
Peak memory 200712 kb
Host smart-9352800e-dfcd-4fc4-a7cb-9bef23b251fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000822208 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.2000822208
Directory /workspace/1.clkmgr_regwen/latest

Test location /workspace/coverage/default/1.clkmgr_sec_cm.1067924026
Short name T45
Test name
Test status
Simulation time 416965709 ps
CPU time 3.99 seconds
Started Jul 24 07:07:58 PM PDT 24
Finished Jul 24 07:08:02 PM PDT 24
Peak memory 217108 kb
Host smart-53530a1b-2c00-4923-92c9-ea0ff681a08e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067924026 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmg
r_sec_cm.1067924026
Directory /workspace/1.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/1.clkmgr_smoke.2850078747
Short name T694
Test name
Test status
Simulation time 59926876 ps
CPU time 0.99 seconds
Started Jul 24 07:08:00 PM PDT 24
Finished Jul 24 07:08:01 PM PDT 24
Peak memory 200484 kb
Host smart-157e2f2e-cfc1-41b6-92a1-339a86f9f73a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850078747 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.2850078747
Directory /workspace/1.clkmgr_smoke/latest

Test location /workspace/coverage/default/1.clkmgr_stress_all.3429956480
Short name T752
Test name
Test status
Simulation time 2664487062 ps
CPU time 12.52 seconds
Started Jul 24 07:07:59 PM PDT 24
Finished Jul 24 07:08:12 PM PDT 24
Peak memory 200788 kb
Host smart-74abc2a3-68e1-4b8d-adba-a7ba6da8c8c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429956480 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_stress_all.3429956480
Directory /workspace/1.clkmgr_stress_all/latest

Test location /workspace/coverage/default/1.clkmgr_stress_all_with_rand_reset.779930126
Short name T70
Test name
Test status
Simulation time 196051714137 ps
CPU time 1354.26 seconds
Started Jul 24 07:07:59 PM PDT 24
Finished Jul 24 07:30:33 PM PDT 24
Peak memory 217284 kb
Host smart-98f7caac-fe4f-4826-b318-0aab211cb23b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=779930126 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all_with_rand_reset.779930126
Directory /workspace/1.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.clkmgr_trans.2966613414
Short name T763
Test name
Test status
Simulation time 51418825 ps
CPU time 0.97 seconds
Started Jul 24 07:07:58 PM PDT 24
Finished Jul 24 07:08:00 PM PDT 24
Peak memory 200440 kb
Host smart-888d57b3-4e4a-41ed-b1f8-b56246ef9447
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966613414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.2966613414
Directory /workspace/1.clkmgr_trans/latest

Test location /workspace/coverage/default/10.clkmgr_alert_test.3837633602
Short name T365
Test name
Test status
Simulation time 48164418 ps
CPU time 0.92 seconds
Started Jul 24 07:08:28 PM PDT 24
Finished Jul 24 07:08:30 PM PDT 24
Peak memory 200552 kb
Host smart-afd688ae-2517-4416-83f9-3a05b11d2dc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837633602 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clk
mgr_alert_test.3837633602
Directory /workspace/10.clkmgr_alert_test/latest

Test location /workspace/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.3435002839
Short name T81
Test name
Test status
Simulation time 91399897 ps
CPU time 1.11 seconds
Started Jul 24 07:08:22 PM PDT 24
Finished Jul 24 07:08:23 PM PDT 24
Peak memory 200476 kb
Host smart-7bbcc119-d836-498f-aae5-ae18b93422f0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435002839 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_clk_handshake_intersig_mubi.3435002839
Directory /workspace/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_clk_status.154831293
Short name T811
Test name
Test status
Simulation time 16861707 ps
CPU time 0.74 seconds
Started Jul 24 07:08:21 PM PDT 24
Finished Jul 24 07:08:22 PM PDT 24
Peak memory 199656 kb
Host smart-7b5ddd0f-a3ee-4dbe-9e21-1620456762fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154831293 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.154831293
Directory /workspace/10.clkmgr_clk_status/latest

Test location /workspace/coverage/default/10.clkmgr_div_intersig_mubi.704843931
Short name T495
Test name
Test status
Simulation time 83484998 ps
CPU time 0.95 seconds
Started Jul 24 07:08:23 PM PDT 24
Finished Jul 24 07:08:24 PM PDT 24
Peak memory 200472 kb
Host smart-8174ae9f-c5bd-49af-b0ff-6988b7295e23
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704843931 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.clkmgr_div_intersig_mubi.704843931
Directory /workspace/10.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_extclk.2094286769
Short name T349
Test name
Test status
Simulation time 30511773 ps
CPU time 0.95 seconds
Started Jul 24 07:08:25 PM PDT 24
Finished Jul 24 07:08:26 PM PDT 24
Peak memory 200516 kb
Host smart-137c22c5-7706-440b-b9fe-c0af921b4f4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094286769 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.2094286769
Directory /workspace/10.clkmgr_extclk/latest

Test location /workspace/coverage/default/10.clkmgr_frequency.1393944133
Short name T17
Test name
Test status
Simulation time 475687534 ps
CPU time 2.58 seconds
Started Jul 24 07:08:17 PM PDT 24
Finished Jul 24 07:08:20 PM PDT 24
Peak memory 200488 kb
Host smart-032d86d0-968f-43d7-9053-be9a80d31377
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393944133 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.1393944133
Directory /workspace/10.clkmgr_frequency/latest

Test location /workspace/coverage/default/10.clkmgr_frequency_timeout.2717221644
Short name T458
Test name
Test status
Simulation time 646737428 ps
CPU time 2.56 seconds
Started Jul 24 07:08:21 PM PDT 24
Finished Jul 24 07:08:24 PM PDT 24
Peak memory 200536 kb
Host smart-6446f9ef-dd88-421f-9871-9ecb317c1eb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717221644 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_t
imeout.2717221644
Directory /workspace/10.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/10.clkmgr_idle_intersig_mubi.1088247730
Short name T356
Test name
Test status
Simulation time 36259219 ps
CPU time 1.03 seconds
Started Jul 24 07:08:31 PM PDT 24
Finished Jul 24 07:08:33 PM PDT 24
Peak memory 200464 kb
Host smart-9c76f951-f137-443a-bb1a-d48edbd136fb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088247730 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_idle_intersig_mubi.1088247730
Directory /workspace/10.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.30198995
Short name T511
Test name
Test status
Simulation time 87858528 ps
CPU time 1.07 seconds
Started Jul 24 07:08:14 PM PDT 24
Finished Jul 24 07:08:15 PM PDT 24
Peak memory 200536 kb
Host smart-2869e00a-831b-4379-b4d0-60c862808ed0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30198995 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_lc_clk_byp_req_intersig_mubi.30198995
Directory /workspace/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.1514401863
Short name T333
Test name
Test status
Simulation time 102581570 ps
CPU time 1.11 seconds
Started Jul 24 07:08:24 PM PDT 24
Finished Jul 24 07:08:25 PM PDT 24
Peak memory 200376 kb
Host smart-4f7cdc80-37a6-4b36-9fae-ca1bbc0e8b9c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514401863 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.clkmgr_lc_ctrl_intersig_mubi.1514401863
Directory /workspace/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_peri.4260095502
Short name T595
Test name
Test status
Simulation time 35606908 ps
CPU time 0.8 seconds
Started Jul 24 07:08:27 PM PDT 24
Finished Jul 24 07:08:28 PM PDT 24
Peak memory 200440 kb
Host smart-e33b43e7-5760-4dd1-a158-dc516b68e789
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260095502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.4260095502
Directory /workspace/10.clkmgr_peri/latest

Test location /workspace/coverage/default/10.clkmgr_regwen.3477015591
Short name T568
Test name
Test status
Simulation time 981174226 ps
CPU time 3.66 seconds
Started Jul 24 07:08:19 PM PDT 24
Finished Jul 24 07:08:23 PM PDT 24
Peak memory 200676 kb
Host smart-0630c6a9-b6e0-469f-9e25-ad782602f2cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477015591 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.3477015591
Directory /workspace/10.clkmgr_regwen/latest

Test location /workspace/coverage/default/10.clkmgr_smoke.3881848877
Short name T355
Test name
Test status
Simulation time 30410209 ps
CPU time 0.91 seconds
Started Jul 24 07:08:31 PM PDT 24
Finished Jul 24 07:08:33 PM PDT 24
Peak memory 200488 kb
Host smart-fb65b2bd-3671-40fb-971e-acaf6365d80a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881848877 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.3881848877
Directory /workspace/10.clkmgr_smoke/latest

Test location /workspace/coverage/default/10.clkmgr_stress_all.1990663849
Short name T303
Test name
Test status
Simulation time 5680501294 ps
CPU time 41.72 seconds
Started Jul 24 07:08:26 PM PDT 24
Finished Jul 24 07:09:08 PM PDT 24
Peak memory 200772 kb
Host smart-11549c49-1ee7-475e-878d-9cb68d68dac8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990663849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_stress_all.1990663849
Directory /workspace/10.clkmgr_stress_all/latest

Test location /workspace/coverage/default/10.clkmgr_trans.878267354
Short name T464
Test name
Test status
Simulation time 80853686 ps
CPU time 1.06 seconds
Started Jul 24 07:08:13 PM PDT 24
Finished Jul 24 07:08:14 PM PDT 24
Peak memory 200428 kb
Host smart-6abb42c7-7b3f-4b89-ba89-eda63264379b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878267354 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.878267354
Directory /workspace/10.clkmgr_trans/latest

Test location /workspace/coverage/default/11.clkmgr_alert_test.1981499373
Short name T777
Test name
Test status
Simulation time 43568255 ps
CPU time 0.87 seconds
Started Jul 24 07:08:28 PM PDT 24
Finished Jul 24 07:08:29 PM PDT 24
Peak memory 200536 kb
Host smart-48801b74-af2c-49b7-9459-7329e9356c3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981499373 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clk
mgr_alert_test.1981499373
Directory /workspace/11.clkmgr_alert_test/latest

Test location /workspace/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.3734592630
Short name T498
Test name
Test status
Simulation time 21608613 ps
CPU time 0.86 seconds
Started Jul 24 07:08:24 PM PDT 24
Finished Jul 24 07:08:25 PM PDT 24
Peak memory 200692 kb
Host smart-e003772e-25ca-4589-8041-3bb5beaa86ad
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734592630 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_clk_handshake_intersig_mubi.3734592630
Directory /workspace/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_clk_status.52638173
Short name T685
Test name
Test status
Simulation time 15506554 ps
CPU time 0.75 seconds
Started Jul 24 07:08:27 PM PDT 24
Finished Jul 24 07:08:28 PM PDT 24
Peak memory 199656 kb
Host smart-a22c1279-5f18-490b-bbfe-ae50975ae731
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52638173 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.52638173
Directory /workspace/11.clkmgr_clk_status/latest

Test location /workspace/coverage/default/11.clkmgr_div_intersig_mubi.2128898798
Short name T203
Test name
Test status
Simulation time 17153205 ps
CPU time 0.83 seconds
Started Jul 24 07:08:26 PM PDT 24
Finished Jul 24 07:08:27 PM PDT 24
Peak memory 200436 kb
Host smart-48175d02-615f-4b67-a1c3-6650470950a3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128898798 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_div_intersig_mubi.2128898798
Directory /workspace/11.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_extclk.3791126956
Short name T428
Test name
Test status
Simulation time 33593394 ps
CPU time 0.9 seconds
Started Jul 24 07:08:23 PM PDT 24
Finished Jul 24 07:08:24 PM PDT 24
Peak memory 200472 kb
Host smart-c26ab120-ba4e-43c1-b94e-cf87047c2d09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791126956 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.3791126956
Directory /workspace/11.clkmgr_extclk/latest

Test location /workspace/coverage/default/11.clkmgr_frequency.3697323050
Short name T507
Test name
Test status
Simulation time 707223314 ps
CPU time 3.61 seconds
Started Jul 24 07:08:21 PM PDT 24
Finished Jul 24 07:08:25 PM PDT 24
Peak memory 200488 kb
Host smart-dec973eb-0776-4faa-8150-e8fbe040b6a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697323050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.3697323050
Directory /workspace/11.clkmgr_frequency/latest

Test location /workspace/coverage/default/11.clkmgr_frequency_timeout.1193345817
Short name T401
Test name
Test status
Simulation time 2418229067 ps
CPU time 17.04 seconds
Started Jul 24 07:08:26 PM PDT 24
Finished Jul 24 07:08:43 PM PDT 24
Peak memory 200636 kb
Host smart-cc6d6c9a-55b6-4449-aa90-5e03ce474ee5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193345817 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_t
imeout.1193345817
Directory /workspace/11.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/11.clkmgr_idle_intersig_mubi.4017008409
Short name T474
Test name
Test status
Simulation time 31039031 ps
CPU time 0.95 seconds
Started Jul 24 07:08:30 PM PDT 24
Finished Jul 24 07:08:31 PM PDT 24
Peak memory 200476 kb
Host smart-0c203efb-e318-4f90-9280-dff0a9f8c5bd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017008409 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_idle_intersig_mubi.4017008409
Directory /workspace/11.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.47341708
Short name T657
Test name
Test status
Simulation time 55759240 ps
CPU time 0.9 seconds
Started Jul 24 07:08:14 PM PDT 24
Finished Jul 24 07:08:15 PM PDT 24
Peak memory 200436 kb
Host smart-64a8d8d6-7580-40ae-ab09-4c55d5464c9f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47341708 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_lc_clk_byp_req_intersig_mubi.47341708
Directory /workspace/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.3495839586
Short name T210
Test name
Test status
Simulation time 20436098 ps
CPU time 0.85 seconds
Started Jul 24 07:08:15 PM PDT 24
Finished Jul 24 07:08:16 PM PDT 24
Peak memory 200368 kb
Host smart-baa06239-0f3e-4309-af07-caa1d868586c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495839586 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.clkmgr_lc_ctrl_intersig_mubi.3495839586
Directory /workspace/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_peri.3750411602
Short name T357
Test name
Test status
Simulation time 16962136 ps
CPU time 0.8 seconds
Started Jul 24 07:08:23 PM PDT 24
Finished Jul 24 07:08:24 PM PDT 24
Peak memory 200452 kb
Host smart-1389e980-35f6-4466-b454-4b961daf582b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750411602 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.3750411602
Directory /workspace/11.clkmgr_peri/latest

Test location /workspace/coverage/default/11.clkmgr_regwen.3801859691
Short name T469
Test name
Test status
Simulation time 265583664 ps
CPU time 1.51 seconds
Started Jul 24 07:08:26 PM PDT 24
Finished Jul 24 07:08:27 PM PDT 24
Peak memory 200420 kb
Host smart-e1a8896a-c979-48e4-b5f4-394347d172cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801859691 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.3801859691
Directory /workspace/11.clkmgr_regwen/latest

Test location /workspace/coverage/default/11.clkmgr_smoke.802431962
Short name T143
Test name
Test status
Simulation time 305245921 ps
CPU time 1.65 seconds
Started Jul 24 07:08:28 PM PDT 24
Finished Jul 24 07:08:30 PM PDT 24
Peak memory 200476 kb
Host smart-113ebef6-d1b4-4dbe-af29-9692aac07e04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802431962 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.802431962
Directory /workspace/11.clkmgr_smoke/latest

Test location /workspace/coverage/default/11.clkmgr_stress_all.2745590325
Short name T705
Test name
Test status
Simulation time 10223195043 ps
CPU time 33.22 seconds
Started Jul 24 07:08:24 PM PDT 24
Finished Jul 24 07:08:57 PM PDT 24
Peak memory 200796 kb
Host smart-48e548a9-30d1-43f6-8b19-28703a0f6964
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745590325 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_stress_all.2745590325
Directory /workspace/11.clkmgr_stress_all/latest

Test location /workspace/coverage/default/11.clkmgr_stress_all_with_rand_reset.4090948913
Short name T71
Test name
Test status
Simulation time 56741334260 ps
CPU time 404.3 seconds
Started Jul 24 07:08:24 PM PDT 24
Finished Jul 24 07:15:09 PM PDT 24
Peak memory 217316 kb
Host smart-f4b2d59a-1afd-4639-8b7d-130d5c831046
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4090948913 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all_with_rand_reset.4090948913
Directory /workspace/11.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.clkmgr_trans.3478207341
Short name T206
Test name
Test status
Simulation time 63207846 ps
CPU time 0.97 seconds
Started Jul 24 07:08:25 PM PDT 24
Finished Jul 24 07:08:26 PM PDT 24
Peak memory 200388 kb
Host smart-ae18c651-947c-4ff8-bd26-393e02e771bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478207341 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.3478207341
Directory /workspace/11.clkmgr_trans/latest

Test location /workspace/coverage/default/12.clkmgr_alert_test.354882755
Short name T383
Test name
Test status
Simulation time 44927715 ps
CPU time 0.83 seconds
Started Jul 24 07:08:31 PM PDT 24
Finished Jul 24 07:08:32 PM PDT 24
Peak memory 200544 kb
Host smart-00f2be7b-b621-41be-801e-5937f2a240b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354882755 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkm
gr_alert_test.354882755
Directory /workspace/12.clkmgr_alert_test/latest

Test location /workspace/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.3784865713
Short name T278
Test name
Test status
Simulation time 32338015 ps
CPU time 0.98 seconds
Started Jul 24 07:08:27 PM PDT 24
Finished Jul 24 07:08:28 PM PDT 24
Peak memory 200484 kb
Host smart-90eac1b9-7e25-4b59-8126-680fb69b95c6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784865713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_clk_handshake_intersig_mubi.3784865713
Directory /workspace/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_clk_status.3764373603
Short name T569
Test name
Test status
Simulation time 24386037 ps
CPU time 0.73 seconds
Started Jul 24 07:08:25 PM PDT 24
Finished Jul 24 07:08:26 PM PDT 24
Peak memory 199564 kb
Host smart-c526339c-ecfa-46c0-971f-35a7a78bf9ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764373603 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.3764373603
Directory /workspace/12.clkmgr_clk_status/latest

Test location /workspace/coverage/default/12.clkmgr_div_intersig_mubi.2028301202
Short name T243
Test name
Test status
Simulation time 59196160 ps
CPU time 0.95 seconds
Started Jul 24 07:08:21 PM PDT 24
Finished Jul 24 07:08:22 PM PDT 24
Peak memory 200476 kb
Host smart-70c4ff87-b158-450c-a623-a14b271d94bd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028301202 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_div_intersig_mubi.2028301202
Directory /workspace/12.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_extclk.1731507521
Short name T486
Test name
Test status
Simulation time 24371381 ps
CPU time 0.8 seconds
Started Jul 24 07:08:27 PM PDT 24
Finished Jul 24 07:08:28 PM PDT 24
Peak memory 200464 kb
Host smart-6fdd2b74-7caa-4948-90bb-66a130b501ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731507521 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.1731507521
Directory /workspace/12.clkmgr_extclk/latest

Test location /workspace/coverage/default/12.clkmgr_frequency.1161933292
Short name T49
Test name
Test status
Simulation time 1526593316 ps
CPU time 8.7 seconds
Started Jul 24 07:08:22 PM PDT 24
Finished Jul 24 07:08:31 PM PDT 24
Peak memory 200460 kb
Host smart-69b7f47c-1f03-45ea-86fe-8f1b6ed49bfd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161933292 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.1161933292
Directory /workspace/12.clkmgr_frequency/latest

Test location /workspace/coverage/default/12.clkmgr_frequency_timeout.3180869342
Short name T722
Test name
Test status
Simulation time 2182051772 ps
CPU time 16.41 seconds
Started Jul 24 07:08:41 PM PDT 24
Finished Jul 24 07:08:57 PM PDT 24
Peak memory 200716 kb
Host smart-8585fd34-4823-4aff-990e-069fce39a83e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180869342 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_t
imeout.3180869342
Directory /workspace/12.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/12.clkmgr_idle_intersig_mubi.2838864147
Short name T617
Test name
Test status
Simulation time 24261454 ps
CPU time 0.76 seconds
Started Jul 24 07:08:29 PM PDT 24
Finished Jul 24 07:08:30 PM PDT 24
Peak memory 200464 kb
Host smart-b54bb7a5-4fbd-4d80-88f1-3827ebac6cea
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838864147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_idle_intersig_mubi.2838864147
Directory /workspace/12.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.3304185840
Short name T521
Test name
Test status
Simulation time 23642536 ps
CPU time 0.89 seconds
Started Jul 24 07:08:26 PM PDT 24
Finished Jul 24 07:08:27 PM PDT 24
Peak memory 200432 kb
Host smart-892c1686-d5c8-440b-9ed1-55a0c6da95e1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304185840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.clkmgr_lc_clk_byp_req_intersig_mubi.3304185840
Directory /workspace/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.1374565752
Short name T387
Test name
Test status
Simulation time 85750672 ps
CPU time 1.05 seconds
Started Jul 24 07:08:27 PM PDT 24
Finished Jul 24 07:08:29 PM PDT 24
Peak memory 200464 kb
Host smart-5b131914-b7c6-4dfb-9eb9-206185b72bc1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374565752 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.clkmgr_lc_ctrl_intersig_mubi.1374565752
Directory /workspace/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_peri.2342285813
Short name T298
Test name
Test status
Simulation time 27277415 ps
CPU time 0.78 seconds
Started Jul 24 07:08:26 PM PDT 24
Finished Jul 24 07:08:27 PM PDT 24
Peak memory 200460 kb
Host smart-547bec69-ebe7-4c99-9908-125981efbc59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342285813 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.2342285813
Directory /workspace/12.clkmgr_peri/latest

Test location /workspace/coverage/default/12.clkmgr_regwen.2482055147
Short name T535
Test name
Test status
Simulation time 936955046 ps
CPU time 5.43 seconds
Started Jul 24 07:08:26 PM PDT 24
Finished Jul 24 07:08:32 PM PDT 24
Peak memory 200644 kb
Host smart-107decc0-5dc4-46ae-a8ff-0e79b24901e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482055147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.2482055147
Directory /workspace/12.clkmgr_regwen/latest

Test location /workspace/coverage/default/12.clkmgr_smoke.209333878
Short name T691
Test name
Test status
Simulation time 20275691 ps
CPU time 0.88 seconds
Started Jul 24 07:08:22 PM PDT 24
Finished Jul 24 07:08:23 PM PDT 24
Peak memory 200444 kb
Host smart-46e0026c-8ba5-47d4-9095-2783985882e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209333878 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.209333878
Directory /workspace/12.clkmgr_smoke/latest

Test location /workspace/coverage/default/12.clkmgr_stress_all.328077322
Short name T597
Test name
Test status
Simulation time 10231587450 ps
CPU time 52.66 seconds
Started Jul 24 07:08:26 PM PDT 24
Finished Jul 24 07:09:19 PM PDT 24
Peak memory 200728 kb
Host smart-7b92d396-5e8d-4d44-8687-6df42e7ff405
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328077322 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_stress_all.328077322
Directory /workspace/12.clkmgr_stress_all/latest

Test location /workspace/coverage/default/12.clkmgr_trans.933528386
Short name T266
Test name
Test status
Simulation time 23223961 ps
CPU time 0.89 seconds
Started Jul 24 07:08:23 PM PDT 24
Finished Jul 24 07:08:25 PM PDT 24
Peak memory 200452 kb
Host smart-2702d11c-d1dd-46f2-8426-0a125457d4a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933528386 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.933528386
Directory /workspace/12.clkmgr_trans/latest

Test location /workspace/coverage/default/13.clkmgr_alert_test.2236019374
Short name T730
Test name
Test status
Simulation time 42842444 ps
CPU time 0.82 seconds
Started Jul 24 07:08:21 PM PDT 24
Finished Jul 24 07:08:22 PM PDT 24
Peak memory 200532 kb
Host smart-ccff62ea-ac36-434e-93cf-ff7936925c6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236019374 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clk
mgr_alert_test.2236019374
Directory /workspace/13.clkmgr_alert_test/latest

Test location /workspace/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.3025187063
Short name T146
Test name
Test status
Simulation time 14560661 ps
CPU time 0.75 seconds
Started Jul 24 07:08:29 PM PDT 24
Finished Jul 24 07:08:30 PM PDT 24
Peak memory 200460 kb
Host smart-ae2ded2c-0a46-4df6-802c-8d4b8c9c554f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025187063 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_clk_handshake_intersig_mubi.3025187063
Directory /workspace/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_clk_status.2169137218
Short name T741
Test name
Test status
Simulation time 23828973 ps
CPU time 0.79 seconds
Started Jul 24 07:08:27 PM PDT 24
Finished Jul 24 07:08:28 PM PDT 24
Peak memory 200400 kb
Host smart-7d2a72e8-154a-4619-9244-0dcbf9cb9a0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169137218 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.2169137218
Directory /workspace/13.clkmgr_clk_status/latest

Test location /workspace/coverage/default/13.clkmgr_div_intersig_mubi.3146151556
Short name T420
Test name
Test status
Simulation time 35736580 ps
CPU time 0.89 seconds
Started Jul 24 07:08:27 PM PDT 24
Finished Jul 24 07:08:28 PM PDT 24
Peak memory 200420 kb
Host smart-35764d4d-5c99-4ab0-b1d4-d5dc0e986b81
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146151556 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_div_intersig_mubi.3146151556
Directory /workspace/13.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_extclk.2433737738
Short name T531
Test name
Test status
Simulation time 22051076 ps
CPU time 0.77 seconds
Started Jul 24 07:08:22 PM PDT 24
Finished Jul 24 07:08:22 PM PDT 24
Peak memory 200532 kb
Host smart-6904782f-c055-4bb4-a8f3-31ef49a83322
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433737738 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.2433737738
Directory /workspace/13.clkmgr_extclk/latest

Test location /workspace/coverage/default/13.clkmgr_frequency.4208832346
Short name T315
Test name
Test status
Simulation time 1155537875 ps
CPU time 8.92 seconds
Started Jul 24 07:08:30 PM PDT 24
Finished Jul 24 07:08:39 PM PDT 24
Peak memory 200492 kb
Host smart-02c65d24-d221-4958-9886-e0fff59bbbae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208832346 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.4208832346
Directory /workspace/13.clkmgr_frequency/latest

Test location /workspace/coverage/default/13.clkmgr_frequency_timeout.1059538729
Short name T252
Test name
Test status
Simulation time 1591280069 ps
CPU time 6.22 seconds
Started Jul 24 07:08:27 PM PDT 24
Finished Jul 24 07:08:34 PM PDT 24
Peak memory 200600 kb
Host smart-79510ce7-ae28-4159-81f2-9044a33b796c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059538729 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_t
imeout.1059538729
Directory /workspace/13.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/13.clkmgr_idle_intersig_mubi.2909148953
Short name T716
Test name
Test status
Simulation time 40688613 ps
CPU time 0.94 seconds
Started Jul 24 07:08:23 PM PDT 24
Finished Jul 24 07:08:24 PM PDT 24
Peak memory 200488 kb
Host smart-022dfcde-564a-423f-be0d-ed7343ad1549
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909148953 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_idle_intersig_mubi.2909148953
Directory /workspace/13.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.857176813
Short name T462
Test name
Test status
Simulation time 314860565 ps
CPU time 1.68 seconds
Started Jul 24 07:08:18 PM PDT 24
Finished Jul 24 07:08:19 PM PDT 24
Peak memory 200692 kb
Host smart-4db95163-8bb0-44c9-87f1-4afcecb3fb93
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857176813 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.clkmgr_lc_clk_byp_req_intersig_mubi.857176813
Directory /workspace/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.378055437
Short name T608
Test name
Test status
Simulation time 115800080 ps
CPU time 0.99 seconds
Started Jul 24 07:08:25 PM PDT 24
Finished Jul 24 07:08:27 PM PDT 24
Peak memory 200480 kb
Host smart-d2ecfdf5-41b1-4b54-b7c5-062dd1b6dfbb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378055437 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.clkmgr_lc_ctrl_intersig_mubi.378055437
Directory /workspace/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_peri.3044832487
Short name T504
Test name
Test status
Simulation time 25488533 ps
CPU time 0.75 seconds
Started Jul 24 07:08:31 PM PDT 24
Finished Jul 24 07:08:33 PM PDT 24
Peak memory 200460 kb
Host smart-d63cbbbd-9a2a-40ca-a55a-aa413fdd15c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044832487 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.3044832487
Directory /workspace/13.clkmgr_peri/latest

Test location /workspace/coverage/default/13.clkmgr_regwen.3491677973
Short name T340
Test name
Test status
Simulation time 1288679473 ps
CPU time 4.78 seconds
Started Jul 24 07:08:26 PM PDT 24
Finished Jul 24 07:08:32 PM PDT 24
Peak memory 200588 kb
Host smart-775d04b7-c00c-486f-a8d8-82eab1887b6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491677973 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.3491677973
Directory /workspace/13.clkmgr_regwen/latest

Test location /workspace/coverage/default/13.clkmgr_smoke.1866575589
Short name T796
Test name
Test status
Simulation time 37862588 ps
CPU time 0.89 seconds
Started Jul 24 07:08:27 PM PDT 24
Finished Jul 24 07:08:29 PM PDT 24
Peak memory 200432 kb
Host smart-f62ac55e-37d2-4759-a92b-eb8f26bdf193
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866575589 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.1866575589
Directory /workspace/13.clkmgr_smoke/latest

Test location /workspace/coverage/default/13.clkmgr_stress_all.1489049357
Short name T276
Test name
Test status
Simulation time 92072196 ps
CPU time 1.03 seconds
Started Jul 24 07:08:29 PM PDT 24
Finished Jul 24 07:08:30 PM PDT 24
Peak memory 200480 kb
Host smart-97aff460-4189-4809-ad82-cb7a8d5206fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489049357 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_stress_all.1489049357
Directory /workspace/13.clkmgr_stress_all/latest

Test location /workspace/coverage/default/13.clkmgr_trans.2429469070
Short name T244
Test name
Test status
Simulation time 55485732 ps
CPU time 0.99 seconds
Started Jul 24 07:08:23 PM PDT 24
Finished Jul 24 07:08:24 PM PDT 24
Peak memory 200468 kb
Host smart-a182e558-7aca-4712-82df-5132e3e2f9b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429469070 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.2429469070
Directory /workspace/13.clkmgr_trans/latest

Test location /workspace/coverage/default/14.clkmgr_alert_test.698716130
Short name T200
Test name
Test status
Simulation time 14806553 ps
CPU time 0.77 seconds
Started Jul 24 07:08:29 PM PDT 24
Finished Jul 24 07:08:30 PM PDT 24
Peak memory 200748 kb
Host smart-1395d76e-75e1-4565-b843-0b66fab8c596
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698716130 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkm
gr_alert_test.698716130
Directory /workspace/14.clkmgr_alert_test/latest

Test location /workspace/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.4089603119
Short name T476
Test name
Test status
Simulation time 98330477 ps
CPU time 1.18 seconds
Started Jul 24 07:08:31 PM PDT 24
Finished Jul 24 07:08:32 PM PDT 24
Peak memory 200504 kb
Host smart-71201571-654c-4523-acd8-631b8760d7fa
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089603119 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_clk_handshake_intersig_mubi.4089603119
Directory /workspace/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_clk_status.813690630
Short name T725
Test name
Test status
Simulation time 23045737 ps
CPU time 0.74 seconds
Started Jul 24 07:08:32 PM PDT 24
Finished Jul 24 07:08:33 PM PDT 24
Peak memory 199696 kb
Host smart-fda376bb-d633-4289-99c3-4af1c40da58e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813690630 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.813690630
Directory /workspace/14.clkmgr_clk_status/latest

Test location /workspace/coverage/default/14.clkmgr_div_intersig_mubi.2652658586
Short name T809
Test name
Test status
Simulation time 43151811 ps
CPU time 0.83 seconds
Started Jul 24 07:08:35 PM PDT 24
Finished Jul 24 07:08:36 PM PDT 24
Peak memory 200468 kb
Host smart-3801e073-e320-4293-b12c-9f7d101b7b65
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652658586 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_div_intersig_mubi.2652658586
Directory /workspace/14.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_extclk.2502463725
Short name T215
Test name
Test status
Simulation time 158205374 ps
CPU time 1.24 seconds
Started Jul 24 07:08:22 PM PDT 24
Finished Jul 24 07:08:23 PM PDT 24
Peak memory 200696 kb
Host smart-da22edcb-cca4-4b0a-9221-4546e11df783
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502463725 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.2502463725
Directory /workspace/14.clkmgr_extclk/latest

Test location /workspace/coverage/default/14.clkmgr_frequency.2432019864
Short name T374
Test name
Test status
Simulation time 239402857 ps
CPU time 1.83 seconds
Started Jul 24 07:08:30 PM PDT 24
Finished Jul 24 07:08:32 PM PDT 24
Peak memory 200472 kb
Host smart-1cf0b13f-91cc-47f2-a069-de288b887087
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432019864 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.2432019864
Directory /workspace/14.clkmgr_frequency/latest

Test location /workspace/coverage/default/14.clkmgr_frequency_timeout.536824580
Short name T410
Test name
Test status
Simulation time 2180885429 ps
CPU time 11.03 seconds
Started Jul 24 07:08:26 PM PDT 24
Finished Jul 24 07:08:37 PM PDT 24
Peak memory 200732 kb
Host smart-50ffc24b-b8db-44c5-a0dd-99a7eb7b8bae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536824580 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_ti
meout.536824580
Directory /workspace/14.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/14.clkmgr_idle_intersig_mubi.3197174805
Short name T656
Test name
Test status
Simulation time 59497483 ps
CPU time 0.98 seconds
Started Jul 24 07:08:28 PM PDT 24
Finished Jul 24 07:08:29 PM PDT 24
Peak memory 200428 kb
Host smart-f8abe63e-e8dd-4a1a-8d2c-0594c6d74f0a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197174805 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_idle_intersig_mubi.3197174805
Directory /workspace/14.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.3199906434
Short name T540
Test name
Test status
Simulation time 18517972 ps
CPU time 0.79 seconds
Started Jul 24 07:08:31 PM PDT 24
Finished Jul 24 07:08:32 PM PDT 24
Peak memory 200496 kb
Host smart-0f72c411-b1ec-44c7-b974-cb03a66fc0d3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199906434 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.clkmgr_lc_clk_byp_req_intersig_mubi.3199906434
Directory /workspace/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.904139651
Short name T339
Test name
Test status
Simulation time 57051421 ps
CPU time 0.99 seconds
Started Jul 24 07:08:35 PM PDT 24
Finished Jul 24 07:08:36 PM PDT 24
Peak memory 200472 kb
Host smart-6f5f4970-272a-4a01-99c9-799371b0891d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904139651 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.clkmgr_lc_ctrl_intersig_mubi.904139651
Directory /workspace/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_peri.2830202926
Short name T67
Test name
Test status
Simulation time 28945509 ps
CPU time 0.74 seconds
Started Jul 24 07:08:25 PM PDT 24
Finished Jul 24 07:08:26 PM PDT 24
Peak memory 200432 kb
Host smart-9d12ba9d-e888-42af-884a-387b36da19f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830202926 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.2830202926
Directory /workspace/14.clkmgr_peri/latest

Test location /workspace/coverage/default/14.clkmgr_regwen.1828831047
Short name T739
Test name
Test status
Simulation time 904771978 ps
CPU time 3.38 seconds
Started Jul 24 07:08:33 PM PDT 24
Finished Jul 24 07:08:37 PM PDT 24
Peak memory 200640 kb
Host smart-e8e995c8-a885-4b4e-8860-e36780ee2a56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828831047 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.1828831047
Directory /workspace/14.clkmgr_regwen/latest

Test location /workspace/coverage/default/14.clkmgr_smoke.2665274798
Short name T676
Test name
Test status
Simulation time 37186797 ps
CPU time 0.9 seconds
Started Jul 24 07:08:26 PM PDT 24
Finished Jul 24 07:08:27 PM PDT 24
Peak memory 200420 kb
Host smart-aa2a4ebc-3318-40e9-9acd-e3c08e0b495d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665274798 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.2665274798
Directory /workspace/14.clkmgr_smoke/latest

Test location /workspace/coverage/default/14.clkmgr_stress_all.1449054933
Short name T295
Test name
Test status
Simulation time 1883201984 ps
CPU time 8.05 seconds
Started Jul 24 07:08:31 PM PDT 24
Finished Jul 24 07:08:39 PM PDT 24
Peak memory 200708 kb
Host smart-b675ad36-31dc-41e7-a596-1af75f439668
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449054933 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_stress_all.1449054933
Directory /workspace/14.clkmgr_stress_all/latest

Test location /workspace/coverage/default/14.clkmgr_trans.2704015399
Short name T712
Test name
Test status
Simulation time 306767679 ps
CPU time 1.68 seconds
Started Jul 24 07:08:28 PM PDT 24
Finished Jul 24 07:08:30 PM PDT 24
Peak memory 200480 kb
Host smart-8c148e49-8d5b-46d9-8b9e-d0bce3876f12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704015399 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.2704015399
Directory /workspace/14.clkmgr_trans/latest

Test location /workspace/coverage/default/15.clkmgr_alert_test.1106650519
Short name T491
Test name
Test status
Simulation time 15575612 ps
CPU time 0.75 seconds
Started Jul 24 07:08:45 PM PDT 24
Finished Jul 24 07:08:46 PM PDT 24
Peak memory 200544 kb
Host smart-d2f7be85-6e8c-415c-8e8f-39a6f6f6bbc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106650519 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clk
mgr_alert_test.1106650519
Directory /workspace/15.clkmgr_alert_test/latest

Test location /workspace/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.640580363
Short name T92
Test name
Test status
Simulation time 27622197 ps
CPU time 0.94 seconds
Started Jul 24 07:08:34 PM PDT 24
Finished Jul 24 07:08:35 PM PDT 24
Peak memory 200400 kb
Host smart-36ce6843-0a4b-4d6a-a27b-5517b077a886
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640580363 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_clk_handshake_intersig_mubi.640580363
Directory /workspace/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_clk_status.3108450892
Short name T313
Test name
Test status
Simulation time 13332013 ps
CPU time 0.72 seconds
Started Jul 24 07:08:29 PM PDT 24
Finished Jul 24 07:08:30 PM PDT 24
Peak memory 199676 kb
Host smart-f5d130f1-4822-4c04-ae8e-33c32bee1b67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108450892 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.3108450892
Directory /workspace/15.clkmgr_clk_status/latest

Test location /workspace/coverage/default/15.clkmgr_div_intersig_mubi.125740426
Short name T803
Test name
Test status
Simulation time 39842780 ps
CPU time 0.79 seconds
Started Jul 24 07:08:38 PM PDT 24
Finished Jul 24 07:08:39 PM PDT 24
Peak memory 200472 kb
Host smart-03e274e1-4dd1-46a3-8918-32eab18ea502
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125740426 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.clkmgr_div_intersig_mubi.125740426
Directory /workspace/15.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_extclk.2592482333
Short name T79
Test name
Test status
Simulation time 33850813 ps
CPU time 0.85 seconds
Started Jul 24 07:08:31 PM PDT 24
Finished Jul 24 07:08:32 PM PDT 24
Peak memory 200408 kb
Host smart-3852de64-3ec0-4c5a-8cfd-30f262563b27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592482333 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.2592482333
Directory /workspace/15.clkmgr_extclk/latest

Test location /workspace/coverage/default/15.clkmgr_frequency.1333198714
Short name T408
Test name
Test status
Simulation time 1876145896 ps
CPU time 14.27 seconds
Started Jul 24 07:08:33 PM PDT 24
Finished Jul 24 07:08:47 PM PDT 24
Peak memory 200652 kb
Host smart-fe3e9565-0f01-4ea7-b527-ee76f9106738
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333198714 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.1333198714
Directory /workspace/15.clkmgr_frequency/latest

Test location /workspace/coverage/default/15.clkmgr_frequency_timeout.3930425994
Short name T762
Test name
Test status
Simulation time 1337293323 ps
CPU time 10.02 seconds
Started Jul 24 07:08:41 PM PDT 24
Finished Jul 24 07:08:51 PM PDT 24
Peak memory 200520 kb
Host smart-c1eae2e9-54fd-4be7-80a1-964b25c95837
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930425994 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_t
imeout.3930425994
Directory /workspace/15.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/15.clkmgr_idle_intersig_mubi.2172040196
Short name T639
Test name
Test status
Simulation time 93593322 ps
CPU time 1.16 seconds
Started Jul 24 07:08:36 PM PDT 24
Finished Jul 24 07:08:38 PM PDT 24
Peak memory 200412 kb
Host smart-2c3d69a0-045c-407f-a604-76f544f3b019
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172040196 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_idle_intersig_mubi.2172040196
Directory /workspace/15.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.3635959941
Short name T442
Test name
Test status
Simulation time 52788727 ps
CPU time 0.89 seconds
Started Jul 24 07:08:37 PM PDT 24
Finished Jul 24 07:08:38 PM PDT 24
Peak memory 200484 kb
Host smart-e973283b-2ba1-4dac-a827-faa6ff7ae671
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635959941 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.clkmgr_lc_clk_byp_req_intersig_mubi.3635959941
Directory /workspace/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.1486363247
Short name T416
Test name
Test status
Simulation time 29540028 ps
CPU time 0.86 seconds
Started Jul 24 07:08:35 PM PDT 24
Finished Jul 24 07:08:36 PM PDT 24
Peak memory 200520 kb
Host smart-bb8ad4eb-abc8-4b9a-9171-881ddeaed650
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486363247 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.clkmgr_lc_ctrl_intersig_mubi.1486363247
Directory /workspace/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_peri.649071076
Short name T682
Test name
Test status
Simulation time 14688668 ps
CPU time 0.79 seconds
Started Jul 24 07:08:28 PM PDT 24
Finished Jul 24 07:08:29 PM PDT 24
Peak memory 200444 kb
Host smart-704aa671-b88b-4484-8ca7-c72b1287a993
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649071076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.649071076
Directory /workspace/15.clkmgr_peri/latest

Test location /workspace/coverage/default/15.clkmgr_regwen.3007682352
Short name T483
Test name
Test status
Simulation time 1160617874 ps
CPU time 4.48 seconds
Started Jul 24 07:08:32 PM PDT 24
Finished Jul 24 07:08:37 PM PDT 24
Peak memory 200728 kb
Host smart-7c559edd-8898-4dcc-9e27-3887eaa3bdfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007682352 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.3007682352
Directory /workspace/15.clkmgr_regwen/latest

Test location /workspace/coverage/default/15.clkmgr_smoke.748652671
Short name T439
Test name
Test status
Simulation time 21237391 ps
CPU time 0.87 seconds
Started Jul 24 07:08:34 PM PDT 24
Finished Jul 24 07:08:35 PM PDT 24
Peak memory 200424 kb
Host smart-db6bf62f-c0b9-488a-b6c4-3332614a5879
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748652671 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.748652671
Directory /workspace/15.clkmgr_smoke/latest

Test location /workspace/coverage/default/15.clkmgr_stress_all.3225507588
Short name T668
Test name
Test status
Simulation time 4022204315 ps
CPU time 30.52 seconds
Started Jul 24 07:08:47 PM PDT 24
Finished Jul 24 07:09:18 PM PDT 24
Peak memory 200784 kb
Host smart-22e06ba8-a718-4ecb-91cf-896ad3979a53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225507588 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_stress_all.3225507588
Directory /workspace/15.clkmgr_stress_all/latest

Test location /workspace/coverage/default/15.clkmgr_trans.3893586153
Short name T526
Test name
Test status
Simulation time 86801648 ps
CPU time 1.1 seconds
Started Jul 24 07:08:32 PM PDT 24
Finished Jul 24 07:08:34 PM PDT 24
Peak memory 200372 kb
Host smart-df2494b7-6056-4385-87b6-e3f3a4d105b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893586153 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.3893586153
Directory /workspace/15.clkmgr_trans/latest

Test location /workspace/coverage/default/16.clkmgr_alert_test.1195863363
Short name T631
Test name
Test status
Simulation time 101707426 ps
CPU time 1.07 seconds
Started Jul 24 07:08:33 PM PDT 24
Finished Jul 24 07:08:34 PM PDT 24
Peak memory 200512 kb
Host smart-10010a64-1609-4976-85eb-9de48be8632d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195863363 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clk
mgr_alert_test.1195863363
Directory /workspace/16.clkmgr_alert_test/latest

Test location /workspace/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.659182147
Short name T767
Test name
Test status
Simulation time 36156015 ps
CPU time 0.81 seconds
Started Jul 24 07:08:40 PM PDT 24
Finished Jul 24 07:08:41 PM PDT 24
Peak memory 200496 kb
Host smart-4cc64254-8aa8-4c29-b92f-fc004f25f621
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659182147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_clk_handshake_intersig_mubi.659182147
Directory /workspace/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_clk_status.2715356883
Short name T671
Test name
Test status
Simulation time 16879742 ps
CPU time 0.74 seconds
Started Jul 24 07:08:40 PM PDT 24
Finished Jul 24 07:08:41 PM PDT 24
Peak memory 199704 kb
Host smart-0440f731-724a-4bc0-9899-c0fc9f718039
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715356883 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.2715356883
Directory /workspace/16.clkmgr_clk_status/latest

Test location /workspace/coverage/default/16.clkmgr_div_intersig_mubi.3455539988
Short name T618
Test name
Test status
Simulation time 81139943 ps
CPU time 1.09 seconds
Started Jul 24 07:08:36 PM PDT 24
Finished Jul 24 07:08:37 PM PDT 24
Peak memory 200484 kb
Host smart-1824bada-11bc-4c53-a8e7-01720d28253a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455539988 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_div_intersig_mubi.3455539988
Directory /workspace/16.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_extclk.2993053839
Short name T287
Test name
Test status
Simulation time 14808460 ps
CPU time 0.81 seconds
Started Jul 24 07:08:42 PM PDT 24
Finished Jul 24 07:08:42 PM PDT 24
Peak memory 200440 kb
Host smart-d88dd750-7042-4332-8999-7e02d5502bd4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993053839 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.2993053839
Directory /workspace/16.clkmgr_extclk/latest

Test location /workspace/coverage/default/16.clkmgr_frequency.3800386104
Short name T230
Test name
Test status
Simulation time 434454704 ps
CPU time 4.17 seconds
Started Jul 24 07:08:44 PM PDT 24
Finished Jul 24 07:08:49 PM PDT 24
Peak memory 200468 kb
Host smart-6e15937f-23b7-41d3-ad55-a55f673533a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800386104 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.3800386104
Directory /workspace/16.clkmgr_frequency/latest

Test location /workspace/coverage/default/16.clkmgr_frequency_timeout.1108819212
Short name T541
Test name
Test status
Simulation time 981235158 ps
CPU time 7.28 seconds
Started Jul 24 07:08:33 PM PDT 24
Finished Jul 24 07:08:41 PM PDT 24
Peak memory 200580 kb
Host smart-2f1b4e59-6e47-44c8-8a08-e6cb0a25a12a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108819212 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_t
imeout.1108819212
Directory /workspace/16.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/16.clkmgr_idle_intersig_mubi.2667243833
Short name T473
Test name
Test status
Simulation time 62122126 ps
CPU time 0.97 seconds
Started Jul 24 07:08:47 PM PDT 24
Finished Jul 24 07:08:48 PM PDT 24
Peak memory 200444 kb
Host smart-bbc45205-64b8-44b8-ac56-9b8517fc555b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667243833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_idle_intersig_mubi.2667243833
Directory /workspace/16.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.1853224224
Short name T713
Test name
Test status
Simulation time 69620408 ps
CPU time 1.06 seconds
Started Jul 24 07:08:35 PM PDT 24
Finished Jul 24 07:08:37 PM PDT 24
Peak memory 200460 kb
Host smart-5f063bd4-0d8c-4cac-99cc-747759605a6d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853224224 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.clkmgr_lc_clk_byp_req_intersig_mubi.1853224224
Directory /workspace/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.1058076056
Short name T253
Test name
Test status
Simulation time 22076864 ps
CPU time 0.84 seconds
Started Jul 24 07:08:50 PM PDT 24
Finished Jul 24 07:08:51 PM PDT 24
Peak memory 200476 kb
Host smart-eac9b29c-413b-468c-ba99-cfc29c01f17a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058076056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.clkmgr_lc_ctrl_intersig_mubi.1058076056
Directory /workspace/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_peri.618592324
Short name T603
Test name
Test status
Simulation time 14707263 ps
CPU time 0.78 seconds
Started Jul 24 07:08:37 PM PDT 24
Finished Jul 24 07:08:38 PM PDT 24
Peak memory 200444 kb
Host smart-e1ad1603-9c91-44f3-b1bb-266d8085d636
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618592324 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.618592324
Directory /workspace/16.clkmgr_peri/latest

Test location /workspace/coverage/default/16.clkmgr_smoke.2393272377
Short name T78
Test name
Test status
Simulation time 93802755 ps
CPU time 1.03 seconds
Started Jul 24 07:08:55 PM PDT 24
Finished Jul 24 07:09:01 PM PDT 24
Peak memory 200436 kb
Host smart-5291264f-348d-4eb4-b017-ec47e46102a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393272377 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.2393272377
Directory /workspace/16.clkmgr_smoke/latest

Test location /workspace/coverage/default/16.clkmgr_stress_all.1481898788
Short name T354
Test name
Test status
Simulation time 7200217557 ps
CPU time 36.63 seconds
Started Jul 24 07:08:45 PM PDT 24
Finished Jul 24 07:09:22 PM PDT 24
Peak memory 200776 kb
Host smart-2a819863-a8c6-4fcd-aa15-c935abc0f46f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481898788 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_stress_all.1481898788
Directory /workspace/16.clkmgr_stress_all/latest

Test location /workspace/coverage/default/16.clkmgr_stress_all_with_rand_reset.3470698999
Short name T153
Test name
Test status
Simulation time 78192701345 ps
CPU time 404.87 seconds
Started Jul 24 07:08:38 PM PDT 24
Finished Jul 24 07:15:23 PM PDT 24
Peak memory 210608 kb
Host smart-d8489659-2ea1-4942-b157-d7ddf40fd95a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3470698999 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all_with_rand_reset.3470698999
Directory /workspace/16.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.clkmgr_trans.1948491999
Short name T182
Test name
Test status
Simulation time 17498980 ps
CPU time 0.75 seconds
Started Jul 24 07:08:37 PM PDT 24
Finished Jul 24 07:08:38 PM PDT 24
Peak memory 200484 kb
Host smart-3a9e7522-c931-4c02-9fa2-d9bb326f5ea0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948491999 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.1948491999
Directory /workspace/16.clkmgr_trans/latest

Test location /workspace/coverage/default/17.clkmgr_alert_test.2118181239
Short name T286
Test name
Test status
Simulation time 47507396 ps
CPU time 0.94 seconds
Started Jul 24 07:08:40 PM PDT 24
Finished Jul 24 07:08:41 PM PDT 24
Peak memory 200528 kb
Host smart-e6bcee1e-4063-496b-ba63-2a8bcd06b585
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118181239 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clk
mgr_alert_test.2118181239
Directory /workspace/17.clkmgr_alert_test/latest

Test location /workspace/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.1609349375
Short name T814
Test name
Test status
Simulation time 23760008 ps
CPU time 0.97 seconds
Started Jul 24 07:08:40 PM PDT 24
Finished Jul 24 07:08:41 PM PDT 24
Peak memory 200500 kb
Host smart-5ccb7627-5d9f-41b5-ac9e-529c0703bf28
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609349375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_clk_handshake_intersig_mubi.1609349375
Directory /workspace/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_clk_status.212801130
Short name T293
Test name
Test status
Simulation time 11056814 ps
CPU time 0.7 seconds
Started Jul 24 07:08:36 PM PDT 24
Finished Jul 24 07:08:37 PM PDT 24
Peak memory 200404 kb
Host smart-da4e04e4-6718-4e93-8bb1-4b931d6a454b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212801130 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.212801130
Directory /workspace/17.clkmgr_clk_status/latest

Test location /workspace/coverage/default/17.clkmgr_div_intersig_mubi.1005746726
Short name T306
Test name
Test status
Simulation time 73201112 ps
CPU time 1.03 seconds
Started Jul 24 07:08:40 PM PDT 24
Finished Jul 24 07:08:42 PM PDT 24
Peak memory 200436 kb
Host smart-13a30bea-14e7-41fd-9b0a-4335ce0d352d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005746726 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_div_intersig_mubi.1005746726
Directory /workspace/17.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_extclk.4147546499
Short name T328
Test name
Test status
Simulation time 23250817 ps
CPU time 0.85 seconds
Started Jul 24 07:08:32 PM PDT 24
Finished Jul 24 07:08:34 PM PDT 24
Peak memory 200488 kb
Host smart-f8c5dcbf-0e0b-44b3-bfc9-88a532ddb6d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147546499 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.4147546499
Directory /workspace/17.clkmgr_extclk/latest

Test location /workspace/coverage/default/17.clkmgr_frequency.669476742
Short name T13
Test name
Test status
Simulation time 1227353050 ps
CPU time 6.03 seconds
Started Jul 24 07:08:37 PM PDT 24
Finished Jul 24 07:08:43 PM PDT 24
Peak memory 200468 kb
Host smart-c9d2dc89-fe5c-46c1-b008-f155fae67ba3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669476742 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.669476742
Directory /workspace/17.clkmgr_frequency/latest

Test location /workspace/coverage/default/17.clkmgr_frequency_timeout.879488606
Short name T481
Test name
Test status
Simulation time 735644020 ps
CPU time 5.59 seconds
Started Jul 24 07:08:47 PM PDT 24
Finished Jul 24 07:08:53 PM PDT 24
Peak memory 200524 kb
Host smart-1a9d72c9-67f9-456a-bafb-ef4154e3d4fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879488606 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_ti
meout.879488606
Directory /workspace/17.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/17.clkmgr_idle_intersig_mubi.2447383280
Short name T169
Test name
Test status
Simulation time 66787531 ps
CPU time 0.95 seconds
Started Jul 24 07:08:55 PM PDT 24
Finished Jul 24 07:08:56 PM PDT 24
Peak memory 200480 kb
Host smart-715c06e5-ca13-474d-be04-298d6c17bdef
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447383280 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_idle_intersig_mubi.2447383280
Directory /workspace/17.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.1989173406
Short name T5
Test name
Test status
Simulation time 43991441 ps
CPU time 0.82 seconds
Started Jul 24 07:08:37 PM PDT 24
Finished Jul 24 07:08:38 PM PDT 24
Peak memory 200448 kb
Host smart-1346b038-dba1-48bf-b234-3f2f4258751c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989173406 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.clkmgr_lc_clk_byp_req_intersig_mubi.1989173406
Directory /workspace/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.1225755876
Short name T307
Test name
Test status
Simulation time 42955150 ps
CPU time 0.94 seconds
Started Jul 24 07:08:44 PM PDT 24
Finished Jul 24 07:08:45 PM PDT 24
Peak memory 200464 kb
Host smart-c1af99af-1f26-4f3d-97a6-40c3aceaab9d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225755876 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.clkmgr_lc_ctrl_intersig_mubi.1225755876
Directory /workspace/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_peri.3498369956
Short name T52
Test name
Test status
Simulation time 13961953 ps
CPU time 0.74 seconds
Started Jul 24 07:08:45 PM PDT 24
Finished Jul 24 07:08:46 PM PDT 24
Peak memory 200464 kb
Host smart-afff2065-84c6-42a6-957d-dff9e981894e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498369956 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.3498369956
Directory /workspace/17.clkmgr_peri/latest

Test location /workspace/coverage/default/17.clkmgr_regwen.46714857
Short name T711
Test name
Test status
Simulation time 1291730468 ps
CPU time 4.81 seconds
Started Jul 24 07:08:45 PM PDT 24
Finished Jul 24 07:08:50 PM PDT 24
Peak memory 200640 kb
Host smart-9bdcd8bd-7a09-41ad-aa37-b2cc39ac42ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46714857 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.46714857
Directory /workspace/17.clkmgr_regwen/latest

Test location /workspace/coverage/default/17.clkmgr_smoke.2314630869
Short name T750
Test name
Test status
Simulation time 21770256 ps
CPU time 0.92 seconds
Started Jul 24 07:08:37 PM PDT 24
Finished Jul 24 07:08:39 PM PDT 24
Peak memory 200408 kb
Host smart-1d03a7cc-5983-438e-924b-15afe00ac4ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314630869 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.2314630869
Directory /workspace/17.clkmgr_smoke/latest

Test location /workspace/coverage/default/17.clkmgr_stress_all.1939210815
Short name T565
Test name
Test status
Simulation time 5705192234 ps
CPU time 24.71 seconds
Started Jul 24 07:09:24 PM PDT 24
Finished Jul 24 07:09:48 PM PDT 24
Peak memory 200736 kb
Host smart-51d441c3-9070-4269-8d50-0540c9f2b053
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939210815 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_stress_all.1939210815
Directory /workspace/17.clkmgr_stress_all/latest

Test location /workspace/coverage/default/17.clkmgr_stress_all_with_rand_reset.3759598490
Short name T72
Test name
Test status
Simulation time 27198505067 ps
CPU time 288.51 seconds
Started Jul 24 07:08:37 PM PDT 24
Finished Jul 24 07:13:26 PM PDT 24
Peak memory 209132 kb
Host smart-53c67d02-bef0-4e89-9d1e-56b72e9dd754
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3759598490 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all_with_rand_reset.3759598490
Directory /workspace/17.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.clkmgr_trans.2246998344
Short name T534
Test name
Test status
Simulation time 33228716 ps
CPU time 0.87 seconds
Started Jul 24 07:08:32 PM PDT 24
Finished Jul 24 07:08:33 PM PDT 24
Peak memory 200400 kb
Host smart-a30bede6-9671-44c5-982f-0cbe10869e6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246998344 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.2246998344
Directory /workspace/17.clkmgr_trans/latest

Test location /workspace/coverage/default/18.clkmgr_alert_test.3464562555
Short name T265
Test name
Test status
Simulation time 57053616 ps
CPU time 0.92 seconds
Started Jul 24 07:08:46 PM PDT 24
Finished Jul 24 07:08:47 PM PDT 24
Peak memory 200544 kb
Host smart-e83bae95-ef67-44b7-b527-8394e70425bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464562555 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clk
mgr_alert_test.3464562555
Directory /workspace/18.clkmgr_alert_test/latest

Test location /workspace/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.1467703200
Short name T80
Test name
Test status
Simulation time 19040798 ps
CPU time 0.83 seconds
Started Jul 24 07:08:40 PM PDT 24
Finished Jul 24 07:08:41 PM PDT 24
Peak memory 200476 kb
Host smart-7ffed960-cbcc-4fb1-9607-920555ae444a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467703200 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_clk_handshake_intersig_mubi.1467703200
Directory /workspace/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_clk_status.295049562
Short name T160
Test name
Test status
Simulation time 37591061 ps
CPU time 0.75 seconds
Started Jul 24 07:08:33 PM PDT 24
Finished Jul 24 07:08:34 PM PDT 24
Peak memory 200448 kb
Host smart-576df154-5ccd-46ec-afa0-9f5fdb2db7a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295049562 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.295049562
Directory /workspace/18.clkmgr_clk_status/latest

Test location /workspace/coverage/default/18.clkmgr_div_intersig_mubi.1772895598
Short name T513
Test name
Test status
Simulation time 241668220 ps
CPU time 1.48 seconds
Started Jul 24 07:08:38 PM PDT 24
Finished Jul 24 07:08:39 PM PDT 24
Peak memory 200488 kb
Host smart-37ca1e00-07e8-4244-b4a3-148a98499631
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772895598 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_div_intersig_mubi.1772895598
Directory /workspace/18.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_extclk.1083353516
Short name T323
Test name
Test status
Simulation time 24847198 ps
CPU time 0.91 seconds
Started Jul 24 07:08:40 PM PDT 24
Finished Jul 24 07:08:41 PM PDT 24
Peak memory 200460 kb
Host smart-e95724d8-c677-4d08-930f-90ecba12efb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083353516 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.1083353516
Directory /workspace/18.clkmgr_extclk/latest

Test location /workspace/coverage/default/18.clkmgr_frequency.1677191900
Short name T198
Test name
Test status
Simulation time 255112006 ps
CPU time 1.54 seconds
Started Jul 24 07:08:47 PM PDT 24
Finished Jul 24 07:08:48 PM PDT 24
Peak memory 200484 kb
Host smart-7f282816-be2a-4c39-b67e-3de5acc3d42e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677191900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.1677191900
Directory /workspace/18.clkmgr_frequency/latest

Test location /workspace/coverage/default/18.clkmgr_frequency_timeout.1018239880
Short name T485
Test name
Test status
Simulation time 499126360 ps
CPU time 4.38 seconds
Started Jul 24 07:08:40 PM PDT 24
Finished Jul 24 07:08:44 PM PDT 24
Peak memory 200560 kb
Host smart-bf5d66a8-3d07-43f3-b3b3-34755a58e9f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018239880 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_t
imeout.1018239880
Directory /workspace/18.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/18.clkmgr_idle_intersig_mubi.3340152441
Short name T389
Test name
Test status
Simulation time 85194416 ps
CPU time 1.15 seconds
Started Jul 24 07:08:41 PM PDT 24
Finished Jul 24 07:08:42 PM PDT 24
Peak memory 200476 kb
Host smart-422fc3ec-ca25-46e6-bd3e-1a600166223a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340152441 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_idle_intersig_mubi.3340152441
Directory /workspace/18.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.3755994487
Short name T444
Test name
Test status
Simulation time 19279637 ps
CPU time 0.75 seconds
Started Jul 24 07:08:45 PM PDT 24
Finished Jul 24 07:08:46 PM PDT 24
Peak memory 200464 kb
Host smart-bdb5fc57-f018-4bf7-942d-cbbd6453c4d5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755994487 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_clk_byp_req_intersig_mubi.3755994487
Directory /workspace/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.2426128437
Short name T537
Test name
Test status
Simulation time 29595265 ps
CPU time 0.92 seconds
Started Jul 24 07:08:42 PM PDT 24
Finished Jul 24 07:08:43 PM PDT 24
Peak memory 200508 kb
Host smart-960406d0-66d7-4947-90ad-da179f37b34d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426128437 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_ctrl_intersig_mubi.2426128437
Directory /workspace/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_peri.2615234753
Short name T337
Test name
Test status
Simulation time 16554045 ps
CPU time 0.77 seconds
Started Jul 24 07:08:40 PM PDT 24
Finished Jul 24 07:08:41 PM PDT 24
Peak memory 200488 kb
Host smart-3774819e-f4f3-45d0-8ed2-61e80cfc2d57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615234753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.2615234753
Directory /workspace/18.clkmgr_peri/latest

Test location /workspace/coverage/default/18.clkmgr_regwen.996074617
Short name T718
Test name
Test status
Simulation time 616729501 ps
CPU time 3.73 seconds
Started Jul 24 07:08:35 PM PDT 24
Finished Jul 24 07:08:39 PM PDT 24
Peak memory 200596 kb
Host smart-d4027b9f-8d72-4200-a2c2-c6c8fb313546
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996074617 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.996074617
Directory /workspace/18.clkmgr_regwen/latest

Test location /workspace/coverage/default/18.clkmgr_smoke.1896618180
Short name T545
Test name
Test status
Simulation time 22977358 ps
CPU time 0.88 seconds
Started Jul 24 07:08:41 PM PDT 24
Finished Jul 24 07:08:42 PM PDT 24
Peak memory 200464 kb
Host smart-6dca65db-1913-4d50-a4f3-2dfedbb7c4c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896618180 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.1896618180
Directory /workspace/18.clkmgr_smoke/latest

Test location /workspace/coverage/default/18.clkmgr_stress_all.4120639419
Short name T445
Test name
Test status
Simulation time 6693805565 ps
CPU time 23.17 seconds
Started Jul 24 07:08:38 PM PDT 24
Finished Jul 24 07:09:01 PM PDT 24
Peak memory 200784 kb
Host smart-075e16d4-daa0-4210-a143-cecdd1d1e1dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120639419 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_stress_all.4120639419
Directory /workspace/18.clkmgr_stress_all/latest

Test location /workspace/coverage/default/18.clkmgr_trans.112407199
Short name T706
Test name
Test status
Simulation time 47627432 ps
CPU time 0.82 seconds
Started Jul 24 07:08:51 PM PDT 24
Finished Jul 24 07:08:52 PM PDT 24
Peak memory 200464 kb
Host smart-ca4e5dc4-ce44-4f6e-9286-1ee9dfa99c45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112407199 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.112407199
Directory /workspace/18.clkmgr_trans/latest

Test location /workspace/coverage/default/19.clkmgr_alert_test.2288026320
Short name T403
Test name
Test status
Simulation time 20736917 ps
CPU time 0.74 seconds
Started Jul 24 07:08:45 PM PDT 24
Finished Jul 24 07:08:46 PM PDT 24
Peak memory 200544 kb
Host smart-df8cf014-6ebd-48d4-924b-fa6a278862f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288026320 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clk
mgr_alert_test.2288026320
Directory /workspace/19.clkmgr_alert_test/latest

Test location /workspace/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.3481037744
Short name T797
Test name
Test status
Simulation time 14445340 ps
CPU time 0.75 seconds
Started Jul 24 07:08:31 PM PDT 24
Finished Jul 24 07:08:32 PM PDT 24
Peak memory 200472 kb
Host smart-b2a7cf9f-742a-4540-a121-8f5383485746
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481037744 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_clk_handshake_intersig_mubi.3481037744
Directory /workspace/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_clk_status.253121022
Short name T572
Test name
Test status
Simulation time 31147534 ps
CPU time 0.76 seconds
Started Jul 24 07:08:48 PM PDT 24
Finished Jul 24 07:08:49 PM PDT 24
Peak memory 200412 kb
Host smart-d6d8b1c7-8ffb-4efe-bd39-ccfd67f190c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253121022 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.253121022
Directory /workspace/19.clkmgr_clk_status/latest

Test location /workspace/coverage/default/19.clkmgr_div_intersig_mubi.222815454
Short name T367
Test name
Test status
Simulation time 74525847 ps
CPU time 0.97 seconds
Started Jul 24 07:08:46 PM PDT 24
Finished Jul 24 07:08:47 PM PDT 24
Peak memory 200500 kb
Host smart-cf201df9-663d-4190-9e50-10cd1fd6d48e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222815454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.clkmgr_div_intersig_mubi.222815454
Directory /workspace/19.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_extclk.2564368099
Short name T193
Test name
Test status
Simulation time 36826032 ps
CPU time 0.82 seconds
Started Jul 24 07:08:46 PM PDT 24
Finished Jul 24 07:08:47 PM PDT 24
Peak memory 200464 kb
Host smart-43d46a3c-fb85-4c3b-bc0d-bf63648a0ffa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564368099 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.2564368099
Directory /workspace/19.clkmgr_extclk/latest

Test location /workspace/coverage/default/19.clkmgr_frequency.1556733449
Short name T731
Test name
Test status
Simulation time 1906942582 ps
CPU time 8.62 seconds
Started Jul 24 07:08:39 PM PDT 24
Finished Jul 24 07:08:48 PM PDT 24
Peak memory 200652 kb
Host smart-bac74825-74a7-40d6-8ff7-952ecc359756
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556733449 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.1556733449
Directory /workspace/19.clkmgr_frequency/latest

Test location /workspace/coverage/default/19.clkmgr_frequency_timeout.3831628320
Short name T175
Test name
Test status
Simulation time 1228723307 ps
CPU time 6.65 seconds
Started Jul 24 07:08:38 PM PDT 24
Finished Jul 24 07:08:45 PM PDT 24
Peak memory 200528 kb
Host smart-2457d6ee-1759-43d2-9803-77579f5af5ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831628320 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_t
imeout.3831628320
Directory /workspace/19.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/19.clkmgr_idle_intersig_mubi.92807987
Short name T373
Test name
Test status
Simulation time 144336788 ps
CPU time 1.18 seconds
Started Jul 24 07:08:46 PM PDT 24
Finished Jul 24 07:08:47 PM PDT 24
Peak memory 200476 kb
Host smart-0f904a79-19fd-4112-82bf-9fd50c061e8a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92807987 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.clkmgr_idle_intersig_mubi.92807987
Directory /workspace/19.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.765607945
Short name T654
Test name
Test status
Simulation time 54320394 ps
CPU time 0.91 seconds
Started Jul 24 07:08:43 PM PDT 24
Finished Jul 24 07:08:44 PM PDT 24
Peak memory 200472 kb
Host smart-c5ac2637-a863-4778-8be3-5db852d55f36
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765607945 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.clkmgr_lc_clk_byp_req_intersig_mubi.765607945
Directory /workspace/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.1925787572
Short name T666
Test name
Test status
Simulation time 42040884 ps
CPU time 0.84 seconds
Started Jul 24 07:08:46 PM PDT 24
Finished Jul 24 07:08:47 PM PDT 24
Peak memory 200448 kb
Host smart-d24ff8be-7e2f-4cfb-a77e-b0c445feb2d5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925787572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.clkmgr_lc_ctrl_intersig_mubi.1925787572
Directory /workspace/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_peri.3537680387
Short name T655
Test name
Test status
Simulation time 18867700 ps
CPU time 0.8 seconds
Started Jul 24 07:08:32 PM PDT 24
Finished Jul 24 07:08:33 PM PDT 24
Peak memory 200492 kb
Host smart-8bb3d54c-c6e8-4158-abe4-495e5cebbba5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537680387 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.3537680387
Directory /workspace/19.clkmgr_peri/latest

Test location /workspace/coverage/default/19.clkmgr_regwen.3151288501
Short name T382
Test name
Test status
Simulation time 786467116 ps
CPU time 4.52 seconds
Started Jul 24 07:08:50 PM PDT 24
Finished Jul 24 07:08:55 PM PDT 24
Peak memory 200644 kb
Host smart-d7367cd7-f3da-4144-9851-d6014eb0e250
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151288501 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.3151288501
Directory /workspace/19.clkmgr_regwen/latest

Test location /workspace/coverage/default/19.clkmgr_smoke.808467278
Short name T114
Test name
Test status
Simulation time 50843281 ps
CPU time 0.9 seconds
Started Jul 24 07:08:37 PM PDT 24
Finished Jul 24 07:08:38 PM PDT 24
Peak memory 200492 kb
Host smart-2fef7808-aca5-4203-a0fb-b2b20c828482
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808467278 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.808467278
Directory /workspace/19.clkmgr_smoke/latest

Test location /workspace/coverage/default/19.clkmgr_stress_all.3280858687
Short name T38
Test name
Test status
Simulation time 8365853043 ps
CPU time 34.13 seconds
Started Jul 24 07:08:41 PM PDT 24
Finished Jul 24 07:09:16 PM PDT 24
Peak memory 200808 kb
Host smart-5cb11eaa-6ea0-4523-814f-c72a73ca1361
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280858687 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_stress_all.3280858687
Directory /workspace/19.clkmgr_stress_all/latest

Test location /workspace/coverage/default/19.clkmgr_trans.3940926013
Short name T658
Test name
Test status
Simulation time 68077189 ps
CPU time 0.92 seconds
Started Jul 24 07:08:33 PM PDT 24
Finished Jul 24 07:08:35 PM PDT 24
Peak memory 200444 kb
Host smart-e69b34a8-9d6e-4c27-aff0-f09dde38b28b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940926013 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.3940926013
Directory /workspace/19.clkmgr_trans/latest

Test location /workspace/coverage/default/2.clkmgr_alert_test.3882656413
Short name T402
Test name
Test status
Simulation time 63793650 ps
CPU time 0.98 seconds
Started Jul 24 07:08:00 PM PDT 24
Finished Jul 24 07:08:02 PM PDT 24
Peak memory 200556 kb
Host smart-5c784586-52cc-49aa-87a2-870e6fd50fdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882656413 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkm
gr_alert_test.3882656413
Directory /workspace/2.clkmgr_alert_test/latest

Test location /workspace/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.1314176666
Short name T538
Test name
Test status
Simulation time 64117196 ps
CPU time 0.97 seconds
Started Jul 24 07:07:55 PM PDT 24
Finished Jul 24 07:07:56 PM PDT 24
Peak memory 200484 kb
Host smart-11cfc7f5-901d-46d6-99aa-0a1bd0a5146f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314176666 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_clk_handshake_intersig_mubi.1314176666
Directory /workspace/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_clk_status.2706151660
Short name T289
Test name
Test status
Simulation time 27986567 ps
CPU time 0.74 seconds
Started Jul 24 07:07:59 PM PDT 24
Finished Jul 24 07:08:00 PM PDT 24
Peak memory 199668 kb
Host smart-cf912c0c-a041-41cb-9062-7720d49fb603
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706151660 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.2706151660
Directory /workspace/2.clkmgr_clk_status/latest

Test location /workspace/coverage/default/2.clkmgr_div_intersig_mubi.3473503309
Short name T771
Test name
Test status
Simulation time 56519595 ps
CPU time 0.96 seconds
Started Jul 24 07:08:01 PM PDT 24
Finished Jul 24 07:08:02 PM PDT 24
Peak memory 200440 kb
Host smart-a64be9fb-24fd-4efb-b799-834727d37852
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473503309 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_div_intersig_mubi.3473503309
Directory /workspace/2.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_extclk.1448615991
Short name T761
Test name
Test status
Simulation time 53502915 ps
CPU time 0.87 seconds
Started Jul 24 07:07:55 PM PDT 24
Finished Jul 24 07:07:56 PM PDT 24
Peak memory 200464 kb
Host smart-116df9d8-cdff-483e-83ab-f34437aaa538
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448615991 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.1448615991
Directory /workspace/2.clkmgr_extclk/latest

Test location /workspace/coverage/default/2.clkmgr_frequency.1335054672
Short name T34
Test name
Test status
Simulation time 2473964936 ps
CPU time 19.12 seconds
Started Jul 24 07:07:58 PM PDT 24
Finished Jul 24 07:08:18 PM PDT 24
Peak memory 200684 kb
Host smart-93f44b6e-d83d-4e20-9199-ce36bb1603af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335054672 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.1335054672
Directory /workspace/2.clkmgr_frequency/latest

Test location /workspace/coverage/default/2.clkmgr_frequency_timeout.791829937
Short name T409
Test name
Test status
Simulation time 859139867 ps
CPU time 6.6 seconds
Started Jul 24 07:07:55 PM PDT 24
Finished Jul 24 07:08:02 PM PDT 24
Peak memory 200556 kb
Host smart-715e815e-0d40-4bf3-b351-072411561ed5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791829937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_tim
eout.791829937
Directory /workspace/2.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/2.clkmgr_idle_intersig_mubi.2073485654
Short name T296
Test name
Test status
Simulation time 49169714 ps
CPU time 1 seconds
Started Jul 24 07:07:55 PM PDT 24
Finished Jul 24 07:07:56 PM PDT 24
Peak memory 200532 kb
Host smart-c673e846-7f85-4678-a9bf-1ddd46d925be
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073485654 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_idle_intersig_mubi.2073485654
Directory /workspace/2.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.486910796
Short name T240
Test name
Test status
Simulation time 37616108 ps
CPU time 0.8 seconds
Started Jul 24 07:07:59 PM PDT 24
Finished Jul 24 07:08:00 PM PDT 24
Peak memory 200492 kb
Host smart-477a1aa5-1aa2-4f05-9b10-ddf23dfd925e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486910796 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.clkmgr_lc_clk_byp_req_intersig_mubi.486910796
Directory /workspace/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.3433226391
Short name T637
Test name
Test status
Simulation time 143131276 ps
CPU time 1.19 seconds
Started Jul 24 07:07:55 PM PDT 24
Finished Jul 24 07:07:57 PM PDT 24
Peak memory 200464 kb
Host smart-591c190d-1fe6-42b3-bddf-b1b44761c6be
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433226391 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_lc_ctrl_intersig_mubi.3433226391
Directory /workspace/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_peri.1940961243
Short name T611
Test name
Test status
Simulation time 32207676 ps
CPU time 0.85 seconds
Started Jul 24 07:07:56 PM PDT 24
Finished Jul 24 07:07:57 PM PDT 24
Peak memory 200352 kb
Host smart-dbac0efd-90fe-4645-a6c6-c2dd5c8a95b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940961243 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.1940961243
Directory /workspace/2.clkmgr_peri/latest

Test location /workspace/coverage/default/2.clkmgr_regwen.4220616678
Short name T233
Test name
Test status
Simulation time 830902570 ps
CPU time 4.51 seconds
Started Jul 24 07:07:55 PM PDT 24
Finished Jul 24 07:08:00 PM PDT 24
Peak memory 200636 kb
Host smart-2c9e5553-b2c9-4894-a393-712f87b51f47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220616678 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.4220616678
Directory /workspace/2.clkmgr_regwen/latest

Test location /workspace/coverage/default/2.clkmgr_sec_cm.712051854
Short name T46
Test name
Test status
Simulation time 299106436 ps
CPU time 3.28 seconds
Started Jul 24 07:07:55 PM PDT 24
Finished Jul 24 07:07:59 PM PDT 24
Peak memory 217108 kb
Host smart-a3789af8-7427-468f-8474-9bb38061c17a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712051854 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr
_sec_cm.712051854
Directory /workspace/2.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/2.clkmgr_smoke.908937160
Short name T499
Test name
Test status
Simulation time 194308068 ps
CPU time 1.37 seconds
Started Jul 24 07:08:00 PM PDT 24
Finished Jul 24 07:08:01 PM PDT 24
Peak memory 200420 kb
Host smart-0e79e63c-aef9-49a7-b891-1a79700d8740
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908937160 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.908937160
Directory /workspace/2.clkmgr_smoke/latest

Test location /workspace/coverage/default/2.clkmgr_stress_all.4290566237
Short name T441
Test name
Test status
Simulation time 5686977022 ps
CPU time 42.69 seconds
Started Jul 24 07:07:58 PM PDT 24
Finished Jul 24 07:08:41 PM PDT 24
Peak memory 200728 kb
Host smart-53700a69-f35c-4f2f-bda0-5e86a28003a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290566237 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_stress_all.4290566237
Directory /workspace/2.clkmgr_stress_all/latest

Test location /workspace/coverage/default/2.clkmgr_trans.2113050148
Short name T651
Test name
Test status
Simulation time 26170018 ps
CPU time 0.89 seconds
Started Jul 24 07:07:59 PM PDT 24
Finished Jul 24 07:08:00 PM PDT 24
Peak memory 200428 kb
Host smart-8b34d46c-85d1-4fe0-a46c-4d75b9369a27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113050148 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.2113050148
Directory /workspace/2.clkmgr_trans/latest

Test location /workspace/coverage/default/20.clkmgr_alert_test.1562583069
Short name T686
Test name
Test status
Simulation time 119139875 ps
CPU time 1.05 seconds
Started Jul 24 07:08:45 PM PDT 24
Finished Jul 24 07:08:46 PM PDT 24
Peak memory 200584 kb
Host smart-ff7be7fe-7f5f-420f-8c4f-971a11f1e1f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562583069 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clk
mgr_alert_test.1562583069
Directory /workspace/20.clkmgr_alert_test/latest

Test location /workspace/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.2835903398
Short name T453
Test name
Test status
Simulation time 15934208 ps
CPU time 0.77 seconds
Started Jul 24 07:08:45 PM PDT 24
Finished Jul 24 07:08:46 PM PDT 24
Peak memory 200476 kb
Host smart-06d0e63c-d987-47eb-b98b-5a92c2e79444
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835903398 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_clk_handshake_intersig_mubi.2835903398
Directory /workspace/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_clk_status.3896565957
Short name T598
Test name
Test status
Simulation time 17749344 ps
CPU time 0.76 seconds
Started Jul 24 07:08:44 PM PDT 24
Finished Jul 24 07:08:45 PM PDT 24
Peak memory 200404 kb
Host smart-22aa0979-67dc-47b5-a2b2-f1da75150079
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896565957 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.3896565957
Directory /workspace/20.clkmgr_clk_status/latest

Test location /workspace/coverage/default/20.clkmgr_div_intersig_mubi.2350069179
Short name T35
Test name
Test status
Simulation time 30648259 ps
CPU time 0.86 seconds
Started Jul 24 07:08:43 PM PDT 24
Finished Jul 24 07:08:44 PM PDT 24
Peak memory 200532 kb
Host smart-0995b768-f639-4bae-b247-3b817361507f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350069179 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_div_intersig_mubi.2350069179
Directory /workspace/20.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_extclk.753771868
Short name T413
Test name
Test status
Simulation time 125178254 ps
CPU time 1.23 seconds
Started Jul 24 07:08:45 PM PDT 24
Finished Jul 24 07:08:46 PM PDT 24
Peak memory 200516 kb
Host smart-9f6d7944-7e33-4069-9a57-a0a2cea2a851
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753771868 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.753771868
Directory /workspace/20.clkmgr_extclk/latest

Test location /workspace/coverage/default/20.clkmgr_frequency.614580256
Short name T218
Test name
Test status
Simulation time 2480827627 ps
CPU time 19.59 seconds
Started Jul 24 07:08:44 PM PDT 24
Finished Jul 24 07:09:04 PM PDT 24
Peak memory 200744 kb
Host smart-8bd23424-0bc9-4b64-8413-8d22d4c10bc5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614580256 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.614580256
Directory /workspace/20.clkmgr_frequency/latest

Test location /workspace/coverage/default/20.clkmgr_frequency_timeout.1892977369
Short name T588
Test name
Test status
Simulation time 159595674 ps
CPU time 1.31 seconds
Started Jul 24 07:08:51 PM PDT 24
Finished Jul 24 07:08:52 PM PDT 24
Peak memory 200496 kb
Host smart-bbf33799-3753-43ad-acb8-87cf17a24524
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892977369 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_t
imeout.1892977369
Directory /workspace/20.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/20.clkmgr_idle_intersig_mubi.1758116676
Short name T817
Test name
Test status
Simulation time 25123756 ps
CPU time 0.78 seconds
Started Jul 24 07:08:42 PM PDT 24
Finished Jul 24 07:08:43 PM PDT 24
Peak memory 200464 kb
Host smart-efe24f86-cd82-4b73-8d00-81658d5d5e22
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758116676 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_idle_intersig_mubi.1758116676
Directory /workspace/20.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.3746320096
Short name T627
Test name
Test status
Simulation time 47906717 ps
CPU time 0.86 seconds
Started Jul 24 07:08:51 PM PDT 24
Finished Jul 24 07:08:52 PM PDT 24
Peak memory 200448 kb
Host smart-7336ca3c-c1ed-401a-98fd-49bba657442a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746320096 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.clkmgr_lc_clk_byp_req_intersig_mubi.3746320096
Directory /workspace/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.1281175134
Short name T256
Test name
Test status
Simulation time 41332424 ps
CPU time 0.83 seconds
Started Jul 24 07:08:39 PM PDT 24
Finished Jul 24 07:08:40 PM PDT 24
Peak memory 200480 kb
Host smart-4ab870dc-8f4b-437f-ba8d-516435a238f9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281175134 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.clkmgr_lc_ctrl_intersig_mubi.1281175134
Directory /workspace/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_peri.3970819448
Short name T500
Test name
Test status
Simulation time 22365741 ps
CPU time 0.84 seconds
Started Jul 24 07:08:54 PM PDT 24
Finished Jul 24 07:08:55 PM PDT 24
Peak memory 200484 kb
Host smart-95a8ee57-38d6-4f17-9e15-4302cf4ae845
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970819448 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.3970819448
Directory /workspace/20.clkmgr_peri/latest

Test location /workspace/coverage/default/20.clkmgr_regwen.2561218311
Short name T150
Test name
Test status
Simulation time 501055492 ps
CPU time 2.41 seconds
Started Jul 24 07:08:44 PM PDT 24
Finished Jul 24 07:08:47 PM PDT 24
Peak memory 200472 kb
Host smart-3300bb2f-5970-4e33-bb22-4a1eddb42fe2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561218311 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.2561218311
Directory /workspace/20.clkmgr_regwen/latest

Test location /workspace/coverage/default/20.clkmgr_smoke.2585438283
Short name T562
Test name
Test status
Simulation time 18929221 ps
CPU time 0.84 seconds
Started Jul 24 07:08:48 PM PDT 24
Finished Jul 24 07:08:49 PM PDT 24
Peak memory 200356 kb
Host smart-f03f085e-0f32-4963-8240-11ad2d204031
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585438283 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.2585438283
Directory /workspace/20.clkmgr_smoke/latest

Test location /workspace/coverage/default/20.clkmgr_stress_all.3460787353
Short name T665
Test name
Test status
Simulation time 8689528612 ps
CPU time 47.33 seconds
Started Jul 24 07:08:48 PM PDT 24
Finished Jul 24 07:09:36 PM PDT 24
Peak memory 200856 kb
Host smart-6b08f9d9-1832-49d8-bbce-278e5049d8fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460787353 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_stress_all.3460787353
Directory /workspace/20.clkmgr_stress_all/latest

Test location /workspace/coverage/default/20.clkmgr_trans.1548846898
Short name T766
Test name
Test status
Simulation time 17853463 ps
CPU time 0.8 seconds
Started Jul 24 07:08:48 PM PDT 24
Finished Jul 24 07:08:49 PM PDT 24
Peak memory 200536 kb
Host smart-c46fd34f-1314-4b28-a6e4-c648d0b6465d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548846898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.1548846898
Directory /workspace/20.clkmgr_trans/latest

Test location /workspace/coverage/default/21.clkmgr_alert_test.3245770402
Short name T294
Test name
Test status
Simulation time 33236952 ps
CPU time 0.76 seconds
Started Jul 24 07:08:43 PM PDT 24
Finished Jul 24 07:08:44 PM PDT 24
Peak memory 200524 kb
Host smart-47bbbc9c-d035-4e2a-bf48-938793ce0a6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245770402 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clk
mgr_alert_test.3245770402
Directory /workspace/21.clkmgr_alert_test/latest

Test location /workspace/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.3026486771
Short name T791
Test name
Test status
Simulation time 29616376 ps
CPU time 0.73 seconds
Started Jul 24 07:08:45 PM PDT 24
Finished Jul 24 07:08:46 PM PDT 24
Peak memory 200448 kb
Host smart-2ab39134-4160-4f95-be29-ca0b1a977cc6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026486771 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_clk_handshake_intersig_mubi.3026486771
Directory /workspace/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_clk_status.1926349159
Short name T157
Test name
Test status
Simulation time 14156139 ps
CPU time 0.67 seconds
Started Jul 24 07:08:44 PM PDT 24
Finished Jul 24 07:08:45 PM PDT 24
Peak memory 199664 kb
Host smart-05db12e9-7009-4ab1-9538-9d2d97be5d32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926349159 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.1926349159
Directory /workspace/21.clkmgr_clk_status/latest

Test location /workspace/coverage/default/21.clkmgr_div_intersig_mubi.1224737920
Short name T53
Test name
Test status
Simulation time 21059957 ps
CPU time 0.83 seconds
Started Jul 24 07:08:42 PM PDT 24
Finished Jul 24 07:08:43 PM PDT 24
Peak memory 200464 kb
Host smart-15650433-c602-4e60-a03c-987777d9cde2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224737920 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_div_intersig_mubi.1224737920
Directory /workspace/21.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_extclk.3230572559
Short name T683
Test name
Test status
Simulation time 25852163 ps
CPU time 0.87 seconds
Started Jul 24 07:08:46 PM PDT 24
Finished Jul 24 07:08:48 PM PDT 24
Peak memory 200488 kb
Host smart-9a3cc736-09ad-4761-a5ee-a1d61d7a311e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230572559 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.3230572559
Directory /workspace/21.clkmgr_extclk/latest

Test location /workspace/coverage/default/21.clkmgr_frequency.493256567
Short name T260
Test name
Test status
Simulation time 2490156579 ps
CPU time 14.59 seconds
Started Jul 24 07:08:43 PM PDT 24
Finished Jul 24 07:08:58 PM PDT 24
Peak memory 200688 kb
Host smart-8adabdf9-d418-4b00-8043-148a937bb3ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493256567 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.493256567
Directory /workspace/21.clkmgr_frequency/latest

Test location /workspace/coverage/default/21.clkmgr_frequency_timeout.3260769909
Short name T723
Test name
Test status
Simulation time 1019422927 ps
CPU time 4.42 seconds
Started Jul 24 07:08:49 PM PDT 24
Finished Jul 24 07:08:53 PM PDT 24
Peak memory 200424 kb
Host smart-1cb0f7c2-7c99-42c6-8bda-97b980c20589
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260769909 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_t
imeout.3260769909
Directory /workspace/21.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/21.clkmgr_idle_intersig_mubi.3281079729
Short name T220
Test name
Test status
Simulation time 44884861 ps
CPU time 1.01 seconds
Started Jul 24 07:08:44 PM PDT 24
Finished Jul 24 07:08:45 PM PDT 24
Peak memory 200392 kb
Host smart-d4db887a-a609-43a6-994b-734b6ac2e618
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281079729 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_idle_intersig_mubi.3281079729
Directory /workspace/21.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.1822629973
Short name T516
Test name
Test status
Simulation time 22109176 ps
CPU time 0.77 seconds
Started Jul 24 07:08:48 PM PDT 24
Finished Jul 24 07:08:49 PM PDT 24
Peak memory 200452 kb
Host smart-5d7c4b1b-30fe-4563-b15b-db26965d9dc2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822629973 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.clkmgr_lc_clk_byp_req_intersig_mubi.1822629973
Directory /workspace/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.482932819
Short name T660
Test name
Test status
Simulation time 45494044 ps
CPU time 1 seconds
Started Jul 24 07:08:48 PM PDT 24
Finished Jul 24 07:08:50 PM PDT 24
Peak memory 200504 kb
Host smart-10dca569-e51a-4c8f-ae15-f8a47ebda23d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482932819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 21.clkmgr_lc_ctrl_intersig_mubi.482932819
Directory /workspace/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_peri.2883292752
Short name T522
Test name
Test status
Simulation time 15824333 ps
CPU time 0.73 seconds
Started Jul 24 07:08:51 PM PDT 24
Finished Jul 24 07:08:51 PM PDT 24
Peak memory 200352 kb
Host smart-c9800f56-0414-4b04-8675-e49fdf589cd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883292752 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.2883292752
Directory /workspace/21.clkmgr_peri/latest

Test location /workspace/coverage/default/21.clkmgr_regwen.103853346
Short name T147
Test name
Test status
Simulation time 628297266 ps
CPU time 2.64 seconds
Started Jul 24 07:08:43 PM PDT 24
Finished Jul 24 07:08:46 PM PDT 24
Peak memory 200468 kb
Host smart-71878d91-f24d-4309-8bc3-4a3858661b80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103853346 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.103853346
Directory /workspace/21.clkmgr_regwen/latest

Test location /workspace/coverage/default/21.clkmgr_smoke.273420147
Short name T141
Test name
Test status
Simulation time 23015819 ps
CPU time 0.86 seconds
Started Jul 24 07:08:48 PM PDT 24
Finished Jul 24 07:08:49 PM PDT 24
Peak memory 200396 kb
Host smart-1412c90c-8fb5-4d04-bba2-9e8d417bd671
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273420147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.273420147
Directory /workspace/21.clkmgr_smoke/latest

Test location /workspace/coverage/default/21.clkmgr_stress_all.1338202698
Short name T497
Test name
Test status
Simulation time 1014549276 ps
CPU time 5.91 seconds
Started Jul 24 07:08:42 PM PDT 24
Finished Jul 24 07:08:49 PM PDT 24
Peak memory 200636 kb
Host smart-006e1033-a87f-429d-93c9-ce528b5a4a8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338202698 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_stress_all.1338202698
Directory /workspace/21.clkmgr_stress_all/latest

Test location /workspace/coverage/default/21.clkmgr_trans.3474038870
Short name T421
Test name
Test status
Simulation time 35841410 ps
CPU time 1.04 seconds
Started Jul 24 07:08:42 PM PDT 24
Finished Jul 24 07:08:43 PM PDT 24
Peak memory 200460 kb
Host smart-3d2bcb2f-acb0-4c50-ba38-20b9d976086f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474038870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.3474038870
Directory /workspace/21.clkmgr_trans/latest

Test location /workspace/coverage/default/22.clkmgr_alert_test.1342850390
Short name T567
Test name
Test status
Simulation time 32690072 ps
CPU time 0.79 seconds
Started Jul 24 07:08:53 PM PDT 24
Finished Jul 24 07:08:54 PM PDT 24
Peak memory 200612 kb
Host smart-d3d2b05d-0ba8-44fd-9bde-b78c4327b069
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342850390 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clk
mgr_alert_test.1342850390
Directory /workspace/22.clkmgr_alert_test/latest

Test location /workspace/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.2257975281
Short name T406
Test name
Test status
Simulation time 21544058 ps
CPU time 0.83 seconds
Started Jul 24 07:08:55 PM PDT 24
Finished Jul 24 07:08:56 PM PDT 24
Peak memory 200476 kb
Host smart-40af0c0c-5424-4449-9b70-9b614f2ab06c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257975281 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_clk_handshake_intersig_mubi.2257975281
Directory /workspace/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_clk_status.677758931
Short name T314
Test name
Test status
Simulation time 44843082 ps
CPU time 0.81 seconds
Started Jul 24 07:08:51 PM PDT 24
Finished Jul 24 07:08:52 PM PDT 24
Peak memory 200352 kb
Host smart-0f73d876-2f61-45ca-b62f-cbd3ad90161f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677758931 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.677758931
Directory /workspace/22.clkmgr_clk_status/latest

Test location /workspace/coverage/default/22.clkmgr_div_intersig_mubi.2624489821
Short name T570
Test name
Test status
Simulation time 16181946 ps
CPU time 0.78 seconds
Started Jul 24 07:08:44 PM PDT 24
Finished Jul 24 07:08:45 PM PDT 24
Peak memory 200444 kb
Host smart-ef0c4649-a6c0-407d-a57a-6e6f6d12f102
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624489821 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_div_intersig_mubi.2624489821
Directory /workspace/22.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_extclk.2579591698
Short name T227
Test name
Test status
Simulation time 38482798 ps
CPU time 0.92 seconds
Started Jul 24 07:08:51 PM PDT 24
Finished Jul 24 07:08:52 PM PDT 24
Peak memory 200688 kb
Host smart-1ecdb68d-7133-4f16-8c71-262909eaf99b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579591698 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.2579591698
Directory /workspace/22.clkmgr_extclk/latest

Test location /workspace/coverage/default/22.clkmgr_frequency.3554045476
Short name T459
Test name
Test status
Simulation time 562384487 ps
CPU time 4.59 seconds
Started Jul 24 07:08:42 PM PDT 24
Finished Jul 24 07:08:47 PM PDT 24
Peak memory 200492 kb
Host smart-900d1388-f693-4f9a-84c3-0ecc25046d64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554045476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.3554045476
Directory /workspace/22.clkmgr_frequency/latest

Test location /workspace/coverage/default/22.clkmgr_frequency_timeout.3687965369
Short name T397
Test name
Test status
Simulation time 1703251242 ps
CPU time 8.66 seconds
Started Jul 24 07:08:47 PM PDT 24
Finished Jul 24 07:08:56 PM PDT 24
Peak memory 200496 kb
Host smart-1738a4a1-dfc5-4889-86d7-d8c3e0da98c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687965369 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_t
imeout.3687965369
Directory /workspace/22.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/22.clkmgr_idle_intersig_mubi.1921625506
Short name T51
Test name
Test status
Simulation time 15197805 ps
CPU time 0.78 seconds
Started Jul 24 07:08:46 PM PDT 24
Finished Jul 24 07:08:47 PM PDT 24
Peak memory 200544 kb
Host smart-adc05484-c66b-4223-b91e-4f0a506e868d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921625506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_idle_intersig_mubi.1921625506
Directory /workspace/22.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.3418032705
Short name T396
Test name
Test status
Simulation time 16289750 ps
CPU time 0.77 seconds
Started Jul 24 07:08:51 PM PDT 24
Finished Jul 24 07:08:52 PM PDT 24
Peak memory 200692 kb
Host smart-69860caf-ad01-432a-93bc-f39376ee2e0d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418032705 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.clkmgr_lc_clk_byp_req_intersig_mubi.3418032705
Directory /workspace/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.3700001706
Short name T75
Test name
Test status
Simulation time 46369017 ps
CPU time 1 seconds
Started Jul 24 07:08:54 PM PDT 24
Finished Jul 24 07:08:56 PM PDT 24
Peak memory 200472 kb
Host smart-b80ae6d8-294d-417b-a6d3-ab02eaa09795
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700001706 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.clkmgr_lc_ctrl_intersig_mubi.3700001706
Directory /workspace/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_peri.4138331948
Short name T822
Test name
Test status
Simulation time 18470026 ps
CPU time 0.84 seconds
Started Jul 24 07:08:43 PM PDT 24
Finished Jul 24 07:08:44 PM PDT 24
Peak memory 200424 kb
Host smart-04f37936-16e5-4e71-9f75-5ba64a044f8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138331948 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.4138331948
Directory /workspace/22.clkmgr_peri/latest

Test location /workspace/coverage/default/22.clkmgr_regwen.3860029828
Short name T149
Test name
Test status
Simulation time 479424298 ps
CPU time 2.45 seconds
Started Jul 24 07:08:44 PM PDT 24
Finished Jul 24 07:08:47 PM PDT 24
Peak memory 200460 kb
Host smart-5d0b4a1c-d070-40ef-82de-eb1a3a8baa83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860029828 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.3860029828
Directory /workspace/22.clkmgr_regwen/latest

Test location /workspace/coverage/default/22.clkmgr_smoke.1697694267
Short name T425
Test name
Test status
Simulation time 21147214 ps
CPU time 0.85 seconds
Started Jul 24 07:08:54 PM PDT 24
Finished Jul 24 07:08:55 PM PDT 24
Peak memory 200432 kb
Host smart-1d732e67-3ecf-4fbe-969a-e49cfe66f414
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697694267 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.1697694267
Directory /workspace/22.clkmgr_smoke/latest

Test location /workspace/coverage/default/22.clkmgr_stress_all.1471409421
Short name T291
Test name
Test status
Simulation time 11435754338 ps
CPU time 61.13 seconds
Started Jul 24 07:08:44 PM PDT 24
Finished Jul 24 07:09:45 PM PDT 24
Peak memory 200780 kb
Host smart-afcc7a7d-b460-4a9d-845c-dcb3321698c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471409421 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_stress_all.1471409421
Directory /workspace/22.clkmgr_stress_all/latest

Test location /workspace/coverage/default/22.clkmgr_stress_all_with_rand_reset.3747376965
Short name T165
Test name
Test status
Simulation time 78297074220 ps
CPU time 877.56 seconds
Started Jul 24 07:08:44 PM PDT 24
Finished Jul 24 07:23:22 PM PDT 24
Peak memory 214900 kb
Host smart-793d6e65-68cd-4ffa-8d94-955afc63799c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3747376965 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all_with_rand_reset.3747376965
Directory /workspace/22.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.clkmgr_trans.3439156266
Short name T268
Test name
Test status
Simulation time 50323377 ps
CPU time 0.99 seconds
Started Jul 24 07:08:54 PM PDT 24
Finished Jul 24 07:08:55 PM PDT 24
Peak memory 200472 kb
Host smart-78468261-e948-41d0-9ac1-f6bae4a8c0c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439156266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.3439156266
Directory /workspace/22.clkmgr_trans/latest

Test location /workspace/coverage/default/23.clkmgr_alert_test.4130032139
Short name T184
Test name
Test status
Simulation time 42960261 ps
CPU time 0.81 seconds
Started Jul 24 07:08:51 PM PDT 24
Finished Jul 24 07:08:52 PM PDT 24
Peak memory 200512 kb
Host smart-2959c2ee-ac30-4ce7-a80a-72298b7e45e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130032139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clk
mgr_alert_test.4130032139
Directory /workspace/23.clkmgr_alert_test/latest

Test location /workspace/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.4021666151
Short name T324
Test name
Test status
Simulation time 17259345 ps
CPU time 0.82 seconds
Started Jul 24 07:08:51 PM PDT 24
Finished Jul 24 07:08:52 PM PDT 24
Peak memory 200532 kb
Host smart-ae5b0018-97ec-477d-b7ea-8a9cedd2e8b2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021666151 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_clk_handshake_intersig_mubi.4021666151
Directory /workspace/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_clk_status.3818747282
Short name T794
Test name
Test status
Simulation time 12964547 ps
CPU time 0.71 seconds
Started Jul 24 07:08:50 PM PDT 24
Finished Jul 24 07:08:51 PM PDT 24
Peak memory 199672 kb
Host smart-87929220-0cda-42f7-b274-b65af9f3afbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818747282 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.3818747282
Directory /workspace/23.clkmgr_clk_status/latest

Test location /workspace/coverage/default/23.clkmgr_div_intersig_mubi.667719880
Short name T689
Test name
Test status
Simulation time 111194504 ps
CPU time 1.21 seconds
Started Jul 24 07:08:54 PM PDT 24
Finished Jul 24 07:08:55 PM PDT 24
Peak memory 200404 kb
Host smart-28a6b8fa-0149-435d-8dab-e86541a8d812
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667719880 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.clkmgr_div_intersig_mubi.667719880
Directory /workspace/23.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_extclk.2510378071
Short name T48
Test name
Test status
Simulation time 21887550 ps
CPU time 0.8 seconds
Started Jul 24 07:08:49 PM PDT 24
Finished Jul 24 07:08:50 PM PDT 24
Peak memory 200548 kb
Host smart-0ce80c3a-e074-4da7-afcd-1e44913dfda6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510378071 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.2510378071
Directory /workspace/23.clkmgr_extclk/latest

Test location /workspace/coverage/default/23.clkmgr_frequency.3990455849
Short name T368
Test name
Test status
Simulation time 330051282 ps
CPU time 2.02 seconds
Started Jul 24 07:08:50 PM PDT 24
Finished Jul 24 07:08:52 PM PDT 24
Peak memory 200476 kb
Host smart-ffe7e6b5-6d71-4cf3-83c1-7b0d8ef83044
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990455849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.3990455849
Directory /workspace/23.clkmgr_frequency/latest

Test location /workspace/coverage/default/23.clkmgr_frequency_timeout.482795983
Short name T747
Test name
Test status
Simulation time 1643722799 ps
CPU time 6.95 seconds
Started Jul 24 07:08:54 PM PDT 24
Finished Jul 24 07:09:02 PM PDT 24
Peak memory 200548 kb
Host smart-56676fa4-109f-43a0-84de-a36fe719118a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482795983 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_ti
meout.482795983
Directory /workspace/23.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/23.clkmgr_idle_intersig_mubi.982459804
Short name T625
Test name
Test status
Simulation time 64249345 ps
CPU time 1 seconds
Started Jul 24 07:08:52 PM PDT 24
Finished Jul 24 07:08:53 PM PDT 24
Peak memory 200464 kb
Host smart-da2998b2-d105-4aa3-9570-1e636b1f54e4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982459804 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.clkmgr_idle_intersig_mubi.982459804
Directory /workspace/23.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.3952239158
Short name T23
Test name
Test status
Simulation time 26992818 ps
CPU time 0.75 seconds
Started Jul 24 07:08:57 PM PDT 24
Finished Jul 24 07:08:58 PM PDT 24
Peak memory 200452 kb
Host smart-58a19cbd-0894-498e-b0ce-abb1b40c4aa3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952239158 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.clkmgr_lc_clk_byp_req_intersig_mubi.3952239158
Directory /workspace/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.1395046998
Short name T111
Test name
Test status
Simulation time 61715874 ps
CPU time 0.99 seconds
Started Jul 24 07:08:56 PM PDT 24
Finished Jul 24 07:08:57 PM PDT 24
Peak memory 200532 kb
Host smart-5385dd59-c2a6-4319-91f0-87262e6bd800
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395046998 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.clkmgr_lc_ctrl_intersig_mubi.1395046998
Directory /workspace/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_peri.1225730211
Short name T744
Test name
Test status
Simulation time 21101025 ps
CPU time 0.75 seconds
Started Jul 24 07:08:54 PM PDT 24
Finished Jul 24 07:08:55 PM PDT 24
Peak memory 200484 kb
Host smart-e2af503f-19bc-47bc-9873-52ab448d7e9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225730211 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.1225730211
Directory /workspace/23.clkmgr_peri/latest

Test location /workspace/coverage/default/23.clkmgr_regwen.1520950502
Short name T254
Test name
Test status
Simulation time 921144023 ps
CPU time 3.65 seconds
Started Jul 24 07:08:53 PM PDT 24
Finished Jul 24 07:08:56 PM PDT 24
Peak memory 200692 kb
Host smart-b3cc217e-e4d1-4d10-a754-619e46133b6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520950502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.1520950502
Directory /workspace/23.clkmgr_regwen/latest

Test location /workspace/coverage/default/23.clkmgr_smoke.2571726386
Short name T237
Test name
Test status
Simulation time 43678227 ps
CPU time 0.91 seconds
Started Jul 24 07:08:48 PM PDT 24
Finished Jul 24 07:08:49 PM PDT 24
Peak memory 200448 kb
Host smart-f49bfb93-285d-473a-a3ed-f7f2107a9f7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571726386 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.2571726386
Directory /workspace/23.clkmgr_smoke/latest

Test location /workspace/coverage/default/23.clkmgr_trans.2387767065
Short name T672
Test name
Test status
Simulation time 15779262 ps
CPU time 0.75 seconds
Started Jul 24 07:08:51 PM PDT 24
Finished Jul 24 07:08:52 PM PDT 24
Peak memory 200508 kb
Host smart-035058f1-d517-45da-8b67-f1f0b42b0656
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387767065 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.2387767065
Directory /workspace/23.clkmgr_trans/latest

Test location /workspace/coverage/default/24.clkmgr_alert_test.79104160
Short name T583
Test name
Test status
Simulation time 20627139 ps
CPU time 0.73 seconds
Started Jul 24 07:08:53 PM PDT 24
Finished Jul 24 07:08:54 PM PDT 24
Peak memory 200532 kb
Host smart-d7ac3e03-d978-45d0-afb3-26378f5cf7fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79104160 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmg
r_alert_test.79104160
Directory /workspace/24.clkmgr_alert_test/latest

Test location /workspace/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.1460817459
Short name T196
Test name
Test status
Simulation time 21082551 ps
CPU time 0.77 seconds
Started Jul 24 07:08:50 PM PDT 24
Finished Jul 24 07:08:51 PM PDT 24
Peak memory 200448 kb
Host smart-3bc7b79a-69ae-4600-ad50-ae5c26967973
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460817459 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_clk_handshake_intersig_mubi.1460817459
Directory /workspace/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_clk_status.490065380
Short name T440
Test name
Test status
Simulation time 14572894 ps
CPU time 0.71 seconds
Started Jul 24 07:08:48 PM PDT 24
Finished Jul 24 07:08:49 PM PDT 24
Peak memory 200416 kb
Host smart-8132e309-3e77-4971-b2cd-8bf2ddbcef5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490065380 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.490065380
Directory /workspace/24.clkmgr_clk_status/latest

Test location /workspace/coverage/default/24.clkmgr_div_intersig_mubi.3465208529
Short name T225
Test name
Test status
Simulation time 70655396 ps
CPU time 1.01 seconds
Started Jul 24 07:08:52 PM PDT 24
Finished Jul 24 07:08:53 PM PDT 24
Peak memory 200456 kb
Host smart-97acba4d-c63d-4e70-89ca-29eaec92fef2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465208529 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_div_intersig_mubi.3465208529
Directory /workspace/24.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_extclk.2144774132
Short name T302
Test name
Test status
Simulation time 27156665 ps
CPU time 0.94 seconds
Started Jul 24 07:08:47 PM PDT 24
Finished Jul 24 07:08:48 PM PDT 24
Peak memory 200476 kb
Host smart-0cabef6b-052c-41e4-a823-a7bc5a7b854d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144774132 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.2144774132
Directory /workspace/24.clkmgr_extclk/latest

Test location /workspace/coverage/default/24.clkmgr_frequency.3990091311
Short name T758
Test name
Test status
Simulation time 338170601 ps
CPU time 2.03 seconds
Started Jul 24 07:08:48 PM PDT 24
Finished Jul 24 07:08:51 PM PDT 24
Peak memory 200480 kb
Host smart-b1600c64-c0cc-451c-98b6-e8dda90b483f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990091311 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.3990091311
Directory /workspace/24.clkmgr_frequency/latest

Test location /workspace/coverage/default/24.clkmgr_frequency_timeout.665131579
Short name T584
Test name
Test status
Simulation time 2427627444 ps
CPU time 12.99 seconds
Started Jul 24 07:08:48 PM PDT 24
Finished Jul 24 07:09:01 PM PDT 24
Peak memory 200680 kb
Host smart-491e5018-990c-4230-aa97-98b15883f73a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665131579 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_ti
meout.665131579
Directory /workspace/24.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/24.clkmgr_idle_intersig_mubi.3491137551
Short name T482
Test name
Test status
Simulation time 38839045 ps
CPU time 1.03 seconds
Started Jul 24 07:08:53 PM PDT 24
Finished Jul 24 07:08:54 PM PDT 24
Peak memory 200476 kb
Host smart-de927350-444d-4ccc-bda8-254a49b2f201
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491137551 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_idle_intersig_mubi.3491137551
Directory /workspace/24.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.3426867218
Short name T430
Test name
Test status
Simulation time 67986442 ps
CPU time 0.94 seconds
Started Jul 24 07:08:51 PM PDT 24
Finished Jul 24 07:08:52 PM PDT 24
Peak memory 200444 kb
Host smart-e2c66e85-53c0-4ccf-9801-e8a81bf4680c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426867218 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.clkmgr_lc_clk_byp_req_intersig_mubi.3426867218
Directory /workspace/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.2211985586
Short name T594
Test name
Test status
Simulation time 26819807 ps
CPU time 0.92 seconds
Started Jul 24 07:08:51 PM PDT 24
Finished Jul 24 07:08:52 PM PDT 24
Peak memory 200496 kb
Host smart-17e57b16-34b5-436a-9a6f-51e96f039d00
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211985586 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.clkmgr_lc_ctrl_intersig_mubi.2211985586
Directory /workspace/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_peri.2008579729
Short name T272
Test name
Test status
Simulation time 147016286 ps
CPU time 1.08 seconds
Started Jul 24 07:08:52 PM PDT 24
Finished Jul 24 07:08:54 PM PDT 24
Peak memory 200456 kb
Host smart-34bb4e38-a156-4e00-8d1e-f41f8772e087
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008579729 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.2008579729
Directory /workspace/24.clkmgr_peri/latest

Test location /workspace/coverage/default/24.clkmgr_regwen.3449794509
Short name T304
Test name
Test status
Simulation time 334576550 ps
CPU time 2.33 seconds
Started Jul 24 07:08:50 PM PDT 24
Finished Jul 24 07:08:52 PM PDT 24
Peak memory 200448 kb
Host smart-1b54fbe9-3627-4e04-8866-25e1e758ea8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449794509 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.3449794509
Directory /workspace/24.clkmgr_regwen/latest

Test location /workspace/coverage/default/24.clkmgr_smoke.593576540
Short name T760
Test name
Test status
Simulation time 16548263 ps
CPU time 0.82 seconds
Started Jul 24 07:08:47 PM PDT 24
Finished Jul 24 07:08:48 PM PDT 24
Peak memory 200284 kb
Host smart-905f95d7-d14d-42f4-9735-321b5b60cc4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593576540 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.593576540
Directory /workspace/24.clkmgr_smoke/latest

Test location /workspace/coverage/default/24.clkmgr_stress_all.2811450920
Short name T772
Test name
Test status
Simulation time 5974190008 ps
CPU time 21.66 seconds
Started Jul 24 07:08:54 PM PDT 24
Finished Jul 24 07:09:16 PM PDT 24
Peak memory 200764 kb
Host smart-46143644-8e4d-408f-b41f-9e481678d7af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811450920 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_stress_all.2811450920
Directory /workspace/24.clkmgr_stress_all/latest

Test location /workspace/coverage/default/24.clkmgr_trans.2886152815
Short name T194
Test name
Test status
Simulation time 75230538 ps
CPU time 1.03 seconds
Started Jul 24 07:08:47 PM PDT 24
Finished Jul 24 07:08:48 PM PDT 24
Peak memory 200504 kb
Host smart-d46c969f-4e87-403f-99d8-661b7a2b14bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886152815 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.2886152815
Directory /workspace/24.clkmgr_trans/latest

Test location /workspace/coverage/default/25.clkmgr_alert_test.3585143269
Short name T221
Test name
Test status
Simulation time 16347719 ps
CPU time 0.78 seconds
Started Jul 24 07:08:55 PM PDT 24
Finished Jul 24 07:08:56 PM PDT 24
Peak memory 200564 kb
Host smart-568bfc9d-ecb6-47f3-a3f6-ce2408dbfea4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585143269 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clk
mgr_alert_test.3585143269
Directory /workspace/25.clkmgr_alert_test/latest

Test location /workspace/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.801801036
Short name T90
Test name
Test status
Simulation time 29150159 ps
CPU time 0.99 seconds
Started Jul 24 07:08:50 PM PDT 24
Finished Jul 24 07:08:51 PM PDT 24
Peak memory 200508 kb
Host smart-a5af0f15-d8b5-4d60-9705-6db67c97c0dc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801801036 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_clk_handshake_intersig_mubi.801801036
Directory /workspace/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_clk_status.4125373774
Short name T800
Test name
Test status
Simulation time 17265546 ps
CPU time 0.7 seconds
Started Jul 24 07:08:49 PM PDT 24
Finished Jul 24 07:08:50 PM PDT 24
Peak memory 200392 kb
Host smart-642869c5-f120-4b31-9eff-5179e42ef70e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125373774 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.4125373774
Directory /workspace/25.clkmgr_clk_status/latest

Test location /workspace/coverage/default/25.clkmgr_div_intersig_mubi.2075743436
Short name T590
Test name
Test status
Simulation time 66616436 ps
CPU time 0.97 seconds
Started Jul 24 07:08:53 PM PDT 24
Finished Jul 24 07:08:54 PM PDT 24
Peak memory 200460 kb
Host smart-5e51d094-b676-4687-82c8-a0ad8ae954fb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075743436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_div_intersig_mubi.2075743436
Directory /workspace/25.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_extclk.2312517740
Short name T638
Test name
Test status
Simulation time 39882585 ps
CPU time 0.91 seconds
Started Jul 24 07:08:53 PM PDT 24
Finished Jul 24 07:08:54 PM PDT 24
Peak memory 200516 kb
Host smart-e1803afd-6bf3-4705-b4f1-e6a3b0a993a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312517740 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.2312517740
Directory /workspace/25.clkmgr_extclk/latest

Test location /workspace/coverage/default/25.clkmgr_frequency.742912572
Short name T115
Test name
Test status
Simulation time 1642228286 ps
CPU time 10.8 seconds
Started Jul 24 07:08:58 PM PDT 24
Finished Jul 24 07:09:09 PM PDT 24
Peak memory 200444 kb
Host smart-8e84bf4a-64cc-413f-b7b5-0ad0feaff648
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742912572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.742912572
Directory /workspace/25.clkmgr_frequency/latest

Test location /workspace/coverage/default/25.clkmgr_frequency_timeout.1871657741
Short name T514
Test name
Test status
Simulation time 856650184 ps
CPU time 6.77 seconds
Started Jul 24 07:08:52 PM PDT 24
Finished Jul 24 07:08:59 PM PDT 24
Peak memory 200556 kb
Host smart-b3b8d4bf-d843-46a5-bbdf-e435f791b7f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871657741 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_t
imeout.1871657741
Directory /workspace/25.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/25.clkmgr_idle_intersig_mubi.3399675223
Short name T310
Test name
Test status
Simulation time 22763274 ps
CPU time 0.84 seconds
Started Jul 24 07:08:49 PM PDT 24
Finished Jul 24 07:08:50 PM PDT 24
Peak memory 200460 kb
Host smart-c4361d6a-6728-4ccf-a57b-d9fe2b71b13d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399675223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_idle_intersig_mubi.3399675223
Directory /workspace/25.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.1806110063
Short name T270
Test name
Test status
Simulation time 16917798 ps
CPU time 0.77 seconds
Started Jul 24 07:08:49 PM PDT 24
Finished Jul 24 07:08:50 PM PDT 24
Peak memory 200376 kb
Host smart-a783820f-21f8-4641-aacf-243ce5b5db7f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806110063 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.clkmgr_lc_clk_byp_req_intersig_mubi.1806110063
Directory /workspace/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.2854975598
Short name T242
Test name
Test status
Simulation time 30275575 ps
CPU time 0.78 seconds
Started Jul 24 07:08:49 PM PDT 24
Finished Jul 24 07:08:50 PM PDT 24
Peak memory 200500 kb
Host smart-f0af29f2-4a05-4869-b402-cb83c37a04d3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854975598 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.clkmgr_lc_ctrl_intersig_mubi.2854975598
Directory /workspace/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_peri.3648148325
Short name T659
Test name
Test status
Simulation time 64006149 ps
CPU time 0.89 seconds
Started Jul 24 07:08:48 PM PDT 24
Finished Jul 24 07:08:49 PM PDT 24
Peak memory 200468 kb
Host smart-bdba21aa-66ce-462c-b61a-9c0dc39e2a91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648148325 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.3648148325
Directory /workspace/25.clkmgr_peri/latest

Test location /workspace/coverage/default/25.clkmgr_regwen.4286877866
Short name T681
Test name
Test status
Simulation time 920225779 ps
CPU time 5.37 seconds
Started Jul 24 07:08:48 PM PDT 24
Finished Jul 24 07:08:54 PM PDT 24
Peak memory 200668 kb
Host smart-976eee3b-d1e2-41a6-92ab-8511b1a2473c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286877866 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.4286877866
Directory /workspace/25.clkmgr_regwen/latest

Test location /workspace/coverage/default/25.clkmgr_smoke.256744203
Short name T820
Test name
Test status
Simulation time 73198974 ps
CPU time 1.01 seconds
Started Jul 24 07:08:55 PM PDT 24
Finished Jul 24 07:08:56 PM PDT 24
Peak memory 200432 kb
Host smart-98eeaa0e-6fc9-4873-8ebf-b51c1f334341
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256744203 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.256744203
Directory /workspace/25.clkmgr_smoke/latest

Test location /workspace/coverage/default/25.clkmgr_stress_all.1360629080
Short name T759
Test name
Test status
Simulation time 2407681055 ps
CPU time 10.57 seconds
Started Jul 24 07:08:56 PM PDT 24
Finished Jul 24 07:09:06 PM PDT 24
Peak memory 200820 kb
Host smart-fc6c18f3-379a-4feb-a0fd-3b6d04f97d3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360629080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_stress_all.1360629080
Directory /workspace/25.clkmgr_stress_all/latest

Test location /workspace/coverage/default/25.clkmgr_trans.1499176440
Short name T447
Test name
Test status
Simulation time 58863022 ps
CPU time 1.02 seconds
Started Jul 24 07:08:49 PM PDT 24
Finished Jul 24 07:08:50 PM PDT 24
Peak memory 200500 kb
Host smart-0c3a9ed3-27cc-4f87-97a8-38c661080812
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499176440 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.1499176440
Directory /workspace/25.clkmgr_trans/latest

Test location /workspace/coverage/default/26.clkmgr_alert_test.1792732302
Short name T774
Test name
Test status
Simulation time 14813721 ps
CPU time 0.78 seconds
Started Jul 24 07:09:01 PM PDT 24
Finished Jul 24 07:09:02 PM PDT 24
Peak memory 200532 kb
Host smart-c1ef1073-8cc9-4d91-83f0-754c8a396ae0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792732302 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clk
mgr_alert_test.1792732302
Directory /workspace/26.clkmgr_alert_test/latest

Test location /workspace/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.697146971
Short name T553
Test name
Test status
Simulation time 33556850 ps
CPU time 0.87 seconds
Started Jul 24 07:08:55 PM PDT 24
Finished Jul 24 07:08:56 PM PDT 24
Peak memory 200488 kb
Host smart-f364c3fb-e02a-4f56-854b-840d7afbe86b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697146971 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_clk_handshake_intersig_mubi.697146971
Directory /workspace/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_clk_status.1371081533
Short name T305
Test name
Test status
Simulation time 21512272 ps
CPU time 0.73 seconds
Started Jul 24 07:08:55 PM PDT 24
Finished Jul 24 07:09:01 PM PDT 24
Peak memory 199700 kb
Host smart-305aeb31-1b60-41cb-8fef-e1fe07324ee9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371081533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.1371081533
Directory /workspace/26.clkmgr_clk_status/latest

Test location /workspace/coverage/default/26.clkmgr_div_intersig_mubi.2565215216
Short name T714
Test name
Test status
Simulation time 36558269 ps
CPU time 0.87 seconds
Started Jul 24 07:08:57 PM PDT 24
Finished Jul 24 07:08:58 PM PDT 24
Peak memory 200468 kb
Host smart-a70339b9-687f-48e9-a01d-2368fbedf057
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565215216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_div_intersig_mubi.2565215216
Directory /workspace/26.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_extclk.224874835
Short name T813
Test name
Test status
Simulation time 73278986 ps
CPU time 1 seconds
Started Jul 24 07:09:02 PM PDT 24
Finished Jul 24 07:09:03 PM PDT 24
Peak memory 200492 kb
Host smart-09bb09ae-16e2-4178-9bf9-4eb0105a2d93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224874835 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.224874835
Directory /workspace/26.clkmgr_extclk/latest

Test location /workspace/coverage/default/26.clkmgr_frequency.316798438
Short name T548
Test name
Test status
Simulation time 2487859282 ps
CPU time 11.4 seconds
Started Jul 24 07:09:03 PM PDT 24
Finished Jul 24 07:09:14 PM PDT 24
Peak memory 200676 kb
Host smart-05b94772-77ab-4ed7-a9db-5d8e1d4694cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316798438 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.316798438
Directory /workspace/26.clkmgr_frequency/latest

Test location /workspace/coverage/default/26.clkmgr_frequency_timeout.163253190
Short name T381
Test name
Test status
Simulation time 1156242234 ps
CPU time 5.18 seconds
Started Jul 24 07:09:15 PM PDT 24
Finished Jul 24 07:09:20 PM PDT 24
Peak memory 200524 kb
Host smart-034a8b92-ab05-4da6-bf49-2d4afbee3017
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163253190 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_ti
meout.163253190
Directory /workspace/26.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/26.clkmgr_idle_intersig_mubi.3847145212
Short name T602
Test name
Test status
Simulation time 102390179 ps
CPU time 1.14 seconds
Started Jul 24 07:08:55 PM PDT 24
Finished Jul 24 07:08:56 PM PDT 24
Peak memory 200456 kb
Host smart-ede7a848-97ac-4a0a-b0ed-407bb8373d24
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847145212 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_idle_intersig_mubi.3847145212
Directory /workspace/26.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.188543263
Short name T224
Test name
Test status
Simulation time 18556135 ps
CPU time 0.8 seconds
Started Jul 24 07:09:06 PM PDT 24
Finished Jul 24 07:09:07 PM PDT 24
Peak memory 200432 kb
Host smart-462c4b5d-0b2b-4913-9ec1-fc05b878b2cb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188543263 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 26.clkmgr_lc_clk_byp_req_intersig_mubi.188543263
Directory /workspace/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.2409045450
Short name T622
Test name
Test status
Simulation time 14029200 ps
CPU time 0.74 seconds
Started Jul 24 07:09:05 PM PDT 24
Finished Jul 24 07:09:06 PM PDT 24
Peak memory 200400 kb
Host smart-5ec65675-f1b4-4f04-b242-bb5d342a337e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409045450 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_ctrl_intersig_mubi.2409045450
Directory /workspace/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_peri.908930212
Short name T564
Test name
Test status
Simulation time 15749250 ps
CPU time 0.74 seconds
Started Jul 24 07:09:02 PM PDT 24
Finished Jul 24 07:09:03 PM PDT 24
Peak memory 200416 kb
Host smart-7178b29a-eefd-40e7-a9e9-6d2481b7d852
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908930212 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.908930212
Directory /workspace/26.clkmgr_peri/latest

Test location /workspace/coverage/default/26.clkmgr_regwen.2119053644
Short name T663
Test name
Test status
Simulation time 333028040 ps
CPU time 2.02 seconds
Started Jul 24 07:08:56 PM PDT 24
Finished Jul 24 07:08:58 PM PDT 24
Peak memory 200464 kb
Host smart-a2f2cd5b-2366-4950-8fe8-d25d7cf9e4bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119053644 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.2119053644
Directory /workspace/26.clkmgr_regwen/latest

Test location /workspace/coverage/default/26.clkmgr_smoke.3292362972
Short name T552
Test name
Test status
Simulation time 22593611 ps
CPU time 0.83 seconds
Started Jul 24 07:08:59 PM PDT 24
Finished Jul 24 07:09:00 PM PDT 24
Peak memory 200412 kb
Host smart-4c961064-db78-485c-9b2e-7f36d1a74864
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292362972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.3292362972
Directory /workspace/26.clkmgr_smoke/latest

Test location /workspace/coverage/default/26.clkmgr_stress_all.1457600825
Short name T245
Test name
Test status
Simulation time 4772443481 ps
CPU time 26.76 seconds
Started Jul 24 07:09:02 PM PDT 24
Finished Jul 24 07:09:28 PM PDT 24
Peak memory 200724 kb
Host smart-2b659589-35e4-491e-90ab-c3084b8bd416
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457600825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_stress_all.1457600825
Directory /workspace/26.clkmgr_stress_all/latest

Test location /workspace/coverage/default/26.clkmgr_stress_all_with_rand_reset.2284882079
Short name T41
Test name
Test status
Simulation time 76705764382 ps
CPU time 652.61 seconds
Started Jul 24 07:08:55 PM PDT 24
Finished Jul 24 07:19:48 PM PDT 24
Peak memory 209108 kb
Host smart-56765b71-f457-44f6-bd72-83ea4bdf82d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2284882079 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_stress_all_with_rand_reset.2284882079
Directory /workspace/26.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.clkmgr_trans.1022046460
Short name T435
Test name
Test status
Simulation time 20096962 ps
CPU time 0.85 seconds
Started Jul 24 07:08:57 PM PDT 24
Finished Jul 24 07:08:58 PM PDT 24
Peak memory 200476 kb
Host smart-f00f8944-879e-41a4-9a4d-ef33d6a35405
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022046460 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.1022046460
Directory /workspace/26.clkmgr_trans/latest

Test location /workspace/coverage/default/27.clkmgr_alert_test.3660979624
Short name T173
Test name
Test status
Simulation time 79184450 ps
CPU time 0.93 seconds
Started Jul 24 07:08:56 PM PDT 24
Finished Jul 24 07:08:57 PM PDT 24
Peak memory 200536 kb
Host smart-803c4b61-8ce9-4ffc-82b2-ebb412c3bfc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660979624 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clk
mgr_alert_test.3660979624
Directory /workspace/27.clkmgr_alert_test/latest

Test location /workspace/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.776255618
Short name T728
Test name
Test status
Simulation time 17697555 ps
CPU time 0.75 seconds
Started Jul 24 07:08:56 PM PDT 24
Finished Jul 24 07:08:57 PM PDT 24
Peak memory 200424 kb
Host smart-cfaa5b89-e67e-4ef9-b3d6-6d02d1f926b6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776255618 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_clk_handshake_intersig_mubi.776255618
Directory /workspace/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_clk_status.1850183570
Short name T503
Test name
Test status
Simulation time 20571135 ps
CPU time 0.76 seconds
Started Jul 24 07:09:00 PM PDT 24
Finished Jul 24 07:09:01 PM PDT 24
Peak memory 199664 kb
Host smart-3b56f52c-0529-4fc0-aa82-1c6234e86f21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850183570 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.1850183570
Directory /workspace/27.clkmgr_clk_status/latest

Test location /workspace/coverage/default/27.clkmgr_div_intersig_mubi.3522289200
Short name T219
Test name
Test status
Simulation time 33689305 ps
CPU time 0.78 seconds
Started Jul 24 07:08:55 PM PDT 24
Finished Jul 24 07:09:01 PM PDT 24
Peak memory 200504 kb
Host smart-024afd51-f69a-4c11-a8f7-910a113ea3ef
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522289200 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_div_intersig_mubi.3522289200
Directory /workspace/27.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_extclk.1770988371
Short name T615
Test name
Test status
Simulation time 122221927 ps
CPU time 1.08 seconds
Started Jul 24 07:08:56 PM PDT 24
Finished Jul 24 07:08:58 PM PDT 24
Peak memory 200460 kb
Host smart-881d515b-0fe1-4cf9-886a-c504e51bd71c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770988371 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.1770988371
Directory /workspace/27.clkmgr_extclk/latest

Test location /workspace/coverage/default/27.clkmgr_frequency.103406539
Short name T432
Test name
Test status
Simulation time 2478914599 ps
CPU time 10.66 seconds
Started Jul 24 07:08:56 PM PDT 24
Finished Jul 24 07:09:07 PM PDT 24
Peak memory 200716 kb
Host smart-d7d964a7-cadc-4541-bc0e-2ed6e14d9f84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103406539 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.103406539
Directory /workspace/27.clkmgr_frequency/latest

Test location /workspace/coverage/default/27.clkmgr_frequency_timeout.1223236779
Short name T753
Test name
Test status
Simulation time 1340053415 ps
CPU time 10.04 seconds
Started Jul 24 07:08:58 PM PDT 24
Finished Jul 24 07:09:08 PM PDT 24
Peak memory 200560 kb
Host smart-460e5586-e61c-41b5-948a-467e06d49d40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223236779 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_t
imeout.1223236779
Directory /workspace/27.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/27.clkmgr_idle_intersig_mubi.3926581541
Short name T269
Test name
Test status
Simulation time 22806673 ps
CPU time 0.84 seconds
Started Jul 24 07:08:53 PM PDT 24
Finished Jul 24 07:08:54 PM PDT 24
Peak memory 200364 kb
Host smart-79b7ed44-6e84-441c-9e16-237313241200
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926581541 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_idle_intersig_mubi.3926581541
Directory /workspace/27.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.3376469252
Short name T404
Test name
Test status
Simulation time 31907331 ps
CPU time 0.8 seconds
Started Jul 24 07:08:58 PM PDT 24
Finished Jul 24 07:08:59 PM PDT 24
Peak memory 200416 kb
Host smart-b50ccfb5-07b4-4ba6-a65d-9c124e402075
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376469252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.clkmgr_lc_clk_byp_req_intersig_mubi.3376469252
Directory /workspace/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.1729947678
Short name T431
Test name
Test status
Simulation time 67844042 ps
CPU time 0.9 seconds
Started Jul 24 07:08:55 PM PDT 24
Finished Jul 24 07:08:56 PM PDT 24
Peak memory 200436 kb
Host smart-6cb24e98-12a0-4ad1-becf-c882124a914c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729947678 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.clkmgr_lc_ctrl_intersig_mubi.1729947678
Directory /workspace/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_peri.602883752
Short name T643
Test name
Test status
Simulation time 71917397 ps
CPU time 0.92 seconds
Started Jul 24 07:08:56 PM PDT 24
Finished Jul 24 07:08:57 PM PDT 24
Peak memory 200440 kb
Host smart-6b147be2-bffb-4338-bde3-aa2a5331f55d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602883752 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.602883752
Directory /workspace/27.clkmgr_peri/latest

Test location /workspace/coverage/default/27.clkmgr_regwen.2426946112
Short name T793
Test name
Test status
Simulation time 2086226966 ps
CPU time 6.75 seconds
Started Jul 24 07:08:56 PM PDT 24
Finished Jul 24 07:09:03 PM PDT 24
Peak memory 200564 kb
Host smart-5741bcfe-c04a-4767-9be5-b6ace277cd1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426946112 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.2426946112
Directory /workspace/27.clkmgr_regwen/latest

Test location /workspace/coverage/default/27.clkmgr_smoke.616198996
Short name T743
Test name
Test status
Simulation time 23900850 ps
CPU time 0.88 seconds
Started Jul 24 07:08:59 PM PDT 24
Finished Jul 24 07:09:00 PM PDT 24
Peak memory 200392 kb
Host smart-dbb9f61a-2caa-42d3-9951-951baa22272c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616198996 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.616198996
Directory /workspace/27.clkmgr_smoke/latest

Test location /workspace/coverage/default/27.clkmgr_stress_all.893493015
Short name T336
Test name
Test status
Simulation time 2223921711 ps
CPU time 16.9 seconds
Started Jul 24 07:08:54 PM PDT 24
Finished Jul 24 07:09:11 PM PDT 24
Peak memory 200800 kb
Host smart-14feb869-5dc2-434d-9862-f69c8629c82b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893493015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_stress_all.893493015
Directory /workspace/27.clkmgr_stress_all/latest

Test location /workspace/coverage/default/27.clkmgr_trans.2972087528
Short name T779
Test name
Test status
Simulation time 28203251 ps
CPU time 0.91 seconds
Started Jul 24 07:08:58 PM PDT 24
Finished Jul 24 07:08:59 PM PDT 24
Peak memory 200524 kb
Host smart-a27b6457-b7a2-40a1-95e3-bf390d09c45d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972087528 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.2972087528
Directory /workspace/27.clkmgr_trans/latest

Test location /workspace/coverage/default/28.clkmgr_alert_test.306008876
Short name T606
Test name
Test status
Simulation time 343204926 ps
CPU time 1.75 seconds
Started Jul 24 07:09:15 PM PDT 24
Finished Jul 24 07:09:17 PM PDT 24
Peak memory 200532 kb
Host smart-89df32c9-36b9-4b07-9e3d-97cfb896077c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306008876 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkm
gr_alert_test.306008876
Directory /workspace/28.clkmgr_alert_test/latest

Test location /workspace/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.535214842
Short name T550
Test name
Test status
Simulation time 75534701 ps
CPU time 1.01 seconds
Started Jul 24 07:09:13 PM PDT 24
Finished Jul 24 07:09:14 PM PDT 24
Peak memory 200496 kb
Host smart-cb70584b-d249-4b5c-8c9e-eca8d88f33f7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535214842 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_clk_handshake_intersig_mubi.535214842
Directory /workspace/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_clk_status.251604535
Short name T815
Test name
Test status
Simulation time 135004634 ps
CPU time 1.01 seconds
Started Jul 24 07:09:16 PM PDT 24
Finished Jul 24 07:09:17 PM PDT 24
Peak memory 200392 kb
Host smart-dba683f8-0d79-4e22-8633-e0a8fea5ec57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251604535 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.251604535
Directory /workspace/28.clkmgr_clk_status/latest

Test location /workspace/coverage/default/28.clkmgr_div_intersig_mubi.2486313974
Short name T258
Test name
Test status
Simulation time 58218634 ps
CPU time 1 seconds
Started Jul 24 07:09:11 PM PDT 24
Finished Jul 24 07:09:12 PM PDT 24
Peak memory 200476 kb
Host smart-9e007489-ea19-45e2-b904-4de76e642c6f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486313974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_div_intersig_mubi.2486313974
Directory /workspace/28.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_extclk.1318952778
Short name T228
Test name
Test status
Simulation time 143097126 ps
CPU time 1.16 seconds
Started Jul 24 07:08:57 PM PDT 24
Finished Jul 24 07:08:58 PM PDT 24
Peak memory 200440 kb
Host smart-653cbcc7-25d1-4e77-93a0-244e6fba2132
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318952778 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.1318952778
Directory /workspace/28.clkmgr_extclk/latest

Test location /workspace/coverage/default/28.clkmgr_frequency.486779504
Short name T593
Test name
Test status
Simulation time 2355452303 ps
CPU time 17.73 seconds
Started Jul 24 07:09:12 PM PDT 24
Finished Jul 24 07:09:30 PM PDT 24
Peak memory 200736 kb
Host smart-6f24660c-fe29-451a-8edc-6841a8117e2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486779504 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.486779504
Directory /workspace/28.clkmgr_frequency/latest

Test location /workspace/coverage/default/28.clkmgr_frequency_timeout.2090250685
Short name T646
Test name
Test status
Simulation time 1223920301 ps
CPU time 6.63 seconds
Started Jul 24 07:09:12 PM PDT 24
Finished Jul 24 07:09:18 PM PDT 24
Peak memory 200484 kb
Host smart-24be1098-7cdd-4e10-98ff-7fa48b85ac1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090250685 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_t
imeout.2090250685
Directory /workspace/28.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/28.clkmgr_idle_intersig_mubi.3775080590
Short name T275
Test name
Test status
Simulation time 34959167 ps
CPU time 0.82 seconds
Started Jul 24 07:09:06 PM PDT 24
Finished Jul 24 07:09:07 PM PDT 24
Peak memory 200476 kb
Host smart-842dc79c-a275-4172-aaef-58833b527e10
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775080590 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_idle_intersig_mubi.3775080590
Directory /workspace/28.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.2869308491
Short name T359
Test name
Test status
Simulation time 34384850 ps
CPU time 0.85 seconds
Started Jul 24 07:09:00 PM PDT 24
Finished Jul 24 07:09:06 PM PDT 24
Peak memory 200468 kb
Host smart-5e03eb01-e466-4552-8d3b-7fcb1d364ee7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869308491 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.clkmgr_lc_clk_byp_req_intersig_mubi.2869308491
Directory /workspace/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.1499398977
Short name T748
Test name
Test status
Simulation time 24934871 ps
CPU time 0.88 seconds
Started Jul 24 07:09:03 PM PDT 24
Finished Jul 24 07:09:04 PM PDT 24
Peak memory 200464 kb
Host smart-5c115719-118c-46ef-bb2c-d5177c9298ee
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499398977 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.clkmgr_lc_ctrl_intersig_mubi.1499398977
Directory /workspace/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_peri.1379619160
Short name T379
Test name
Test status
Simulation time 27260341 ps
CPU time 0.8 seconds
Started Jul 24 07:09:01 PM PDT 24
Finished Jul 24 07:09:02 PM PDT 24
Peak memory 200488 kb
Host smart-206726cc-669e-4529-8b3b-907604233807
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379619160 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.1379619160
Directory /workspace/28.clkmgr_peri/latest

Test location /workspace/coverage/default/28.clkmgr_regwen.473375078
Short name T393
Test name
Test status
Simulation time 1526010890 ps
CPU time 5.26 seconds
Started Jul 24 07:09:01 PM PDT 24
Finished Jul 24 07:09:06 PM PDT 24
Peak memory 200712 kb
Host smart-2522c492-0a06-493f-ad10-e615b5c31216
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473375078 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.473375078
Directory /workspace/28.clkmgr_regwen/latest

Test location /workspace/coverage/default/28.clkmgr_smoke.1175178960
Short name T308
Test name
Test status
Simulation time 19602022 ps
CPU time 0.87 seconds
Started Jul 24 07:09:12 PM PDT 24
Finished Jul 24 07:09:13 PM PDT 24
Peak memory 200336 kb
Host smart-72ff5961-047b-4495-82ad-76dd59387982
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175178960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.1175178960
Directory /workspace/28.clkmgr_smoke/latest

Test location /workspace/coverage/default/28.clkmgr_stress_all.941345506
Short name T450
Test name
Test status
Simulation time 5019437070 ps
CPU time 38.64 seconds
Started Jul 24 07:09:02 PM PDT 24
Finished Jul 24 07:09:41 PM PDT 24
Peak memory 200784 kb
Host smart-f167ae84-6a16-46c9-a651-736d164d7861
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941345506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_stress_all.941345506
Directory /workspace/28.clkmgr_stress_all/latest

Test location /workspace/coverage/default/28.clkmgr_trans.3310853755
Short name T821
Test name
Test status
Simulation time 42789258 ps
CPU time 0.96 seconds
Started Jul 24 07:09:13 PM PDT 24
Finished Jul 24 07:09:14 PM PDT 24
Peak memory 200456 kb
Host smart-2831e082-01bb-4583-b479-db89e54d6187
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310853755 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.3310853755
Directory /workspace/28.clkmgr_trans/latest

Test location /workspace/coverage/default/29.clkmgr_alert_test.3217943519
Short name T740
Test name
Test status
Simulation time 45983927 ps
CPU time 1.05 seconds
Started Jul 24 07:09:03 PM PDT 24
Finished Jul 24 07:09:04 PM PDT 24
Peak memory 200552 kb
Host smart-a8d14d35-93f4-42cf-b02b-0268f354b80a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217943519 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clk
mgr_alert_test.3217943519
Directory /workspace/29.clkmgr_alert_test/latest

Test location /workspace/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.2711677920
Short name T806
Test name
Test status
Simulation time 12322570 ps
CPU time 0.73 seconds
Started Jul 24 07:09:18 PM PDT 24
Finished Jul 24 07:09:19 PM PDT 24
Peak memory 200472 kb
Host smart-c296c227-37d2-49f0-a3c4-3640c417112f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711677920 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_clk_handshake_intersig_mubi.2711677920
Directory /workspace/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_clk_status.3159071010
Short name T321
Test name
Test status
Simulation time 14664678 ps
CPU time 0.74 seconds
Started Jul 24 07:09:10 PM PDT 24
Finished Jul 24 07:09:11 PM PDT 24
Peak memory 199716 kb
Host smart-5dee5db7-a6b0-4521-b63f-894c2029ef3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159071010 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.3159071010
Directory /workspace/29.clkmgr_clk_status/latest

Test location /workspace/coverage/default/29.clkmgr_div_intersig_mubi.4027582806
Short name T510
Test name
Test status
Simulation time 53480801 ps
CPU time 0.99 seconds
Started Jul 24 07:09:13 PM PDT 24
Finished Jul 24 07:09:14 PM PDT 24
Peak memory 200408 kb
Host smart-6a92a166-ffa2-44fc-a200-99fbfeed45c5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027582806 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_div_intersig_mubi.4027582806
Directory /workspace/29.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_extclk.1182500558
Short name T353
Test name
Test status
Simulation time 95340519 ps
CPU time 1.14 seconds
Started Jul 24 07:09:19 PM PDT 24
Finished Jul 24 07:09:20 PM PDT 24
Peak memory 200464 kb
Host smart-369301ff-8a88-44fe-8c9d-73bd3b1186b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182500558 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.1182500558
Directory /workspace/29.clkmgr_extclk/latest

Test location /workspace/coverage/default/29.clkmgr_frequency.3492733290
Short name T600
Test name
Test status
Simulation time 2428207395 ps
CPU time 11.35 seconds
Started Jul 24 07:09:04 PM PDT 24
Finished Jul 24 07:09:15 PM PDT 24
Peak memory 200736 kb
Host smart-6efb101f-cba4-47f7-aba8-55789b9ad026
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492733290 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.3492733290
Directory /workspace/29.clkmgr_frequency/latest

Test location /workspace/coverage/default/29.clkmgr_frequency_timeout.3542903870
Short name T472
Test name
Test status
Simulation time 667067962 ps
CPU time 3.47 seconds
Started Jul 24 07:09:14 PM PDT 24
Finished Jul 24 07:09:18 PM PDT 24
Peak memory 200524 kb
Host smart-e9f9c392-c214-4c7a-9c8c-0ab146ab0948
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542903870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_t
imeout.3542903870
Directory /workspace/29.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/29.clkmgr_idle_intersig_mubi.700763905
Short name T505
Test name
Test status
Simulation time 101924335 ps
CPU time 1.23 seconds
Started Jul 24 07:09:00 PM PDT 24
Finished Jul 24 07:09:01 PM PDT 24
Peak memory 200412 kb
Host smart-b746da8d-b157-4803-8871-1c15c2e531b1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700763905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.clkmgr_idle_intersig_mubi.700763905
Directory /workspace/29.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.3559180049
Short name T208
Test name
Test status
Simulation time 29405149 ps
CPU time 0.79 seconds
Started Jul 24 07:09:13 PM PDT 24
Finished Jul 24 07:09:14 PM PDT 24
Peak memory 200464 kb
Host smart-f8924d4f-a3d8-427d-88cf-49ac7e87710a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559180049 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.clkmgr_lc_clk_byp_req_intersig_mubi.3559180049
Directory /workspace/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.1932793915
Short name T55
Test name
Test status
Simulation time 91903890 ps
CPU time 1.05 seconds
Started Jul 24 07:08:59 PM PDT 24
Finished Jul 24 07:09:00 PM PDT 24
Peak memory 200472 kb
Host smart-63acbe8f-1398-4a9e-bc74-731641c83029
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932793915 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.clkmgr_lc_ctrl_intersig_mubi.1932793915
Directory /workspace/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_peri.3091802762
Short name T299
Test name
Test status
Simulation time 21127891 ps
CPU time 0.79 seconds
Started Jul 24 07:09:19 PM PDT 24
Finished Jul 24 07:09:20 PM PDT 24
Peak memory 200424 kb
Host smart-434492fd-b6ed-4dfc-a695-5bdfc8a4dc81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091802762 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.3091802762
Directory /workspace/29.clkmgr_peri/latest

Test location /workspace/coverage/default/29.clkmgr_regwen.800704686
Short name T737
Test name
Test status
Simulation time 820864204 ps
CPU time 4.82 seconds
Started Jul 24 07:09:14 PM PDT 24
Finished Jul 24 07:09:19 PM PDT 24
Peak memory 200668 kb
Host smart-daa6b31e-6bf1-4df0-aa09-b8755f80d68d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800704686 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.800704686
Directory /workspace/29.clkmgr_regwen/latest

Test location /workspace/coverage/default/29.clkmgr_smoke.3959338143
Short name T613
Test name
Test status
Simulation time 69168740 ps
CPU time 1 seconds
Started Jul 24 07:09:12 PM PDT 24
Finished Jul 24 07:09:14 PM PDT 24
Peak memory 200416 kb
Host smart-73e5e411-2c54-495d-bc9d-22b486952ca3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959338143 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.3959338143
Directory /workspace/29.clkmgr_smoke/latest

Test location /workspace/coverage/default/29.clkmgr_stress_all.3568369705
Short name T493
Test name
Test status
Simulation time 10466742378 ps
CPU time 43.69 seconds
Started Jul 24 07:09:02 PM PDT 24
Finished Jul 24 07:09:46 PM PDT 24
Peak memory 200812 kb
Host smart-5bd6c5c5-884d-4135-b258-68ce5ac0a194
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568369705 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_stress_all.3568369705
Directory /workspace/29.clkmgr_stress_all/latest

Test location /workspace/coverage/default/29.clkmgr_trans.1063963139
Short name T186
Test name
Test status
Simulation time 31694257 ps
CPU time 0.98 seconds
Started Jul 24 07:09:02 PM PDT 24
Finished Jul 24 07:09:03 PM PDT 24
Peak memory 200420 kb
Host smart-44be7ad9-b477-4a5b-b53c-1de84b953250
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063963139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.1063963139
Directory /workspace/29.clkmgr_trans/latest

Test location /workspace/coverage/default/3.clkmgr_alert_test.740285587
Short name T574
Test name
Test status
Simulation time 54637129 ps
CPU time 0.88 seconds
Started Jul 24 07:07:54 PM PDT 24
Finished Jul 24 07:07:55 PM PDT 24
Peak memory 200544 kb
Host smart-6daa417c-f370-4057-a006-062a5f008f98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740285587 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmg
r_alert_test.740285587
Directory /workspace/3.clkmgr_alert_test/latest

Test location /workspace/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.1024812284
Short name T239
Test name
Test status
Simulation time 79549982 ps
CPU time 1.12 seconds
Started Jul 24 07:07:56 PM PDT 24
Finished Jul 24 07:07:58 PM PDT 24
Peak memory 200688 kb
Host smart-57de6e3c-b28e-404d-98a7-d39e6654c610
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024812284 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_clk_handshake_intersig_mubi.1024812284
Directory /workspace/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_clk_status.3433005004
Short name T156
Test name
Test status
Simulation time 35005259 ps
CPU time 0.77 seconds
Started Jul 24 07:08:00 PM PDT 24
Finished Jul 24 07:08:01 PM PDT 24
Peak memory 199640 kb
Host smart-7709b7fe-b026-42ee-87c0-38d0ff03d932
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433005004 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.3433005004
Directory /workspace/3.clkmgr_clk_status/latest

Test location /workspace/coverage/default/3.clkmgr_div_intersig_mubi.2765199107
Short name T76
Test name
Test status
Simulation time 101257360 ps
CPU time 1.15 seconds
Started Jul 24 07:07:56 PM PDT 24
Finished Jul 24 07:07:58 PM PDT 24
Peak memory 200436 kb
Host smart-f0c3ddda-f2da-422c-af2e-63e31dc4c981
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765199107 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_div_intersig_mubi.2765199107
Directory /workspace/3.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_extclk.3236738543
Short name T596
Test name
Test status
Simulation time 31005622 ps
CPU time 0.96 seconds
Started Jul 24 07:07:55 PM PDT 24
Finished Jul 24 07:07:56 PM PDT 24
Peak memory 200464 kb
Host smart-2e43085a-3eaf-4f26-a884-34ca30ee6e61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236738543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.3236738543
Directory /workspace/3.clkmgr_extclk/latest

Test location /workspace/coverage/default/3.clkmgr_frequency.663188352
Short name T546
Test name
Test status
Simulation time 1404620979 ps
CPU time 8.03 seconds
Started Jul 24 07:07:59 PM PDT 24
Finished Jul 24 07:08:07 PM PDT 24
Peak memory 200504 kb
Host smart-4b5c16fc-e466-49f4-a11d-91775f385ace
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663188352 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.663188352
Directory /workspace/3.clkmgr_frequency/latest

Test location /workspace/coverage/default/3.clkmgr_frequency_timeout.3449521561
Short name T33
Test name
Test status
Simulation time 862947879 ps
CPU time 5.17 seconds
Started Jul 24 07:07:55 PM PDT 24
Finished Jul 24 07:08:01 PM PDT 24
Peak memory 200556 kb
Host smart-356e7e68-5b94-49d6-b21c-4a4103fd3d12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449521561 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_ti
meout.3449521561
Directory /workspace/3.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/3.clkmgr_idle_intersig_mubi.534766422
Short name T434
Test name
Test status
Simulation time 120644030 ps
CPU time 1.3 seconds
Started Jul 24 07:07:54 PM PDT 24
Finished Jul 24 07:07:56 PM PDT 24
Peak memory 200392 kb
Host smart-acd0c116-e6de-4004-b368-5a840db5b635
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534766422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.clkmgr_idle_intersig_mubi.534766422
Directory /workspace/3.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.3654474799
Short name T684
Test name
Test status
Simulation time 22778426 ps
CPU time 0.83 seconds
Started Jul 24 07:07:56 PM PDT 24
Finished Jul 24 07:07:57 PM PDT 24
Peak memory 200488 kb
Host smart-2eb9b63e-f935-4b6f-8d10-423ef98538ef
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654474799 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_lc_clk_byp_req_intersig_mubi.3654474799
Directory /workspace/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.3672159069
Short name T792
Test name
Test status
Simulation time 42017641 ps
CPU time 0.87 seconds
Started Jul 24 07:08:03 PM PDT 24
Finished Jul 24 07:08:04 PM PDT 24
Peak memory 200300 kb
Host smart-8567d9db-d352-4a4e-af1a-ec66890f6cb4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672159069 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_lc_ctrl_intersig_mubi.3672159069
Directory /workspace/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_peri.932932053
Short name T825
Test name
Test status
Simulation time 18250291 ps
CPU time 0.79 seconds
Started Jul 24 07:08:00 PM PDT 24
Finished Jul 24 07:08:01 PM PDT 24
Peak memory 200452 kb
Host smart-baa438ff-23dc-42b5-81db-82fc73942368
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932932053 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.932932053
Directory /workspace/3.clkmgr_peri/latest

Test location /workspace/coverage/default/3.clkmgr_regwen.734440663
Short name T205
Test name
Test status
Simulation time 938961271 ps
CPU time 4.46 seconds
Started Jul 24 07:07:55 PM PDT 24
Finished Jul 24 07:08:00 PM PDT 24
Peak memory 200648 kb
Host smart-0c1efd6f-b64b-48a5-82ff-2a94463146d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734440663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.734440663
Directory /workspace/3.clkmgr_regwen/latest

Test location /workspace/coverage/default/3.clkmgr_sec_cm.1954117762
Short name T44
Test name
Test status
Simulation time 299920735 ps
CPU time 3.11 seconds
Started Jul 24 07:08:03 PM PDT 24
Finished Jul 24 07:08:06 PM PDT 24
Peak memory 217080 kb
Host smart-12d38dbc-b1ea-4cfb-afc9-59a6119188c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954117762 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmg
r_sec_cm.1954117762
Directory /workspace/3.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/3.clkmgr_smoke.1197255658
Short name T696
Test name
Test status
Simulation time 118206716 ps
CPU time 1.11 seconds
Started Jul 24 07:08:00 PM PDT 24
Finished Jul 24 07:08:02 PM PDT 24
Peak memory 200352 kb
Host smart-952dc8cf-af66-47a9-bbdf-a3506b5552ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197255658 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.1197255658
Directory /workspace/3.clkmgr_smoke/latest

Test location /workspace/coverage/default/3.clkmgr_stress_all.3957131484
Short name T532
Test name
Test status
Simulation time 5271435158 ps
CPU time 37 seconds
Started Jul 24 07:07:56 PM PDT 24
Finished Jul 24 07:08:33 PM PDT 24
Peak memory 200708 kb
Host smart-19addb75-9050-49a5-a900-646b02fb1728
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957131484 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_stress_all.3957131484
Directory /workspace/3.clkmgr_stress_all/latest

Test location /workspace/coverage/default/3.clkmgr_trans.692020925
Short name T709
Test name
Test status
Simulation time 78069178 ps
CPU time 1.13 seconds
Started Jul 24 07:07:59 PM PDT 24
Finished Jul 24 07:08:00 PM PDT 24
Peak memory 200472 kb
Host smart-28153843-2a0e-45f0-99ad-3517ea3332dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692020925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.692020925
Directory /workspace/3.clkmgr_trans/latest

Test location /workspace/coverage/default/30.clkmgr_alert_test.1430557975
Short name T229
Test name
Test status
Simulation time 39622257 ps
CPU time 0.86 seconds
Started Jul 24 07:09:13 PM PDT 24
Finished Jul 24 07:09:15 PM PDT 24
Peak memory 200480 kb
Host smart-9218cf2e-27f5-4726-95b2-a55cb14740e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430557975 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clk
mgr_alert_test.1430557975
Directory /workspace/30.clkmgr_alert_test/latest

Test location /workspace/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.182452124
Short name T560
Test name
Test status
Simulation time 31791678 ps
CPU time 1 seconds
Started Jul 24 07:09:19 PM PDT 24
Finished Jul 24 07:09:20 PM PDT 24
Peak memory 200696 kb
Host smart-a29f92d4-baae-466a-8d54-a103d59f75b4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182452124 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_clk_handshake_intersig_mubi.182452124
Directory /workspace/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_clk_status.2662353045
Short name T438
Test name
Test status
Simulation time 50086491 ps
CPU time 0.83 seconds
Started Jul 24 07:09:02 PM PDT 24
Finished Jul 24 07:09:03 PM PDT 24
Peak memory 200392 kb
Host smart-55533618-33b0-4f36-8f25-d94636f6e27c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662353045 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.2662353045
Directory /workspace/30.clkmgr_clk_status/latest

Test location /workspace/coverage/default/30.clkmgr_div_intersig_mubi.2999020953
Short name T351
Test name
Test status
Simulation time 19216992 ps
CPU time 0.82 seconds
Started Jul 24 07:09:20 PM PDT 24
Finished Jul 24 07:09:21 PM PDT 24
Peak memory 200492 kb
Host smart-70ff04eb-5d2a-4e39-96d7-06a3f7ecc6fd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999020953 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_div_intersig_mubi.2999020953
Directory /workspace/30.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_extclk.1706288560
Short name T745
Test name
Test status
Simulation time 78313985 ps
CPU time 1.03 seconds
Started Jul 24 07:09:14 PM PDT 24
Finished Jul 24 07:09:15 PM PDT 24
Peak memory 200472 kb
Host smart-884b7775-c1c4-4cac-8b9b-7bd6673b9d38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706288560 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.1706288560
Directory /workspace/30.clkmgr_extclk/latest

Test location /workspace/coverage/default/30.clkmgr_frequency.1327029624
Short name T824
Test name
Test status
Simulation time 708879712 ps
CPU time 3.74 seconds
Started Jul 24 07:09:13 PM PDT 24
Finished Jul 24 07:09:17 PM PDT 24
Peak memory 200692 kb
Host smart-c935f40b-242f-45b3-86eb-989bf1d710a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327029624 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.1327029624
Directory /workspace/30.clkmgr_frequency/latest

Test location /workspace/coverage/default/30.clkmgr_frequency_timeout.4180964936
Short name T633
Test name
Test status
Simulation time 861228900 ps
CPU time 6.81 seconds
Started Jul 24 07:09:08 PM PDT 24
Finished Jul 24 07:09:15 PM PDT 24
Peak memory 200496 kb
Host smart-566ea51a-11cb-4c08-a5eb-d4bfccd8569e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180964936 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_t
imeout.4180964936
Directory /workspace/30.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/30.clkmgr_idle_intersig_mubi.1522494411
Short name T360
Test name
Test status
Simulation time 62595270 ps
CPU time 1 seconds
Started Jul 24 07:09:16 PM PDT 24
Finished Jul 24 07:09:17 PM PDT 24
Peak memory 200472 kb
Host smart-ffdaecb2-5614-42cd-be22-c0132d57dde6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522494411 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_idle_intersig_mubi.1522494411
Directory /workspace/30.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.1915660989
Short name T257
Test name
Test status
Simulation time 21644596 ps
CPU time 0.82 seconds
Started Jul 24 07:09:18 PM PDT 24
Finished Jul 24 07:09:19 PM PDT 24
Peak memory 200412 kb
Host smart-255208d4-9b00-4a43-ba29-b5de45e1eaba
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915660989 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.clkmgr_lc_clk_byp_req_intersig_mubi.1915660989
Directory /workspace/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.3075967756
Short name T436
Test name
Test status
Simulation time 20734890 ps
CPU time 0.86 seconds
Started Jul 24 07:09:15 PM PDT 24
Finished Jul 24 07:09:16 PM PDT 24
Peak memory 200520 kb
Host smart-d2090244-0f26-453d-b226-daf7787a7c58
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075967756 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.clkmgr_lc_ctrl_intersig_mubi.3075967756
Directory /workspace/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_peri.2082771261
Short name T6
Test name
Test status
Simulation time 44419338 ps
CPU time 0.9 seconds
Started Jul 24 07:09:00 PM PDT 24
Finished Jul 24 07:09:01 PM PDT 24
Peak memory 200344 kb
Host smart-105b42a4-49b5-4f52-a442-65dcd3f4b611
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082771261 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.2082771261
Directory /workspace/30.clkmgr_peri/latest

Test location /workspace/coverage/default/30.clkmgr_regwen.156255055
Short name T539
Test name
Test status
Simulation time 520330349 ps
CPU time 3.49 seconds
Started Jul 24 07:09:21 PM PDT 24
Finished Jul 24 07:09:25 PM PDT 24
Peak memory 200644 kb
Host smart-3ada6188-33f6-45bc-9825-3661c1ccad94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156255055 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.156255055
Directory /workspace/30.clkmgr_regwen/latest

Test location /workspace/coverage/default/30.clkmgr_smoke.3961138718
Short name T297
Test name
Test status
Simulation time 67134770 ps
CPU time 0.95 seconds
Started Jul 24 07:09:15 PM PDT 24
Finished Jul 24 07:09:16 PM PDT 24
Peak memory 200428 kb
Host smart-c8a2b6cf-4030-4acb-b32a-f0f2f5b5dc00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961138718 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.3961138718
Directory /workspace/30.clkmgr_smoke/latest

Test location /workspace/coverage/default/30.clkmgr_stress_all.2078301605
Short name T140
Test name
Test status
Simulation time 11622279520 ps
CPU time 43.96 seconds
Started Jul 24 07:09:21 PM PDT 24
Finished Jul 24 07:10:06 PM PDT 24
Peak memory 200788 kb
Host smart-a897fb52-ad3c-4a37-95d3-05be68c0d6bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078301605 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_stress_all.2078301605
Directory /workspace/30.clkmgr_stress_all/latest

Test location /workspace/coverage/default/30.clkmgr_stress_all_with_rand_reset.2336965862
Short name T69
Test name
Test status
Simulation time 45789100158 ps
CPU time 300.98 seconds
Started Jul 24 07:09:19 PM PDT 24
Finished Jul 24 07:14:20 PM PDT 24
Peak memory 209112 kb
Host smart-73eed558-47a6-4bba-80b9-b1fda332e6f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2336965862 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all_with_rand_reset.2336965862
Directory /workspace/30.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.clkmgr_trans.2833491988
Short name T616
Test name
Test status
Simulation time 16499019 ps
CPU time 0.78 seconds
Started Jul 24 07:09:13 PM PDT 24
Finished Jul 24 07:09:14 PM PDT 24
Peak memory 200480 kb
Host smart-42cf1ca3-94d2-4493-b9f8-6e2788bff618
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833491988 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.2833491988
Directory /workspace/30.clkmgr_trans/latest

Test location /workspace/coverage/default/31.clkmgr_alert_test.2376058219
Short name T36
Test name
Test status
Simulation time 16342128 ps
CPU time 0.74 seconds
Started Jul 24 07:09:15 PM PDT 24
Finished Jul 24 07:09:16 PM PDT 24
Peak memory 200548 kb
Host smart-d82597da-c3f9-464e-9aa4-4a08e749320e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376058219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clk
mgr_alert_test.2376058219
Directory /workspace/31.clkmgr_alert_test/latest

Test location /workspace/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.3086842389
Short name T471
Test name
Test status
Simulation time 18404091 ps
CPU time 0.8 seconds
Started Jul 24 07:09:13 PM PDT 24
Finished Jul 24 07:09:14 PM PDT 24
Peak memory 200480 kb
Host smart-48731842-9811-4920-aea3-d35300cfe55d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086842389 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_clk_handshake_intersig_mubi.3086842389
Directory /workspace/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_clk_status.1497367245
Short name T288
Test name
Test status
Simulation time 25539518 ps
CPU time 0.74 seconds
Started Jul 24 07:09:17 PM PDT 24
Finished Jul 24 07:09:18 PM PDT 24
Peak memory 200380 kb
Host smart-cd531c7d-7ccc-4ce3-9ef8-d467e5160069
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497367245 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.1497367245
Directory /workspace/31.clkmgr_clk_status/latest

Test location /workspace/coverage/default/31.clkmgr_div_intersig_mubi.1525234619
Short name T582
Test name
Test status
Simulation time 12910985 ps
CPU time 0.75 seconds
Started Jul 24 07:09:17 PM PDT 24
Finished Jul 24 07:09:18 PM PDT 24
Peak memory 200496 kb
Host smart-303d8db0-2a51-4b25-9785-3c6916c59b5b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525234619 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_div_intersig_mubi.1525234619
Directory /workspace/31.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_extclk.3690429921
Short name T214
Test name
Test status
Simulation time 37253266 ps
CPU time 0.8 seconds
Started Jul 24 07:09:17 PM PDT 24
Finished Jul 24 07:09:18 PM PDT 24
Peak memory 200372 kb
Host smart-448660ad-1a8a-4696-b281-73aa5558fdeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690429921 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.3690429921
Directory /workspace/31.clkmgr_extclk/latest

Test location /workspace/coverage/default/31.clkmgr_frequency.1554691437
Short name T327
Test name
Test status
Simulation time 567294037 ps
CPU time 3.69 seconds
Started Jul 24 07:09:16 PM PDT 24
Finished Jul 24 07:09:20 PM PDT 24
Peak memory 200468 kb
Host smart-237f7bdb-253b-449b-9ea9-e152afed2fad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554691437 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.1554691437
Directory /workspace/31.clkmgr_frequency/latest

Test location /workspace/coverage/default/31.clkmgr_frequency_timeout.3078991208
Short name T738
Test name
Test status
Simulation time 2065130805 ps
CPU time 10.52 seconds
Started Jul 24 07:09:13 PM PDT 24
Finished Jul 24 07:09:24 PM PDT 24
Peak memory 200736 kb
Host smart-c78921a6-7681-440e-a859-62041866102c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078991208 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_t
imeout.3078991208
Directory /workspace/31.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/31.clkmgr_idle_intersig_mubi.1675582446
Short name T726
Test name
Test status
Simulation time 36320452 ps
CPU time 0.91 seconds
Started Jul 24 07:09:13 PM PDT 24
Finished Jul 24 07:09:14 PM PDT 24
Peak memory 200464 kb
Host smart-c37705bd-e3cd-4bca-83c4-0a007aeaa3f8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675582446 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_idle_intersig_mubi.1675582446
Directory /workspace/31.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.1987088808
Short name T502
Test name
Test status
Simulation time 25387936 ps
CPU time 0.74 seconds
Started Jul 24 07:09:14 PM PDT 24
Finished Jul 24 07:09:15 PM PDT 24
Peak memory 200456 kb
Host smart-738fed0b-be0b-4e2b-a957-36d5829b2cf9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987088808 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_clk_byp_req_intersig_mubi.1987088808
Directory /workspace/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.2839382509
Short name T350
Test name
Test status
Simulation time 68537636 ps
CPU time 1.02 seconds
Started Jul 24 07:09:22 PM PDT 24
Finished Jul 24 07:09:24 PM PDT 24
Peak memory 200516 kb
Host smart-f299807e-21a5-4103-aa2a-65b74ada701d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839382509 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_ctrl_intersig_mubi.2839382509
Directory /workspace/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_peri.3298899597
Short name T693
Test name
Test status
Simulation time 21590190 ps
CPU time 0.78 seconds
Started Jul 24 07:09:16 PM PDT 24
Finished Jul 24 07:09:17 PM PDT 24
Peak memory 200468 kb
Host smart-221c9f3f-5624-4ce1-894a-1a58bcbfdcca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298899597 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.3298899597
Directory /workspace/31.clkmgr_peri/latest

Test location /workspace/coverage/default/31.clkmgr_regwen.120626809
Short name T501
Test name
Test status
Simulation time 902439852 ps
CPU time 4.26 seconds
Started Jul 24 07:09:15 PM PDT 24
Finished Jul 24 07:09:19 PM PDT 24
Peak memory 200644 kb
Host smart-53faa45a-db91-46e0-87cd-8f3c4d4a6cfc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120626809 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.120626809
Directory /workspace/31.clkmgr_regwen/latest

Test location /workspace/coverage/default/31.clkmgr_smoke.2997915377
Short name T765
Test name
Test status
Simulation time 47921871 ps
CPU time 0.9 seconds
Started Jul 24 07:09:20 PM PDT 24
Finished Jul 24 07:09:21 PM PDT 24
Peak memory 200428 kb
Host smart-91ab70cf-f0cb-44ff-80bd-a7c202088ebd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997915377 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.2997915377
Directory /workspace/31.clkmgr_smoke/latest

Test location /workspace/coverage/default/31.clkmgr_stress_all.2743623887
Short name T551
Test name
Test status
Simulation time 4336216410 ps
CPU time 28.43 seconds
Started Jul 24 07:09:17 PM PDT 24
Finished Jul 24 07:09:46 PM PDT 24
Peak memory 200984 kb
Host smart-65c1c37d-b3cc-4697-9fc6-4b2b09a902e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743623887 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_stress_all.2743623887
Directory /workspace/31.clkmgr_stress_all/latest

Test location /workspace/coverage/default/31.clkmgr_stress_all_with_rand_reset.2690402374
Short name T492
Test name
Test status
Simulation time 178108128482 ps
CPU time 1029.88 seconds
Started Jul 24 07:09:13 PM PDT 24
Finished Jul 24 07:26:23 PM PDT 24
Peak memory 209088 kb
Host smart-a8e776b5-43bd-421f-98b8-4128e6c9ea78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2690402374 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all_with_rand_reset.2690402374
Directory /workspace/31.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.clkmgr_trans.3382457152
Short name T490
Test name
Test status
Simulation time 40498314 ps
CPU time 1.01 seconds
Started Jul 24 07:09:20 PM PDT 24
Finished Jul 24 07:09:21 PM PDT 24
Peak memory 200480 kb
Host smart-7b1ccdde-c0f3-48c3-a51d-40f4c3c937fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382457152 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.3382457152
Directory /workspace/31.clkmgr_trans/latest

Test location /workspace/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.3854992597
Short name T449
Test name
Test status
Simulation time 23803496 ps
CPU time 0.79 seconds
Started Jul 24 07:09:15 PM PDT 24
Finished Jul 24 07:09:16 PM PDT 24
Peak memory 200496 kb
Host smart-e1aee3b8-ed4f-42b4-b2f7-cacf4346aff6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854992597 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_clk_handshake_intersig_mubi.3854992597
Directory /workspace/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_clk_status.996163048
Short name T783
Test name
Test status
Simulation time 37667822 ps
CPU time 0.75 seconds
Started Jul 24 07:09:20 PM PDT 24
Finished Jul 24 07:09:21 PM PDT 24
Peak memory 199672 kb
Host smart-65aca778-738b-4810-a324-491c00dc1409
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996163048 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.996163048
Directory /workspace/32.clkmgr_clk_status/latest

Test location /workspace/coverage/default/32.clkmgr_div_intersig_mubi.2931775572
Short name T607
Test name
Test status
Simulation time 26324752 ps
CPU time 0.92 seconds
Started Jul 24 07:09:15 PM PDT 24
Finished Jul 24 07:09:16 PM PDT 24
Peak memory 200476 kb
Host smart-8fb7da6b-5706-42f9-9250-d9542cc602fd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931775572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_div_intersig_mubi.2931775572
Directory /workspace/32.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_extclk.4163199060
Short name T144
Test name
Test status
Simulation time 26533049 ps
CPU time 0.92 seconds
Started Jul 24 07:09:16 PM PDT 24
Finished Jul 24 07:09:17 PM PDT 24
Peak memory 200696 kb
Host smart-b46d7679-ba98-464d-b603-11bf1c258c94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163199060 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.4163199060
Directory /workspace/32.clkmgr_extclk/latest

Test location /workspace/coverage/default/32.clkmgr_frequency.2859458974
Short name T661
Test name
Test status
Simulation time 2513853939 ps
CPU time 9.83 seconds
Started Jul 24 07:09:17 PM PDT 24
Finished Jul 24 07:09:27 PM PDT 24
Peak memory 200716 kb
Host smart-a7ea3a96-7647-4a6b-9bc8-04b98e6c999c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859458974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.2859458974
Directory /workspace/32.clkmgr_frequency/latest

Test location /workspace/coverage/default/32.clkmgr_frequency_timeout.3425525769
Short name T807
Test name
Test status
Simulation time 135359221 ps
CPU time 1.5 seconds
Started Jul 24 07:09:19 PM PDT 24
Finished Jul 24 07:09:21 PM PDT 24
Peak memory 200520 kb
Host smart-f46a73ad-9094-4185-9df8-8bc49157d1df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425525769 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_t
imeout.3425525769
Directory /workspace/32.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/32.clkmgr_idle_intersig_mubi.3065256299
Short name T423
Test name
Test status
Simulation time 120776880 ps
CPU time 1.29 seconds
Started Jul 24 07:09:16 PM PDT 24
Finished Jul 24 07:09:18 PM PDT 24
Peak memory 200380 kb
Host smart-41fca199-6361-4dd9-875c-edabd5b7e6a3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065256299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_idle_intersig_mubi.3065256299
Directory /workspace/32.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.3100572244
Short name T145
Test name
Test status
Simulation time 21782045 ps
CPU time 0.84 seconds
Started Jul 24 07:09:20 PM PDT 24
Finished Jul 24 07:09:21 PM PDT 24
Peak memory 200484 kb
Host smart-3dba1160-bfb4-4b5f-95fe-81f3858c1086
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100572244 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.clkmgr_lc_clk_byp_req_intersig_mubi.3100572244
Directory /workspace/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.3639743664
Short name T424
Test name
Test status
Simulation time 67053407 ps
CPU time 1 seconds
Started Jul 24 07:09:21 PM PDT 24
Finished Jul 24 07:09:22 PM PDT 24
Peak memory 200464 kb
Host smart-20698e6e-6088-490b-a525-fa03f4dfb4d9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639743664 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.clkmgr_lc_ctrl_intersig_mubi.3639743664
Directory /workspace/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_peri.3926363485
Short name T285
Test name
Test status
Simulation time 32249356 ps
CPU time 0.77 seconds
Started Jul 24 07:09:18 PM PDT 24
Finished Jul 24 07:09:19 PM PDT 24
Peak memory 200400 kb
Host smart-5a5587b6-faf4-48d8-9efb-c8b58deb71af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926363485 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.3926363485
Directory /workspace/32.clkmgr_peri/latest

Test location /workspace/coverage/default/32.clkmgr_regwen.3874022430
Short name T10
Test name
Test status
Simulation time 208190047 ps
CPU time 1.73 seconds
Started Jul 24 07:09:19 PM PDT 24
Finished Jul 24 07:09:21 PM PDT 24
Peak memory 200372 kb
Host smart-6dc29239-0fb1-4247-8b0a-f1193e45819b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874022430 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.3874022430
Directory /workspace/32.clkmgr_regwen/latest

Test location /workspace/coverage/default/32.clkmgr_smoke.1959520509
Short name T776
Test name
Test status
Simulation time 28115789 ps
CPU time 0.92 seconds
Started Jul 24 07:09:10 PM PDT 24
Finished Jul 24 07:09:11 PM PDT 24
Peak memory 200436 kb
Host smart-4e670e0c-f537-4589-bc98-1091a8383a58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959520509 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.1959520509
Directory /workspace/32.clkmgr_smoke/latest

Test location /workspace/coverage/default/32.clkmgr_stress_all.3795443080
Short name T778
Test name
Test status
Simulation time 1997720066 ps
CPU time 14.66 seconds
Started Jul 24 07:09:16 PM PDT 24
Finished Jul 24 07:09:31 PM PDT 24
Peak memory 200716 kb
Host smart-3cfd9395-60a8-45a3-98d9-525a66273170
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795443080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_stress_all.3795443080
Directory /workspace/32.clkmgr_stress_all/latest

Test location /workspace/coverage/default/32.clkmgr_trans.2384111277
Short name T769
Test name
Test status
Simulation time 41144631 ps
CPU time 0.96 seconds
Started Jul 24 07:09:18 PM PDT 24
Finished Jul 24 07:09:19 PM PDT 24
Peak memory 200504 kb
Host smart-1bd06eba-e4ca-4595-9c40-848b4496311e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384111277 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.2384111277
Directory /workspace/32.clkmgr_trans/latest

Test location /workspace/coverage/default/33.clkmgr_alert_test.2194775678
Short name T558
Test name
Test status
Simulation time 15164266 ps
CPU time 0.81 seconds
Started Jul 24 07:09:17 PM PDT 24
Finished Jul 24 07:09:18 PM PDT 24
Peak memory 200552 kb
Host smart-e1d20e6d-6c49-44ae-9229-7958ed7ae394
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194775678 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clk
mgr_alert_test.2194775678
Directory /workspace/33.clkmgr_alert_test/latest

Test location /workspace/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.3303648200
Short name T802
Test name
Test status
Simulation time 46720584 ps
CPU time 1.01 seconds
Started Jul 24 07:09:25 PM PDT 24
Finished Jul 24 07:09:26 PM PDT 24
Peak memory 200484 kb
Host smart-a4fcce93-80f3-48a3-a3d1-cce16c63ce3b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303648200 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_clk_handshake_intersig_mubi.3303648200
Directory /workspace/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_clk_status.2009808676
Short name T162
Test name
Test status
Simulation time 15925444 ps
CPU time 0.74 seconds
Started Jul 24 07:09:22 PM PDT 24
Finished Jul 24 07:09:23 PM PDT 24
Peak memory 199636 kb
Host smart-e06be6a7-b329-4a5e-bf40-8cf66fbc730d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009808676 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.2009808676
Directory /workspace/33.clkmgr_clk_status/latest

Test location /workspace/coverage/default/33.clkmgr_div_intersig_mubi.637301962
Short name T426
Test name
Test status
Simulation time 25014805 ps
CPU time 0.88 seconds
Started Jul 24 07:09:23 PM PDT 24
Finished Jul 24 07:09:24 PM PDT 24
Peak memory 200488 kb
Host smart-e6fa73ba-50bc-4876-bc38-a167c80b069a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637301962 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.clkmgr_div_intersig_mubi.637301962
Directory /workspace/33.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_extclk.2246117704
Short name T580
Test name
Test status
Simulation time 24486550 ps
CPU time 0.88 seconds
Started Jul 24 07:09:13 PM PDT 24
Finished Jul 24 07:09:15 PM PDT 24
Peak memory 200440 kb
Host smart-40b2e1d1-6edb-45a4-a51b-ae3fae4dfe99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246117704 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.2246117704
Directory /workspace/33.clkmgr_extclk/latest

Test location /workspace/coverage/default/33.clkmgr_frequency.2563845665
Short name T234
Test name
Test status
Simulation time 2480033151 ps
CPU time 18.53 seconds
Started Jul 24 07:09:21 PM PDT 24
Finished Jul 24 07:09:40 PM PDT 24
Peak memory 200648 kb
Host smart-6fcfd3e1-aa99-4b47-8a5f-887336a06fe5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563845665 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.2563845665
Directory /workspace/33.clkmgr_frequency/latest

Test location /workspace/coverage/default/33.clkmgr_frequency_timeout.1419815675
Short name T398
Test name
Test status
Simulation time 632968949 ps
CPU time 2.87 seconds
Started Jul 24 07:09:19 PM PDT 24
Finished Jul 24 07:09:22 PM PDT 24
Peak memory 200524 kb
Host smart-c2ece609-f927-456b-a1d6-d8bc09c327e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419815675 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_t
imeout.1419815675
Directory /workspace/33.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/33.clkmgr_idle_intersig_mubi.2085459136
Short name T530
Test name
Test status
Simulation time 29562857 ps
CPU time 0.96 seconds
Started Jul 24 07:09:20 PM PDT 24
Finished Jul 24 07:09:21 PM PDT 24
Peak memory 200468 kb
Host smart-c6b1f94a-c83d-45f2-8d6d-3573dc42ed87
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085459136 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_idle_intersig_mubi.2085459136
Directory /workspace/33.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.4290032841
Short name T508
Test name
Test status
Simulation time 286300524 ps
CPU time 1.65 seconds
Started Jul 24 07:09:21 PM PDT 24
Finished Jul 24 07:09:23 PM PDT 24
Peak memory 200436 kb
Host smart-01065df8-3cfa-474e-942a-c607cf453d72
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290032841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.clkmgr_lc_clk_byp_req_intersig_mubi.4290032841
Directory /workspace/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.2673750791
Short name T320
Test name
Test status
Simulation time 22331705 ps
CPU time 0.77 seconds
Started Jul 24 07:09:20 PM PDT 24
Finished Jul 24 07:09:21 PM PDT 24
Peak memory 200360 kb
Host smart-ee2168c4-8af4-4d05-af8a-dd700aefd84f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673750791 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.clkmgr_lc_ctrl_intersig_mubi.2673750791
Directory /workspace/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_peri.618708173
Short name T400
Test name
Test status
Simulation time 27375154 ps
CPU time 0.82 seconds
Started Jul 24 07:09:14 PM PDT 24
Finished Jul 24 07:09:15 PM PDT 24
Peak memory 200432 kb
Host smart-9d1137b1-952f-4ed3-9aff-a6ba1555f1b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618708173 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.618708173
Directory /workspace/33.clkmgr_peri/latest

Test location /workspace/coverage/default/33.clkmgr_regwen.4143357714
Short name T488
Test name
Test status
Simulation time 517485968 ps
CPU time 3.14 seconds
Started Jul 24 07:09:18 PM PDT 24
Finished Jul 24 07:09:21 PM PDT 24
Peak memory 200668 kb
Host smart-d54dc987-db2d-41c6-9fbe-8309c385a794
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143357714 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.4143357714
Directory /workspace/33.clkmgr_regwen/latest

Test location /workspace/coverage/default/33.clkmgr_smoke.2222508635
Short name T525
Test name
Test status
Simulation time 19133331 ps
CPU time 0.83 seconds
Started Jul 24 07:09:14 PM PDT 24
Finished Jul 24 07:09:15 PM PDT 24
Peak memory 200452 kb
Host smart-5b3e1b63-d6fe-40b4-8762-ad15ce9bcd46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222508635 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.2222508635
Directory /workspace/33.clkmgr_smoke/latest

Test location /workspace/coverage/default/33.clkmgr_stress_all.668887619
Short name T235
Test name
Test status
Simulation time 2380658011 ps
CPU time 17.24 seconds
Started Jul 24 07:09:21 PM PDT 24
Finished Jul 24 07:09:39 PM PDT 24
Peak memory 200784 kb
Host smart-1b35b246-fb8f-4813-a866-1656f854cf3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668887619 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_stress_all.668887619
Directory /workspace/33.clkmgr_stress_all/latest

Test location /workspace/coverage/default/33.clkmgr_trans.3756165776
Short name T20
Test name
Test status
Simulation time 55059604 ps
CPU time 0.88 seconds
Started Jul 24 07:09:19 PM PDT 24
Finished Jul 24 07:09:20 PM PDT 24
Peak memory 200484 kb
Host smart-12b5b84d-1e3d-4fb3-8a43-c7ce18985bf9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756165776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.3756165776
Directory /workspace/33.clkmgr_trans/latest

Test location /workspace/coverage/default/34.clkmgr_alert_test.2634973236
Short name T688
Test name
Test status
Simulation time 12681854 ps
CPU time 0.75 seconds
Started Jul 24 07:09:25 PM PDT 24
Finished Jul 24 07:09:25 PM PDT 24
Peak memory 200448 kb
Host smart-5474e951-cb32-475c-aa77-daa35c3d5f94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634973236 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clk
mgr_alert_test.2634973236
Directory /workspace/34.clkmgr_alert_test/latest

Test location /workspace/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.2469002108
Short name T238
Test name
Test status
Simulation time 37385384 ps
CPU time 0.9 seconds
Started Jul 24 07:09:25 PM PDT 24
Finished Jul 24 07:09:26 PM PDT 24
Peak memory 200496 kb
Host smart-6ea18da3-05cd-4bf7-aa88-64f531966bc9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469002108 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_clk_handshake_intersig_mubi.2469002108
Directory /workspace/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_clk_status.2009549760
Short name T161
Test name
Test status
Simulation time 51086811 ps
CPU time 0.86 seconds
Started Jul 24 07:09:19 PM PDT 24
Finished Jul 24 07:09:20 PM PDT 24
Peak memory 199688 kb
Host smart-13afb4ff-c5d5-4482-8bbe-e3ed1fabd2c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009549760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.2009549760
Directory /workspace/34.clkmgr_clk_status/latest

Test location /workspace/coverage/default/34.clkmgr_div_intersig_mubi.4111594686
Short name T392
Test name
Test status
Simulation time 45486324 ps
CPU time 0.96 seconds
Started Jul 24 07:09:20 PM PDT 24
Finished Jul 24 07:09:21 PM PDT 24
Peak memory 200480 kb
Host smart-9c2d6fea-46fb-4412-96f5-d428fcc48b67
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111594686 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_div_intersig_mubi.4111594686
Directory /workspace/34.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_extclk.2258366838
Short name T819
Test name
Test status
Simulation time 18243594 ps
CPU time 0.83 seconds
Started Jul 24 07:09:16 PM PDT 24
Finished Jul 24 07:09:17 PM PDT 24
Peak memory 200464 kb
Host smart-4b660f79-a6d1-4789-a368-816c0dec3c5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258366838 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.2258366838
Directory /workspace/34.clkmgr_extclk/latest

Test location /workspace/coverage/default/34.clkmgr_frequency.2260999089
Short name T201
Test name
Test status
Simulation time 322816073 ps
CPU time 2.41 seconds
Started Jul 24 07:09:26 PM PDT 24
Finished Jul 24 07:09:29 PM PDT 24
Peak memory 200480 kb
Host smart-5136db4a-8850-4717-9755-0e72611f3557
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260999089 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.2260999089
Directory /workspace/34.clkmgr_frequency/latest

Test location /workspace/coverage/default/34.clkmgr_frequency_timeout.1282454406
Short name T690
Test name
Test status
Simulation time 1595019044 ps
CPU time 6.72 seconds
Started Jul 24 07:09:21 PM PDT 24
Finished Jul 24 07:09:28 PM PDT 24
Peak memory 200560 kb
Host smart-7f9ed41d-8c2d-4921-8e50-7991c60db3a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282454406 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_t
imeout.1282454406
Directory /workspace/34.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/34.clkmgr_idle_intersig_mubi.1971281396
Short name T470
Test name
Test status
Simulation time 49020710 ps
CPU time 0.83 seconds
Started Jul 24 07:09:19 PM PDT 24
Finished Jul 24 07:09:20 PM PDT 24
Peak memory 200500 kb
Host smart-2cbb5585-d7f5-4349-bbc7-ea38941bc116
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971281396 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_idle_intersig_mubi.1971281396
Directory /workspace/34.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.3106366035
Short name T605
Test name
Test status
Simulation time 15562328 ps
CPU time 0.79 seconds
Started Jul 24 07:09:22 PM PDT 24
Finished Jul 24 07:09:23 PM PDT 24
Peak memory 200472 kb
Host smart-33289fa7-b610-42ec-bb79-d2142fc123f1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106366035 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.clkmgr_lc_clk_byp_req_intersig_mubi.3106366035
Directory /workspace/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.373655330
Short name T317
Test name
Test status
Simulation time 38075518 ps
CPU time 0.79 seconds
Started Jul 24 07:09:14 PM PDT 24
Finished Jul 24 07:09:15 PM PDT 24
Peak memory 200456 kb
Host smart-8079c69b-0910-46aa-a939-730b5636b49b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373655330 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 34.clkmgr_lc_ctrl_intersig_mubi.373655330
Directory /workspace/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_peri.3077835698
Short name T801
Test name
Test status
Simulation time 28067487 ps
CPU time 0.75 seconds
Started Jul 24 07:09:23 PM PDT 24
Finished Jul 24 07:09:24 PM PDT 24
Peak memory 200408 kb
Host smart-3f204f77-a346-4c1b-89f7-b8d2143c47a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077835698 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.3077835698
Directory /workspace/34.clkmgr_peri/latest

Test location /workspace/coverage/default/34.clkmgr_regwen.1400312899
Short name T429
Test name
Test status
Simulation time 1453175438 ps
CPU time 4.83 seconds
Started Jul 24 07:09:20 PM PDT 24
Finished Jul 24 07:09:25 PM PDT 24
Peak memory 200620 kb
Host smart-f1a3886a-059c-4971-ad4e-27228cc954a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400312899 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.1400312899
Directory /workspace/34.clkmgr_regwen/latest

Test location /workspace/coverage/default/34.clkmgr_smoke.2322126720
Short name T645
Test name
Test status
Simulation time 28329407 ps
CPU time 0.88 seconds
Started Jul 24 07:09:22 PM PDT 24
Finished Jul 24 07:09:23 PM PDT 24
Peak memory 200396 kb
Host smart-4e8c6e01-021e-42cd-b697-df5d09d40ae1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322126720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.2322126720
Directory /workspace/34.clkmgr_smoke/latest

Test location /workspace/coverage/default/34.clkmgr_stress_all.1092113508
Short name T217
Test name
Test status
Simulation time 2290384269 ps
CPU time 18.95 seconds
Started Jul 24 07:09:21 PM PDT 24
Finished Jul 24 07:09:40 PM PDT 24
Peak memory 200780 kb
Host smart-25695285-901f-4eda-ae55-8a568215c859
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092113508 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_stress_all.1092113508
Directory /workspace/34.clkmgr_stress_all/latest

Test location /workspace/coverage/default/34.clkmgr_trans.3444401563
Short name T628
Test name
Test status
Simulation time 23454549 ps
CPU time 0.87 seconds
Started Jul 24 07:09:20 PM PDT 24
Finished Jul 24 07:09:21 PM PDT 24
Peak memory 200456 kb
Host smart-afba4ac2-8e9b-47cb-b20b-4e633416b1f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444401563 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.3444401563
Directory /workspace/34.clkmgr_trans/latest

Test location /workspace/coverage/default/35.clkmgr_alert_test.3894351633
Short name T190
Test name
Test status
Simulation time 15211278 ps
CPU time 0.75 seconds
Started Jul 24 07:09:26 PM PDT 24
Finished Jul 24 07:09:27 PM PDT 24
Peak memory 200492 kb
Host smart-2258d39a-d991-49e7-a495-895580b092ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894351633 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clk
mgr_alert_test.3894351633
Directory /workspace/35.clkmgr_alert_test/latest

Test location /workspace/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.4277155994
Short name T164
Test name
Test status
Simulation time 201553185 ps
CPU time 1.42 seconds
Started Jul 24 07:09:20 PM PDT 24
Finished Jul 24 07:09:21 PM PDT 24
Peak memory 200492 kb
Host smart-a5f78bfc-8569-4591-a78e-a55362893dc3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277155994 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_clk_handshake_intersig_mubi.4277155994
Directory /workspace/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_clk_status.35050560
Short name T549
Test name
Test status
Simulation time 14987890 ps
CPU time 0.73 seconds
Started Jul 24 07:09:20 PM PDT 24
Finished Jul 24 07:09:21 PM PDT 24
Peak memory 199652 kb
Host smart-7c2b00c7-a016-4eab-8c54-75e50b364018
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35050560 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.35050560
Directory /workspace/35.clkmgr_clk_status/latest

Test location /workspace/coverage/default/35.clkmgr_div_intersig_mubi.713867666
Short name T341
Test name
Test status
Simulation time 15637208 ps
CPU time 0.77 seconds
Started Jul 24 07:09:34 PM PDT 24
Finished Jul 24 07:09:35 PM PDT 24
Peak memory 200484 kb
Host smart-29f889f9-bb57-4575-8438-43556176005e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713867666 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.clkmgr_div_intersig_mubi.713867666
Directory /workspace/35.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_extclk.3370527322
Short name T209
Test name
Test status
Simulation time 40888929 ps
CPU time 0.78 seconds
Started Jul 24 07:09:20 PM PDT 24
Finished Jul 24 07:09:21 PM PDT 24
Peak memory 200472 kb
Host smart-5f2e3557-838b-4760-a35d-5a1cd3fa4c87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370527322 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.3370527322
Directory /workspace/35.clkmgr_extclk/latest

Test location /workspace/coverage/default/35.clkmgr_frequency.778575844
Short name T318
Test name
Test status
Simulation time 1180842217 ps
CPU time 5.45 seconds
Started Jul 24 07:09:20 PM PDT 24
Finished Jul 24 07:09:25 PM PDT 24
Peak memory 200472 kb
Host smart-0d8189e0-2d0e-4afb-be76-c96881cfd9ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778575844 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.778575844
Directory /workspace/35.clkmgr_frequency/latest

Test location /workspace/coverage/default/35.clkmgr_frequency_timeout.2391951582
Short name T345
Test name
Test status
Simulation time 2292351821 ps
CPU time 7.66 seconds
Started Jul 24 07:09:22 PM PDT 24
Finished Jul 24 07:09:30 PM PDT 24
Peak memory 200836 kb
Host smart-fe5ca877-85b0-4218-8c31-61b06210e715
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391951582 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_t
imeout.2391951582
Directory /workspace/35.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/35.clkmgr_idle_intersig_mubi.885717345
Short name T624
Test name
Test status
Simulation time 141992903 ps
CPU time 1.23 seconds
Started Jul 24 07:09:24 PM PDT 24
Finished Jul 24 07:09:26 PM PDT 24
Peak memory 200500 kb
Host smart-aa7fda29-61c6-438f-89b5-432078900de3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885717345 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.clkmgr_idle_intersig_mubi.885717345
Directory /workspace/35.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.1142951438
Short name T301
Test name
Test status
Simulation time 30149172 ps
CPU time 0.79 seconds
Started Jul 24 07:09:25 PM PDT 24
Finished Jul 24 07:09:26 PM PDT 24
Peak memory 200468 kb
Host smart-bce760c4-7384-491a-8939-b85076e49553
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142951438 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.clkmgr_lc_clk_byp_req_intersig_mubi.1142951438
Directory /workspace/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.2482197740
Short name T695
Test name
Test status
Simulation time 23426287 ps
CPU time 0.91 seconds
Started Jul 24 07:09:21 PM PDT 24
Finished Jul 24 07:09:22 PM PDT 24
Peak memory 200372 kb
Host smart-509d5896-bb91-4f61-97b8-d135ce60f8c3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482197740 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.clkmgr_lc_ctrl_intersig_mubi.2482197740
Directory /workspace/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_peri.3334908398
Short name T342
Test name
Test status
Simulation time 20207526 ps
CPU time 0.81 seconds
Started Jul 24 07:09:18 PM PDT 24
Finished Jul 24 07:09:19 PM PDT 24
Peak memory 200396 kb
Host smart-2323fb29-4ed7-46e7-8d67-076fc9a25835
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334908398 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.3334908398
Directory /workspace/35.clkmgr_peri/latest

Test location /workspace/coverage/default/35.clkmgr_regwen.80025633
Short name T629
Test name
Test status
Simulation time 551944549 ps
CPU time 2.76 seconds
Started Jul 24 07:09:31 PM PDT 24
Finished Jul 24 07:09:34 PM PDT 24
Peak memory 200664 kb
Host smart-ff1c490e-c60f-493f-9946-f7085efe3b2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80025633 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.80025633
Directory /workspace/35.clkmgr_regwen/latest

Test location /workspace/coverage/default/35.clkmgr_smoke.3819380401
Short name T512
Test name
Test status
Simulation time 17043656 ps
CPU time 0.81 seconds
Started Jul 24 07:09:18 PM PDT 24
Finished Jul 24 07:09:19 PM PDT 24
Peak memory 200436 kb
Host smart-0bb4950c-8dc3-4245-8117-7ba55725add0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819380401 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.3819380401
Directory /workspace/35.clkmgr_smoke/latest

Test location /workspace/coverage/default/35.clkmgr_stress_all.51463881
Short name T187
Test name
Test status
Simulation time 8429840404 ps
CPU time 35.27 seconds
Started Jul 24 07:09:27 PM PDT 24
Finished Jul 24 07:10:03 PM PDT 24
Peak memory 200820 kb
Host smart-164b56c1-fd38-45e3-97e3-a7c9a23c311b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51463881 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_
TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.clkmgr_stress_all.51463881
Directory /workspace/35.clkmgr_stress_all/latest

Test location /workspace/coverage/default/35.clkmgr_trans.446197775
Short name T754
Test name
Test status
Simulation time 48928441 ps
CPU time 0.93 seconds
Started Jul 24 07:09:21 PM PDT 24
Finished Jul 24 07:09:22 PM PDT 24
Peak memory 200548 kb
Host smart-380a257d-5f4b-4b60-9622-fdd1652127f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446197775 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.446197775
Directory /workspace/35.clkmgr_trans/latest

Test location /workspace/coverage/default/36.clkmgr_alert_test.4026017554
Short name T180
Test name
Test status
Simulation time 17353968 ps
CPU time 0.71 seconds
Started Jul 24 07:09:27 PM PDT 24
Finished Jul 24 07:09:28 PM PDT 24
Peak memory 200564 kb
Host smart-ef98384f-913a-4276-862a-19644d79bfe9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026017554 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clk
mgr_alert_test.4026017554
Directory /workspace/36.clkmgr_alert_test/latest

Test location /workspace/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.1579990362
Short name T804
Test name
Test status
Simulation time 86446626 ps
CPU time 0.95 seconds
Started Jul 24 07:09:23 PM PDT 24
Finished Jul 24 07:09:24 PM PDT 24
Peak memory 200480 kb
Host smart-4c38e81d-9610-4db2-90a5-9e710986f275
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579990362 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_clk_handshake_intersig_mubi.1579990362
Directory /workspace/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_clk_status.2723878641
Short name T346
Test name
Test status
Simulation time 96281725 ps
CPU time 0.91 seconds
Started Jul 24 07:09:30 PM PDT 24
Finished Jul 24 07:09:31 PM PDT 24
Peak memory 200428 kb
Host smart-05738669-98e0-4ce8-8e04-2e79245249d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723878641 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.2723878641
Directory /workspace/36.clkmgr_clk_status/latest

Test location /workspace/coverage/default/36.clkmgr_div_intersig_mubi.751231733
Short name T496
Test name
Test status
Simulation time 25449514 ps
CPU time 0.9 seconds
Started Jul 24 07:09:35 PM PDT 24
Finished Jul 24 07:09:36 PM PDT 24
Peak memory 200480 kb
Host smart-cf3e4169-ddbc-407b-848d-7ef4ca02ae6f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751231733 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.clkmgr_div_intersig_mubi.751231733
Directory /workspace/36.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_extclk.2561183548
Short name T371
Test name
Test status
Simulation time 28438501 ps
CPU time 0.8 seconds
Started Jul 24 07:09:27 PM PDT 24
Finished Jul 24 07:09:28 PM PDT 24
Peak memory 200428 kb
Host smart-50d37240-91e1-4bf4-8878-63bfc3ac64d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561183548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.2561183548
Directory /workspace/36.clkmgr_extclk/latest

Test location /workspace/coverage/default/36.clkmgr_frequency.1612558258
Short name T788
Test name
Test status
Simulation time 914003078 ps
CPU time 7.27 seconds
Started Jul 24 07:09:22 PM PDT 24
Finished Jul 24 07:09:30 PM PDT 24
Peak memory 200476 kb
Host smart-8b16d3f7-4b1c-4e30-8f06-64b7b20e0a54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612558258 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.1612558258
Directory /workspace/36.clkmgr_frequency/latest

Test location /workspace/coverage/default/36.clkmgr_frequency_timeout.1264284093
Short name T284
Test name
Test status
Simulation time 626773403 ps
CPU time 3.52 seconds
Started Jul 24 07:09:23 PM PDT 24
Finished Jul 24 07:09:26 PM PDT 24
Peak memory 200516 kb
Host smart-27cb03fe-4890-4b40-aa00-c540a2b0eeaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264284093 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_t
imeout.1264284093
Directory /workspace/36.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/36.clkmgr_idle_intersig_mubi.1370054129
Short name T641
Test name
Test status
Simulation time 77923664 ps
CPU time 0.92 seconds
Started Jul 24 07:09:30 PM PDT 24
Finished Jul 24 07:09:31 PM PDT 24
Peak memory 200492 kb
Host smart-df220e00-89f7-4981-87a1-ce2ef7abc0db
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370054129 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_idle_intersig_mubi.1370054129
Directory /workspace/36.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.1841617090
Short name T191
Test name
Test status
Simulation time 29391162 ps
CPU time 0.76 seconds
Started Jul 24 07:09:23 PM PDT 24
Finished Jul 24 07:09:24 PM PDT 24
Peak memory 200420 kb
Host smart-68132db1-89e2-4086-a809-a36a2f2b144a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841617090 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 36.clkmgr_lc_clk_byp_req_intersig_mubi.1841617090
Directory /workspace/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.4093472502
Short name T604
Test name
Test status
Simulation time 141512984 ps
CPU time 1.25 seconds
Started Jul 24 07:09:24 PM PDT 24
Finished Jul 24 07:09:25 PM PDT 24
Peak memory 200416 kb
Host smart-3c7d8c9f-65c1-4db3-bd48-d82c3cae2371
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093472502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 36.clkmgr_lc_ctrl_intersig_mubi.4093472502
Directory /workspace/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_peri.838819003
Short name T414
Test name
Test status
Simulation time 25454584 ps
CPU time 0.75 seconds
Started Jul 24 07:09:25 PM PDT 24
Finished Jul 24 07:09:26 PM PDT 24
Peak memory 200456 kb
Host smart-28064788-d235-464f-b848-d32c2418295f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838819003 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.838819003
Directory /workspace/36.clkmgr_peri/latest

Test location /workspace/coverage/default/36.clkmgr_regwen.906378814
Short name T746
Test name
Test status
Simulation time 987101994 ps
CPU time 3.75 seconds
Started Jul 24 07:09:30 PM PDT 24
Finished Jul 24 07:09:35 PM PDT 24
Peak memory 200564 kb
Host smart-270060eb-9ef3-424b-bae2-f8cb7d3685ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906378814 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.906378814
Directory /workspace/36.clkmgr_regwen/latest

Test location /workspace/coverage/default/36.clkmgr_smoke.4210162049
Short name T325
Test name
Test status
Simulation time 23389604 ps
CPU time 0.85 seconds
Started Jul 24 07:09:28 PM PDT 24
Finished Jul 24 07:09:29 PM PDT 24
Peak memory 200404 kb
Host smart-600e098d-963b-4ed4-8f90-be554f305fb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210162049 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.4210162049
Directory /workspace/36.clkmgr_smoke/latest

Test location /workspace/coverage/default/36.clkmgr_stress_all.925137419
Short name T556
Test name
Test status
Simulation time 2657756153 ps
CPU time 14.5 seconds
Started Jul 24 07:09:27 PM PDT 24
Finished Jul 24 07:09:41 PM PDT 24
Peak memory 200736 kb
Host smart-2ba941c1-7e23-45bc-b3d3-d3e6e0f03c3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925137419 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_stress_all.925137419
Directory /workspace/36.clkmgr_stress_all/latest

Test location /workspace/coverage/default/36.clkmgr_stress_all_with_rand_reset.3733041107
Short name T68
Test name
Test status
Simulation time 93142729235 ps
CPU time 550.6 seconds
Started Jul 24 07:09:28 PM PDT 24
Finished Jul 24 07:18:39 PM PDT 24
Peak memory 209084 kb
Host smart-0865669b-a96d-4c84-a237-3ca491071ae1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3733041107 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all_with_rand_reset.3733041107
Directory /workspace/36.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.clkmgr_trans.3629830290
Short name T213
Test name
Test status
Simulation time 17942044 ps
CPU time 0.85 seconds
Started Jul 24 07:09:25 PM PDT 24
Finished Jul 24 07:09:26 PM PDT 24
Peak memory 200480 kb
Host smart-935b117e-3841-4030-9774-a57beb149e28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629830290 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.3629830290
Directory /workspace/36.clkmgr_trans/latest

Test location /workspace/coverage/default/37.clkmgr_alert_test.3422710903
Short name T805
Test name
Test status
Simulation time 57751494 ps
CPU time 0.91 seconds
Started Jul 24 07:09:21 PM PDT 24
Finished Jul 24 07:09:23 PM PDT 24
Peak memory 200440 kb
Host smart-48ae3be3-8b5d-43b4-ae7c-935e7c3da07b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422710903 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clk
mgr_alert_test.3422710903
Directory /workspace/37.clkmgr_alert_test/latest

Test location /workspace/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.2236927604
Short name T375
Test name
Test status
Simulation time 23005823 ps
CPU time 0.89 seconds
Started Jul 24 07:09:31 PM PDT 24
Finished Jul 24 07:09:33 PM PDT 24
Peak memory 200488 kb
Host smart-ef2805a6-6bfc-42c6-95a3-0a0088f23064
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236927604 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_clk_handshake_intersig_mubi.2236927604
Directory /workspace/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_clk_status.2479654354
Short name T787
Test name
Test status
Simulation time 43974688 ps
CPU time 0.81 seconds
Started Jul 24 07:09:31 PM PDT 24
Finished Jul 24 07:09:32 PM PDT 24
Peak memory 200444 kb
Host smart-403ff024-1281-4654-93ea-162bdca4f815
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479654354 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.2479654354
Directory /workspace/37.clkmgr_clk_status/latest

Test location /workspace/coverage/default/37.clkmgr_div_intersig_mubi.2596186664
Short name T768
Test name
Test status
Simulation time 96893387 ps
CPU time 1.12 seconds
Started Jul 24 07:09:31 PM PDT 24
Finished Jul 24 07:09:33 PM PDT 24
Peak memory 200524 kb
Host smart-ef883026-8085-4b8e-9223-98845d5f9764
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596186664 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_div_intersig_mubi.2596186664
Directory /workspace/37.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_extclk.2026462244
Short name T29
Test name
Test status
Simulation time 34643404 ps
CPU time 0.94 seconds
Started Jul 24 07:09:28 PM PDT 24
Finished Jul 24 07:09:29 PM PDT 24
Peak memory 200520 kb
Host smart-6563a2fb-7068-4473-812a-e9c0b4d2978c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026462244 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.2026462244
Directory /workspace/37.clkmgr_extclk/latest

Test location /workspace/coverage/default/37.clkmgr_frequency.2174647182
Short name T610
Test name
Test status
Simulation time 1896999817 ps
CPU time 9.12 seconds
Started Jul 24 07:09:27 PM PDT 24
Finished Jul 24 07:09:36 PM PDT 24
Peak memory 200668 kb
Host smart-26b9c606-6690-428e-8abe-2ccc8f6a19ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174647182 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.2174647182
Directory /workspace/37.clkmgr_frequency/latest

Test location /workspace/coverage/default/37.clkmgr_frequency_timeout.1158311352
Short name T259
Test name
Test status
Simulation time 744331520 ps
CPU time 4.47 seconds
Started Jul 24 07:09:29 PM PDT 24
Finished Jul 24 07:09:34 PM PDT 24
Peak memory 200568 kb
Host smart-e59b4345-ad33-41d9-a4f8-2ef3d0884fa1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158311352 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_t
imeout.1158311352
Directory /workspace/37.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/37.clkmgr_idle_intersig_mubi.2973330754
Short name T480
Test name
Test status
Simulation time 21045717 ps
CPU time 0.88 seconds
Started Jul 24 07:09:23 PM PDT 24
Finished Jul 24 07:09:24 PM PDT 24
Peak memory 200456 kb
Host smart-a7353103-4b49-412c-90f1-ca70d211eff4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973330754 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_idle_intersig_mubi.2973330754
Directory /workspace/37.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.3772413315
Short name T599
Test name
Test status
Simulation time 31884845 ps
CPU time 0.86 seconds
Started Jul 24 07:09:35 PM PDT 24
Finished Jul 24 07:09:36 PM PDT 24
Peak memory 200476 kb
Host smart-8ea8eb70-f968-4bb6-a370-762de33b37c2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772413315 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.clkmgr_lc_clk_byp_req_intersig_mubi.3772413315
Directory /workspace/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.4242268124
Short name T446
Test name
Test status
Simulation time 19885140 ps
CPU time 0.85 seconds
Started Jul 24 07:09:27 PM PDT 24
Finished Jul 24 07:09:28 PM PDT 24
Peak memory 200480 kb
Host smart-179f6306-ef81-4aa3-a1e8-8ae78e3b1d63
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242268124 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.clkmgr_lc_ctrl_intersig_mubi.4242268124
Directory /workspace/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_peri.3450295685
Short name T192
Test name
Test status
Simulation time 13390579 ps
CPU time 0.75 seconds
Started Jul 24 07:09:22 PM PDT 24
Finished Jul 24 07:09:23 PM PDT 24
Peak memory 200372 kb
Host smart-cd0868be-0b27-485a-9c5e-a6948df97681
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450295685 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.3450295685
Directory /workspace/37.clkmgr_peri/latest

Test location /workspace/coverage/default/37.clkmgr_regwen.1250632505
Short name T742
Test name
Test status
Simulation time 828679899 ps
CPU time 3.28 seconds
Started Jul 24 07:09:31 PM PDT 24
Finished Jul 24 07:09:35 PM PDT 24
Peak memory 200692 kb
Host smart-32c1470d-a5b3-43af-bb83-cea826443368
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250632505 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.1250632505
Directory /workspace/37.clkmgr_regwen/latest

Test location /workspace/coverage/default/37.clkmgr_smoke.4005548660
Short name T138
Test name
Test status
Simulation time 75180059 ps
CPU time 1.04 seconds
Started Jul 24 07:09:29 PM PDT 24
Finished Jul 24 07:09:30 PM PDT 24
Peak memory 200412 kb
Host smart-34120d0d-9aad-4b95-91c3-78956cd8170d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005548660 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.4005548660
Directory /workspace/37.clkmgr_smoke/latest

Test location /workspace/coverage/default/37.clkmgr_stress_all.1426870786
Short name T422
Test name
Test status
Simulation time 524762102 ps
CPU time 2.76 seconds
Started Jul 24 07:09:28 PM PDT 24
Finished Jul 24 07:09:31 PM PDT 24
Peak memory 200504 kb
Host smart-5a609073-4e56-40e0-8bb3-de9064b6c54e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426870786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_stress_all.1426870786
Directory /workspace/37.clkmgr_stress_all/latest

Test location /workspace/coverage/default/37.clkmgr_stress_all_with_rand_reset.3244077517
Short name T74
Test name
Test status
Simulation time 70753045313 ps
CPU time 427.8 seconds
Started Jul 24 07:09:25 PM PDT 24
Finished Jul 24 07:16:33 PM PDT 24
Peak memory 209096 kb
Host smart-926228d5-b4e1-48c5-91b3-ea5e45634405
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3244077517 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all_with_rand_reset.3244077517
Directory /workspace/37.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.clkmgr_trans.1311926939
Short name T475
Test name
Test status
Simulation time 98324436 ps
CPU time 1.04 seconds
Started Jul 24 07:09:28 PM PDT 24
Finished Jul 24 07:09:29 PM PDT 24
Peak memory 200464 kb
Host smart-4a57bbd7-0aee-4303-8c5c-32f7cdb2d174
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311926939 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.1311926939
Directory /workspace/37.clkmgr_trans/latest

Test location /workspace/coverage/default/38.clkmgr_alert_test.468204821
Short name T632
Test name
Test status
Simulation time 41987517 ps
CPU time 0.76 seconds
Started Jul 24 07:09:28 PM PDT 24
Finished Jul 24 07:09:29 PM PDT 24
Peak memory 200568 kb
Host smart-b48a3997-bc8f-498d-a4c3-cadc971ef3a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468204821 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkm
gr_alert_test.468204821
Directory /workspace/38.clkmgr_alert_test/latest

Test location /workspace/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.3395546176
Short name T216
Test name
Test status
Simulation time 43071272 ps
CPU time 0.84 seconds
Started Jul 24 07:09:30 PM PDT 24
Finished Jul 24 07:09:32 PM PDT 24
Peak memory 200452 kb
Host smart-6cad2d30-8c17-4d62-b9a2-852ae89bf2e9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395546176 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_clk_handshake_intersig_mubi.3395546176
Directory /workspace/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_clk_status.3661405452
Short name T412
Test name
Test status
Simulation time 15249225 ps
CPU time 0.73 seconds
Started Jul 24 07:09:30 PM PDT 24
Finished Jul 24 07:09:31 PM PDT 24
Peak memory 200432 kb
Host smart-a8f3d64f-55ac-4bf0-a860-5b185a207642
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661405452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.3661405452
Directory /workspace/38.clkmgr_clk_status/latest

Test location /workspace/coverage/default/38.clkmgr_div_intersig_mubi.3531760399
Short name T544
Test name
Test status
Simulation time 90245096 ps
CPU time 1.09 seconds
Started Jul 24 07:09:32 PM PDT 24
Finished Jul 24 07:09:34 PM PDT 24
Peak memory 200524 kb
Host smart-6cc56137-c311-46ad-bb50-221ce8450a9a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531760399 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_div_intersig_mubi.3531760399
Directory /workspace/38.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_extclk.4019466230
Short name T724
Test name
Test status
Simulation time 14855854 ps
CPU time 0.74 seconds
Started Jul 24 07:09:37 PM PDT 24
Finished Jul 24 07:09:38 PM PDT 24
Peak memory 200448 kb
Host smart-a97852d8-4074-4836-9699-5c325756a4f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019466230 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.4019466230
Directory /workspace/38.clkmgr_extclk/latest

Test location /workspace/coverage/default/38.clkmgr_frequency.1959591496
Short name T14
Test name
Test status
Simulation time 2361425898 ps
CPU time 17.76 seconds
Started Jul 24 07:09:30 PM PDT 24
Finished Jul 24 07:09:48 PM PDT 24
Peak memory 200692 kb
Host smart-8999a072-1aee-49fc-aabd-92f6c1637b2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959591496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.1959591496
Directory /workspace/38.clkmgr_frequency/latest

Test location /workspace/coverage/default/38.clkmgr_frequency_timeout.1939555960
Short name T264
Test name
Test status
Simulation time 1588659569 ps
CPU time 8 seconds
Started Jul 24 07:09:31 PM PDT 24
Finished Jul 24 07:09:40 PM PDT 24
Peak memory 200560 kb
Host smart-27d41645-c954-4b4c-ac7d-2311b2f78c15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939555960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_t
imeout.1939555960
Directory /workspace/38.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/38.clkmgr_idle_intersig_mubi.1133088740
Short name T232
Test name
Test status
Simulation time 75949786 ps
CPU time 1.21 seconds
Started Jul 24 07:09:30 PM PDT 24
Finished Jul 24 07:09:31 PM PDT 24
Peak memory 200432 kb
Host smart-d8cb0d66-c52c-4ef8-8578-8d5fbea0e03e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133088740 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_idle_intersig_mubi.1133088740
Directory /workspace/38.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.1773238628
Short name T419
Test name
Test status
Simulation time 15958229 ps
CPU time 0.78 seconds
Started Jul 24 07:09:35 PM PDT 24
Finished Jul 24 07:09:36 PM PDT 24
Peak memory 200460 kb
Host smart-d36723d8-48e6-4e9d-bde4-aace618e7eb5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773238628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.clkmgr_lc_clk_byp_req_intersig_mubi.1773238628
Directory /workspace/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.1147632873
Short name T785
Test name
Test status
Simulation time 98937860 ps
CPU time 1.07 seconds
Started Jul 24 07:09:30 PM PDT 24
Finished Jul 24 07:09:32 PM PDT 24
Peak memory 200464 kb
Host smart-5ef8f2dc-8e91-434b-a658-ccb48b889f66
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147632873 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.clkmgr_lc_ctrl_intersig_mubi.1147632873
Directory /workspace/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_peri.1210001678
Short name T433
Test name
Test status
Simulation time 15549754 ps
CPU time 0.78 seconds
Started Jul 24 07:09:33 PM PDT 24
Finished Jul 24 07:09:34 PM PDT 24
Peak memory 200452 kb
Host smart-e19b6565-e7e7-4bae-9a21-ea14b3a9a76e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210001678 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.1210001678
Directory /workspace/38.clkmgr_peri/latest

Test location /workspace/coverage/default/38.clkmgr_regwen.1272720127
Short name T148
Test name
Test status
Simulation time 229822665 ps
CPU time 1.92 seconds
Started Jul 24 07:09:31 PM PDT 24
Finished Jul 24 07:09:34 PM PDT 24
Peak memory 200468 kb
Host smart-5042adc4-b853-42d7-88e2-b48be48d2aa7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272720127 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.1272720127
Directory /workspace/38.clkmgr_regwen/latest

Test location /workspace/coverage/default/38.clkmgr_smoke.2280171976
Short name T139
Test name
Test status
Simulation time 23869635 ps
CPU time 0.91 seconds
Started Jul 24 07:09:30 PM PDT 24
Finished Jul 24 07:09:32 PM PDT 24
Peak memory 200412 kb
Host smart-a51ffb6a-e803-4586-9d02-df9ea267cedc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280171976 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.2280171976
Directory /workspace/38.clkmgr_smoke/latest

Test location /workspace/coverage/default/38.clkmgr_stress_all.221446793
Short name T751
Test name
Test status
Simulation time 2744093681 ps
CPU time 19.55 seconds
Started Jul 24 07:09:29 PM PDT 24
Finished Jul 24 07:09:49 PM PDT 24
Peak memory 200784 kb
Host smart-4d5fc8f5-667b-4170-acd4-64a52519b7cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221446793 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_stress_all.221446793
Directory /workspace/38.clkmgr_stress_all/latest

Test location /workspace/coverage/default/38.clkmgr_trans.3907502365
Short name T827
Test name
Test status
Simulation time 37613806 ps
CPU time 0.77 seconds
Started Jul 24 07:09:33 PM PDT 24
Finished Jul 24 07:09:34 PM PDT 24
Peak memory 200548 kb
Host smart-72bc76c7-74a8-4971-a85f-9ce43d34f066
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907502365 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.3907502365
Directory /workspace/38.clkmgr_trans/latest

Test location /workspace/coverage/default/39.clkmgr_alert_test.684191556
Short name T626
Test name
Test status
Simulation time 14344276 ps
CPU time 0.78 seconds
Started Jul 24 07:09:29 PM PDT 24
Finished Jul 24 07:09:30 PM PDT 24
Peak memory 200528 kb
Host smart-f32bd8e3-a79f-4c8a-90c3-ec0b6cbc049e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684191556 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkm
gr_alert_test.684191556
Directory /workspace/39.clkmgr_alert_test/latest

Test location /workspace/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.4215297051
Short name T18
Test name
Test status
Simulation time 96063065 ps
CPU time 1.08 seconds
Started Jul 24 07:09:31 PM PDT 24
Finished Jul 24 07:09:33 PM PDT 24
Peak memory 200512 kb
Host smart-b028ad66-49ca-4c9d-b870-ad993642ea38
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215297051 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_clk_handshake_intersig_mubi.4215297051
Directory /workspace/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_clk_status.2513527818
Short name T40
Test name
Test status
Simulation time 14011509 ps
CPU time 0.69 seconds
Started Jul 24 07:09:29 PM PDT 24
Finished Jul 24 07:09:30 PM PDT 24
Peak memory 199636 kb
Host smart-605d7c7f-9e61-431a-a6dc-1df11a913502
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513527818 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.2513527818
Directory /workspace/39.clkmgr_clk_status/latest

Test location /workspace/coverage/default/39.clkmgr_div_intersig_mubi.3343494237
Short name T640
Test name
Test status
Simulation time 63763428 ps
CPU time 1.04 seconds
Started Jul 24 07:09:31 PM PDT 24
Finished Jul 24 07:09:33 PM PDT 24
Peak memory 200500 kb
Host smart-16bf7d67-e2f1-4b79-b61c-3ece12bb60f0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343494237 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_div_intersig_mubi.3343494237
Directory /workspace/39.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_extclk.2149456136
Short name T468
Test name
Test status
Simulation time 12573330 ps
CPU time 0.74 seconds
Started Jul 24 07:09:30 PM PDT 24
Finished Jul 24 07:09:31 PM PDT 24
Peak memory 200428 kb
Host smart-dceaedb2-268a-4ffe-a84e-ef953a80f936
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149456136 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.2149456136
Directory /workspace/39.clkmgr_extclk/latest

Test location /workspace/coverage/default/39.clkmgr_frequency.517217640
Short name T577
Test name
Test status
Simulation time 1645314167 ps
CPU time 9.29 seconds
Started Jul 24 07:09:33 PM PDT 24
Finished Jul 24 07:09:42 PM PDT 24
Peak memory 200480 kb
Host smart-19395b90-6cc0-418b-b1a8-becd832f6b7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517217640 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.517217640
Directory /workspace/39.clkmgr_frequency/latest

Test location /workspace/coverage/default/39.clkmgr_frequency_timeout.624180047
Short name T363
Test name
Test status
Simulation time 1034854022 ps
CPU time 4.85 seconds
Started Jul 24 07:09:28 PM PDT 24
Finished Jul 24 07:09:33 PM PDT 24
Peak memory 200544 kb
Host smart-d114b928-5c6e-43aa-beaa-1891a0e75bee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624180047 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_ti
meout.624180047
Directory /workspace/39.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/39.clkmgr_idle_intersig_mubi.1323306029
Short name T563
Test name
Test status
Simulation time 37025297 ps
CPU time 0.79 seconds
Started Jul 24 07:09:37 PM PDT 24
Finished Jul 24 07:09:38 PM PDT 24
Peak memory 200452 kb
Host smart-3109abc4-1478-4989-bc4c-b72282e80e44
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323306029 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_idle_intersig_mubi.1323306029
Directory /workspace/39.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.805788847
Short name T179
Test name
Test status
Simulation time 22973171 ps
CPU time 0.91 seconds
Started Jul 24 07:09:31 PM PDT 24
Finished Jul 24 07:09:33 PM PDT 24
Peak memory 200692 kb
Host smart-a211a70c-f571-4e14-b5ba-d0fe420af34f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805788847 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 39.clkmgr_lc_clk_byp_req_intersig_mubi.805788847
Directory /workspace/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.2877687386
Short name T283
Test name
Test status
Simulation time 34645789 ps
CPU time 0.89 seconds
Started Jul 24 07:09:29 PM PDT 24
Finished Jul 24 07:09:31 PM PDT 24
Peak memory 200468 kb
Host smart-753d37d7-a3ca-43b1-b50c-491603c26f3f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877687386 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.clkmgr_lc_ctrl_intersig_mubi.2877687386
Directory /workspace/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_peri.3263883561
Short name T566
Test name
Test status
Simulation time 62325684 ps
CPU time 0.85 seconds
Started Jul 24 07:09:28 PM PDT 24
Finished Jul 24 07:09:29 PM PDT 24
Peak memory 200472 kb
Host smart-43c34add-2dfb-4539-be64-b04c025ff7b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263883561 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.3263883561
Directory /workspace/39.clkmgr_peri/latest

Test location /workspace/coverage/default/39.clkmgr_regwen.1482114338
Short name T405
Test name
Test status
Simulation time 739974931 ps
CPU time 4.5 seconds
Started Jul 24 07:09:31 PM PDT 24
Finished Jul 24 07:09:36 PM PDT 24
Peak memory 200680 kb
Host smart-04ddfd6e-9ddd-44fe-858e-7c4c7d379df6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482114338 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.1482114338
Directory /workspace/39.clkmgr_regwen/latest

Test location /workspace/coverage/default/39.clkmgr_smoke.679658287
Short name T757
Test name
Test status
Simulation time 15636089 ps
CPU time 0.86 seconds
Started Jul 24 07:09:33 PM PDT 24
Finished Jul 24 07:09:34 PM PDT 24
Peak memory 200428 kb
Host smart-4319c168-846a-4bd0-a034-8a182c9562a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679658287 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.679658287
Directory /workspace/39.clkmgr_smoke/latest

Test location /workspace/coverage/default/39.clkmgr_stress_all.2817220648
Short name T443
Test name
Test status
Simulation time 10707492253 ps
CPU time 52.65 seconds
Started Jul 24 07:09:32 PM PDT 24
Finished Jul 24 07:10:25 PM PDT 24
Peak memory 200844 kb
Host smart-3bc22554-167c-415c-8fe3-643072223576
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817220648 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_stress_all.2817220648
Directory /workspace/39.clkmgr_stress_all/latest

Test location /workspace/coverage/default/39.clkmgr_stress_all_with_rand_reset.2544849841
Short name T703
Test name
Test status
Simulation time 82012465922 ps
CPU time 602.08 seconds
Started Jul 24 07:09:37 PM PDT 24
Finished Jul 24 07:19:39 PM PDT 24
Peak memory 209124 kb
Host smart-b887e3a0-4487-4aae-9785-317ff7df31c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2544849841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all_with_rand_reset.2544849841
Directory /workspace/39.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.clkmgr_trans.848178543
Short name T571
Test name
Test status
Simulation time 103975599 ps
CPU time 1.15 seconds
Started Jul 24 07:09:33 PM PDT 24
Finished Jul 24 07:09:35 PM PDT 24
Peak memory 200480 kb
Host smart-3df42d72-034f-490a-94bc-806f41b01df9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848178543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.848178543
Directory /workspace/39.clkmgr_trans/latest

Test location /workspace/coverage/default/4.clkmgr_alert_test.2483721634
Short name T620
Test name
Test status
Simulation time 59788724 ps
CPU time 0.95 seconds
Started Jul 24 07:08:07 PM PDT 24
Finished Jul 24 07:08:08 PM PDT 24
Peak memory 200472 kb
Host smart-5c314fcc-87a8-4367-b6da-93eb5aece91c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483721634 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkm
gr_alert_test.2483721634
Directory /workspace/4.clkmgr_alert_test/latest

Test location /workspace/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.2238489533
Short name T417
Test name
Test status
Simulation time 41652752 ps
CPU time 0.82 seconds
Started Jul 24 07:08:00 PM PDT 24
Finished Jul 24 07:08:01 PM PDT 24
Peak memory 200472 kb
Host smart-4478609b-1b9b-45fe-88d0-ac466849da20
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238489533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_clk_handshake_intersig_mubi.2238489533
Directory /workspace/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_clk_status.3259191120
Short name T158
Test name
Test status
Simulation time 35282525 ps
CPU time 0.8 seconds
Started Jul 24 07:08:04 PM PDT 24
Finished Jul 24 07:08:05 PM PDT 24
Peak memory 200460 kb
Host smart-afa6e980-3aea-4f50-a36d-68d4a0d922d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259191120 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.3259191120
Directory /workspace/4.clkmgr_clk_status/latest

Test location /workspace/coverage/default/4.clkmgr_div_intersig_mubi.3549723849
Short name T555
Test name
Test status
Simulation time 36658956 ps
CPU time 0.89 seconds
Started Jul 24 07:08:01 PM PDT 24
Finished Jul 24 07:08:02 PM PDT 24
Peak memory 200408 kb
Host smart-15eddfbe-388d-4e0b-87a6-851a756e054b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549723849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_div_intersig_mubi.3549723849
Directory /workspace/4.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_extclk.3603573893
Short name T407
Test name
Test status
Simulation time 23925810 ps
CPU time 0.8 seconds
Started Jul 24 07:08:03 PM PDT 24
Finished Jul 24 07:08:04 PM PDT 24
Peak memory 200488 kb
Host smart-732021a6-891b-4300-86ce-2ecc536879ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603573893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.3603573893
Directory /workspace/4.clkmgr_extclk/latest

Test location /workspace/coverage/default/4.clkmgr_frequency.747541934
Short name T16
Test name
Test status
Simulation time 1655834397 ps
CPU time 7.98 seconds
Started Jul 24 07:08:03 PM PDT 24
Finished Jul 24 07:08:11 PM PDT 24
Peak memory 200468 kb
Host smart-dc1957c6-c582-4d8c-a9e4-fdab14d5df9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747541934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.747541934
Directory /workspace/4.clkmgr_frequency/latest

Test location /workspace/coverage/default/4.clkmgr_frequency_timeout.2756651192
Short name T674
Test name
Test status
Simulation time 617913309 ps
CPU time 4.08 seconds
Started Jul 24 07:08:07 PM PDT 24
Finished Jul 24 07:08:11 PM PDT 24
Peak memory 200540 kb
Host smart-2465d824-9bfe-4f56-ba2d-21126be7bbf4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756651192 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_ti
meout.2756651192
Directory /workspace/4.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/4.clkmgr_idle_intersig_mubi.2971057413
Short name T384
Test name
Test status
Simulation time 14317127 ps
CPU time 0.74 seconds
Started Jul 24 07:08:04 PM PDT 24
Finished Jul 24 07:08:05 PM PDT 24
Peak memory 200448 kb
Host smart-5fd28976-b949-4209-9135-f5eda47a05c3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971057413 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_idle_intersig_mubi.2971057413
Directory /workspace/4.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.1411196088
Short name T311
Test name
Test status
Simulation time 47446442 ps
CPU time 0.87 seconds
Started Jul 24 07:08:02 PM PDT 24
Finished Jul 24 07:08:03 PM PDT 24
Peak memory 200464 kb
Host smart-4408b13b-4179-4172-ba11-b664143ee49e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411196088 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_lc_clk_byp_req_intersig_mubi.1411196088
Directory /workspace/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.777972591
Short name T729
Test name
Test status
Simulation time 25114304 ps
CPU time 0.88 seconds
Started Jul 24 07:08:01 PM PDT 24
Finished Jul 24 07:08:02 PM PDT 24
Peak memory 200476 kb
Host smart-7354c0c9-1e0d-415b-bb0b-2d05b763c845
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777972591 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.clkmgr_lc_ctrl_intersig_mubi.777972591
Directory /workspace/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_peri.505127236
Short name T437
Test name
Test status
Simulation time 37383657 ps
CPU time 0.87 seconds
Started Jul 24 07:08:07 PM PDT 24
Finished Jul 24 07:08:08 PM PDT 24
Peak memory 200420 kb
Host smart-e7fd6b7e-9be6-4407-9233-5e51360a4d3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505127236 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.505127236
Directory /workspace/4.clkmgr_peri/latest

Test location /workspace/coverage/default/4.clkmgr_regwen.2228441303
Short name T460
Test name
Test status
Simulation time 776855147 ps
CPU time 3.3 seconds
Started Jul 24 07:08:03 PM PDT 24
Finished Jul 24 07:08:07 PM PDT 24
Peak memory 200628 kb
Host smart-f326d390-33a4-4347-8277-dfa32d502974
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228441303 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.2228441303
Directory /workspace/4.clkmgr_regwen/latest

Test location /workspace/coverage/default/4.clkmgr_sec_cm.1678393737
Short name T43
Test name
Test status
Simulation time 421318977 ps
CPU time 3.35 seconds
Started Jul 24 07:08:05 PM PDT 24
Finished Jul 24 07:08:08 PM PDT 24
Peak memory 217108 kb
Host smart-4626aab7-48cb-4e08-a5ea-d1c04ca02024
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678393737 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmg
r_sec_cm.1678393737
Directory /workspace/4.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/4.clkmgr_smoke.1108565774
Short name T142
Test name
Test status
Simulation time 22228144 ps
CPU time 0.87 seconds
Started Jul 24 07:07:59 PM PDT 24
Finished Jul 24 07:08:00 PM PDT 24
Peak memory 200448 kb
Host smart-da90b771-d43f-409d-80bf-94fed625b9ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108565774 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.1108565774
Directory /workspace/4.clkmgr_smoke/latest

Test location /workspace/coverage/default/4.clkmgr_stress_all.197810432
Short name T733
Test name
Test status
Simulation time 1486648451 ps
CPU time 9.41 seconds
Started Jul 24 07:08:07 PM PDT 24
Finished Jul 24 07:08:16 PM PDT 24
Peak memory 200780 kb
Host smart-042a1210-271b-451a-8a7f-5387e50d79ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197810432 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_stress_all.197810432
Directory /workspace/4.clkmgr_stress_all/latest

Test location /workspace/coverage/default/4.clkmgr_trans.3807890845
Short name T692
Test name
Test status
Simulation time 17886302 ps
CPU time 0.8 seconds
Started Jul 24 07:08:05 PM PDT 24
Finished Jul 24 07:08:06 PM PDT 24
Peak memory 200460 kb
Host smart-9c967e27-e00f-4e11-8857-a2e2ab96ddcc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807890845 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.3807890845
Directory /workspace/4.clkmgr_trans/latest

Test location /workspace/coverage/default/40.clkmgr_alert_test.3648782882
Short name T798
Test name
Test status
Simulation time 215326469 ps
CPU time 1.35 seconds
Started Jul 24 07:09:36 PM PDT 24
Finished Jul 24 07:09:37 PM PDT 24
Peak memory 200552 kb
Host smart-f36c37b5-759b-48f7-b635-c96ce72e0153
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648782882 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clk
mgr_alert_test.3648782882
Directory /workspace/40.clkmgr_alert_test/latest

Test location /workspace/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.3389045122
Short name T19
Test name
Test status
Simulation time 20811926 ps
CPU time 0.9 seconds
Started Jul 24 07:09:35 PM PDT 24
Finished Jul 24 07:09:36 PM PDT 24
Peak memory 200472 kb
Host smart-3b46cd2d-7c88-41e5-9993-857b2c79fad1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389045122 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_clk_handshake_intersig_mubi.3389045122
Directory /workspace/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_clk_status.588357213
Short name T736
Test name
Test status
Simulation time 45566080 ps
CPU time 0.83 seconds
Started Jul 24 07:09:32 PM PDT 24
Finished Jul 24 07:09:33 PM PDT 24
Peak memory 199580 kb
Host smart-a6c3caf8-04d8-4ffc-a0a0-ec81454b6eae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588357213 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.588357213
Directory /workspace/40.clkmgr_clk_status/latest

Test location /workspace/coverage/default/40.clkmgr_div_intersig_mubi.137858249
Short name T395
Test name
Test status
Simulation time 18912296 ps
CPU time 0.83 seconds
Started Jul 24 07:09:36 PM PDT 24
Finished Jul 24 07:09:37 PM PDT 24
Peak memory 200464 kb
Host smart-2b46f44b-4c31-4c16-a0a5-6fff426db209
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137858249 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.clkmgr_div_intersig_mubi.137858249
Directory /workspace/40.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_extclk.1974699260
Short name T380
Test name
Test status
Simulation time 35881913 ps
CPU time 0.86 seconds
Started Jul 24 07:09:36 PM PDT 24
Finished Jul 24 07:09:37 PM PDT 24
Peak memory 200452 kb
Host smart-ced3f3ac-a15c-4902-9d69-26d0740ed3ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974699260 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.1974699260
Directory /workspace/40.clkmgr_extclk/latest

Test location /workspace/coverage/default/40.clkmgr_frequency.1050435641
Short name T619
Test name
Test status
Simulation time 1041846211 ps
CPU time 8.22 seconds
Started Jul 24 07:09:31 PM PDT 24
Finished Jul 24 07:09:40 PM PDT 24
Peak memory 200388 kb
Host smart-a3139d41-0bcb-47f5-b9a9-27cd8af50fe2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050435641 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.1050435641
Directory /workspace/40.clkmgr_frequency/latest

Test location /workspace/coverage/default/40.clkmgr_frequency_timeout.2097728652
Short name T487
Test name
Test status
Simulation time 2300247681 ps
CPU time 17.31 seconds
Started Jul 24 07:09:31 PM PDT 24
Finished Jul 24 07:09:49 PM PDT 24
Peak memory 200736 kb
Host smart-a0a56472-8323-4b29-ae7d-4730cf00bf7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097728652 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_t
imeout.2097728652
Directory /workspace/40.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/40.clkmgr_idle_intersig_mubi.1292966750
Short name T369
Test name
Test status
Simulation time 35444768 ps
CPU time 0.79 seconds
Started Jul 24 07:09:31 PM PDT 24
Finished Jul 24 07:09:33 PM PDT 24
Peak memory 200532 kb
Host smart-74bfcb2a-8326-44ef-9942-da61e6bbeba4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292966750 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_idle_intersig_mubi.1292966750
Directory /workspace/40.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.1543906473
Short name T523
Test name
Test status
Simulation time 22734989 ps
CPU time 0.83 seconds
Started Jul 24 07:09:35 PM PDT 24
Finished Jul 24 07:09:36 PM PDT 24
Peak memory 200456 kb
Host smart-3011572b-7986-4719-8254-52a4b27deaee
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543906473 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.clkmgr_lc_clk_byp_req_intersig_mubi.1543906473
Directory /workspace/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.2739938041
Short name T770
Test name
Test status
Simulation time 45698210 ps
CPU time 0.85 seconds
Started Jul 24 07:09:32 PM PDT 24
Finished Jul 24 07:09:33 PM PDT 24
Peak memory 200456 kb
Host smart-0cdc9129-0851-4f0c-9aaa-27cca8f0122a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739938041 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.clkmgr_lc_ctrl_intersig_mubi.2739938041
Directory /workspace/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_peri.2422109720
Short name T455
Test name
Test status
Simulation time 45680815 ps
CPU time 0.84 seconds
Started Jul 24 07:09:31 PM PDT 24
Finished Jul 24 07:09:33 PM PDT 24
Peak memory 200468 kb
Host smart-09d1a013-f93a-45c8-9a40-ac1029ec37b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422109720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.2422109720
Directory /workspace/40.clkmgr_peri/latest

Test location /workspace/coverage/default/40.clkmgr_regwen.439023909
Short name T47
Test name
Test status
Simulation time 660677674 ps
CPU time 2.76 seconds
Started Jul 24 07:09:31 PM PDT 24
Finished Jul 24 07:09:35 PM PDT 24
Peak memory 200660 kb
Host smart-08d14252-c395-4996-adea-e97db2abcc05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439023909 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.439023909
Directory /workspace/40.clkmgr_regwen/latest

Test location /workspace/coverage/default/40.clkmgr_smoke.890399711
Short name T679
Test name
Test status
Simulation time 24142540 ps
CPU time 0.92 seconds
Started Jul 24 07:09:40 PM PDT 24
Finished Jul 24 07:09:41 PM PDT 24
Peak memory 200288 kb
Host smart-49376305-57e9-49b7-83b1-446bb3d12b6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890399711 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.890399711
Directory /workspace/40.clkmgr_smoke/latest

Test location /workspace/coverage/default/40.clkmgr_stress_all.3514156763
Short name T273
Test name
Test status
Simulation time 4723055344 ps
CPU time 34.7 seconds
Started Jul 24 07:09:36 PM PDT 24
Finished Jul 24 07:10:11 PM PDT 24
Peak memory 200756 kb
Host smart-39443922-4979-4da7-b3fb-ea4ac60a0852
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514156763 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_stress_all.3514156763
Directory /workspace/40.clkmgr_stress_all/latest

Test location /workspace/coverage/default/40.clkmgr_trans.1463357394
Short name T484
Test name
Test status
Simulation time 41301341 ps
CPU time 1.1 seconds
Started Jul 24 07:09:32 PM PDT 24
Finished Jul 24 07:09:33 PM PDT 24
Peak memory 200472 kb
Host smart-542d3205-28a6-46ab-a865-5995f0ead790
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463357394 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.1463357394
Directory /workspace/40.clkmgr_trans/latest

Test location /workspace/coverage/default/41.clkmgr_alert_test.1396487328
Short name T781
Test name
Test status
Simulation time 40752519 ps
CPU time 0.8 seconds
Started Jul 24 07:09:40 PM PDT 24
Finished Jul 24 07:09:41 PM PDT 24
Peak memory 200548 kb
Host smart-f566ece9-8ee9-4f9b-b540-3c96d6d29353
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396487328 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clk
mgr_alert_test.1396487328
Directory /workspace/41.clkmgr_alert_test/latest

Test location /workspace/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.3000536522
Short name T89
Test name
Test status
Simulation time 23567789 ps
CPU time 0.91 seconds
Started Jul 24 07:09:35 PM PDT 24
Finished Jul 24 07:09:37 PM PDT 24
Peak memory 200480 kb
Host smart-670753b2-435e-42bf-8897-132b32224d30
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000536522 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_clk_handshake_intersig_mubi.3000536522
Directory /workspace/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_div_intersig_mubi.4192580385
Short name T708
Test name
Test status
Simulation time 49277869 ps
CPU time 0.99 seconds
Started Jul 24 07:09:30 PM PDT 24
Finished Jul 24 07:09:32 PM PDT 24
Peak memory 200484 kb
Host smart-bfd28b24-246a-49f1-b39d-5d6ae068495a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192580385 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_div_intersig_mubi.4192580385
Directory /workspace/41.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_extclk.2865098511
Short name T223
Test name
Test status
Simulation time 35905871 ps
CPU time 0.88 seconds
Started Jul 24 07:09:33 PM PDT 24
Finished Jul 24 07:09:34 PM PDT 24
Peak memory 200460 kb
Host smart-bf3d86c2-c5e4-4e08-8783-df967c1f03cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865098511 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.2865098511
Directory /workspace/41.clkmgr_extclk/latest

Test location /workspace/coverage/default/41.clkmgr_frequency.1678299671
Short name T581
Test name
Test status
Simulation time 465472842 ps
CPU time 2.72 seconds
Started Jul 24 07:09:32 PM PDT 24
Finished Jul 24 07:09:35 PM PDT 24
Peak memory 200472 kb
Host smart-625946ea-1c72-4a53-bec6-3e0fc8cbf55f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678299671 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.1678299671
Directory /workspace/41.clkmgr_frequency/latest

Test location /workspace/coverage/default/41.clkmgr_frequency_timeout.562293522
Short name T177
Test name
Test status
Simulation time 1235099499 ps
CPU time 5.45 seconds
Started Jul 24 07:09:34 PM PDT 24
Finished Jul 24 07:09:40 PM PDT 24
Peak memory 200572 kb
Host smart-1f1b87ff-da44-4fe8-ba9d-74f73bd05c36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562293522 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_ti
meout.562293522
Directory /workspace/41.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/41.clkmgr_idle_intersig_mubi.179462362
Short name T557
Test name
Test status
Simulation time 181760736 ps
CPU time 1.29 seconds
Started Jul 24 07:09:29 PM PDT 24
Finished Jul 24 07:09:30 PM PDT 24
Peak memory 200316 kb
Host smart-ff1584f6-41d6-4598-86cf-26ebc96b6d8d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179462362 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.clkmgr_idle_intersig_mubi.179462362
Directory /workspace/41.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.718457607
Short name T601
Test name
Test status
Simulation time 28359961 ps
CPU time 1.01 seconds
Started Jul 24 07:09:40 PM PDT 24
Finished Jul 24 07:09:42 PM PDT 24
Peak memory 200304 kb
Host smart-6b8c82c9-b2ed-4821-b87b-bba7d147b571
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718457607 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 41.clkmgr_lc_clk_byp_req_intersig_mubi.718457607
Directory /workspace/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.3646646149
Short name T649
Test name
Test status
Simulation time 63481207 ps
CPU time 0.96 seconds
Started Jul 24 07:09:37 PM PDT 24
Finished Jul 24 07:09:38 PM PDT 24
Peak memory 200448 kb
Host smart-6f89d42a-6fbd-44a1-a1b3-6e6bb4e61f7f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646646149 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.clkmgr_lc_ctrl_intersig_mubi.3646646149
Directory /workspace/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_peri.295231992
Short name T316
Test name
Test status
Simulation time 15615835 ps
CPU time 0.76 seconds
Started Jul 24 07:09:30 PM PDT 24
Finished Jul 24 07:09:31 PM PDT 24
Peak memory 200380 kb
Host smart-99d4dcbb-fcd6-4896-915b-9fdffd64cf86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295231992 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.295231992
Directory /workspace/41.clkmgr_peri/latest

Test location /workspace/coverage/default/41.clkmgr_regwen.625088080
Short name T83
Test name
Test status
Simulation time 691655910 ps
CPU time 2.95 seconds
Started Jul 24 07:09:36 PM PDT 24
Finished Jul 24 07:09:39 PM PDT 24
Peak memory 200636 kb
Host smart-6413b421-384a-4b49-976e-94596254c8e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625088080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.625088080
Directory /workspace/41.clkmgr_regwen/latest

Test location /workspace/coverage/default/41.clkmgr_smoke.1154696663
Short name T263
Test name
Test status
Simulation time 72413474 ps
CPU time 1.04 seconds
Started Jul 24 07:09:34 PM PDT 24
Finished Jul 24 07:09:35 PM PDT 24
Peak memory 200448 kb
Host smart-347024b4-12b3-4db3-ac20-d17207ef5ab2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154696663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.1154696663
Directory /workspace/41.clkmgr_smoke/latest

Test location /workspace/coverage/default/41.clkmgr_stress_all.370904356
Short name T780
Test name
Test status
Simulation time 523940994 ps
CPU time 4.87 seconds
Started Jul 24 07:09:40 PM PDT 24
Finished Jul 24 07:09:45 PM PDT 24
Peak memory 200492 kb
Host smart-4c4afbe0-7c55-488e-9c9a-3ee452ed18b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370904356 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_stress_all.370904356
Directory /workspace/41.clkmgr_stress_all/latest

Test location /workspace/coverage/default/41.clkmgr_stress_all_with_rand_reset.1491493263
Short name T727
Test name
Test status
Simulation time 314578525638 ps
CPU time 1177.35 seconds
Started Jul 24 07:09:29 PM PDT 24
Finished Jul 24 07:29:07 PM PDT 24
Peak memory 217288 kb
Host smart-7067e2b1-962a-43ae-b666-47da0e5416e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1491493263 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all_with_rand_reset.1491493263
Directory /workspace/41.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.clkmgr_trans.2885635432
Short name T113
Test name
Test status
Simulation time 89233314 ps
CPU time 1.12 seconds
Started Jul 24 07:09:37 PM PDT 24
Finished Jul 24 07:09:38 PM PDT 24
Peak memory 200472 kb
Host smart-d72c37c6-f779-4587-abaf-5e2744c4b758
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885635432 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.2885635432
Directory /workspace/41.clkmgr_trans/latest

Test location /workspace/coverage/default/42.clkmgr_alert_test.1225162587
Short name T547
Test name
Test status
Simulation time 47705101 ps
CPU time 0.86 seconds
Started Jul 24 07:09:41 PM PDT 24
Finished Jul 24 07:09:42 PM PDT 24
Peak memory 200544 kb
Host smart-55f9b580-b3b4-40b7-9953-9f5403fdacfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225162587 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clk
mgr_alert_test.1225162587
Directory /workspace/42.clkmgr_alert_test/latest

Test location /workspace/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.1248869290
Short name T94
Test name
Test status
Simulation time 22512874 ps
CPU time 0.86 seconds
Started Jul 24 07:09:38 PM PDT 24
Finished Jul 24 07:09:39 PM PDT 24
Peak memory 200492 kb
Host smart-034a5c49-ba33-4526-8b6b-3a313534378c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248869290 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_clk_handshake_intersig_mubi.1248869290
Directory /workspace/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_clk_status.3106712385
Short name T385
Test name
Test status
Simulation time 14779950 ps
CPU time 0.74 seconds
Started Jul 24 07:09:40 PM PDT 24
Finished Jul 24 07:09:41 PM PDT 24
Peak memory 199664 kb
Host smart-ad0524c4-7918-46e5-9e33-5bd1030df43a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106712385 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.3106712385
Directory /workspace/42.clkmgr_clk_status/latest

Test location /workspace/coverage/default/42.clkmgr_div_intersig_mubi.1728225481
Short name T362
Test name
Test status
Simulation time 24231057 ps
CPU time 0.88 seconds
Started Jul 24 07:09:50 PM PDT 24
Finished Jul 24 07:09:51 PM PDT 24
Peak memory 200448 kb
Host smart-c9b1dca7-0bff-4617-9cbd-2c3f210d1a45
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728225481 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_div_intersig_mubi.1728225481
Directory /workspace/42.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_extclk.4291829454
Short name T621
Test name
Test status
Simulation time 47841102 ps
CPU time 0.86 seconds
Started Jul 24 07:09:39 PM PDT 24
Finished Jul 24 07:09:41 PM PDT 24
Peak memory 200464 kb
Host smart-9025b3d9-776b-46c6-b078-5857ac678fad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291829454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.4291829454
Directory /workspace/42.clkmgr_extclk/latest

Test location /workspace/coverage/default/42.clkmgr_frequency.3672871150
Short name T575
Test name
Test status
Simulation time 1780479870 ps
CPU time 8.27 seconds
Started Jul 24 07:09:35 PM PDT 24
Finished Jul 24 07:09:43 PM PDT 24
Peak memory 200660 kb
Host smart-96fc68b6-9c18-40e7-86be-ec7ba8fd1f39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672871150 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.3672871150
Directory /workspace/42.clkmgr_frequency/latest

Test location /workspace/coverage/default/42.clkmgr_frequency_timeout.1562162658
Short name T326
Test name
Test status
Simulation time 742405204 ps
CPU time 4.25 seconds
Started Jul 24 07:09:32 PM PDT 24
Finished Jul 24 07:09:37 PM PDT 24
Peak memory 200572 kb
Host smart-4f56420a-c2c4-46a1-ba41-f717319a2fb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562162658 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_t
imeout.1562162658
Directory /workspace/42.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/42.clkmgr_idle_intersig_mubi.699651763
Short name T612
Test name
Test status
Simulation time 16271172 ps
CPU time 0.78 seconds
Started Jul 24 07:09:35 PM PDT 24
Finished Jul 24 07:09:36 PM PDT 24
Peak memory 200456 kb
Host smart-7c9a7c78-b681-4c6c-adac-ff75db3a4c91
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699651763 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.clkmgr_idle_intersig_mubi.699651763
Directory /workspace/42.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.1772116023
Short name T171
Test name
Test status
Simulation time 16269864 ps
CPU time 0.77 seconds
Started Jul 24 07:09:37 PM PDT 24
Finished Jul 24 07:09:38 PM PDT 24
Peak memory 200496 kb
Host smart-052bcac7-0375-450c-a26d-e149cca40dfe
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772116023 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.clkmgr_lc_clk_byp_req_intersig_mubi.1772116023
Directory /workspace/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.270226236
Short name T591
Test name
Test status
Simulation time 33924803 ps
CPU time 0.92 seconds
Started Jul 24 07:09:40 PM PDT 24
Finished Jul 24 07:09:42 PM PDT 24
Peak memory 200456 kb
Host smart-3772cc23-433e-479d-8de8-5cf3ae57496a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270226236 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 42.clkmgr_lc_ctrl_intersig_mubi.270226236
Directory /workspace/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_peri.290826520
Short name T50
Test name
Test status
Simulation time 26920232 ps
CPU time 0.8 seconds
Started Jul 24 07:09:39 PM PDT 24
Finished Jul 24 07:09:41 PM PDT 24
Peak memory 200436 kb
Host smart-91715da4-6164-4c81-a8c2-9c773801fa0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290826520 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.290826520
Directory /workspace/42.clkmgr_peri/latest

Test location /workspace/coverage/default/42.clkmgr_regwen.3279729835
Short name T573
Test name
Test status
Simulation time 532451826 ps
CPU time 3.25 seconds
Started Jul 24 07:09:39 PM PDT 24
Finished Jul 24 07:09:43 PM PDT 24
Peak memory 200464 kb
Host smart-dac9c783-ca0e-46e3-8618-61cf2df39f8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279729835 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.3279729835
Directory /workspace/42.clkmgr_regwen/latest

Test location /workspace/coverage/default/42.clkmgr_smoke.2971752443
Short name T585
Test name
Test status
Simulation time 40275397 ps
CPU time 0.86 seconds
Started Jul 24 07:09:37 PM PDT 24
Finished Jul 24 07:09:38 PM PDT 24
Peak memory 200412 kb
Host smart-1fe7e927-31bd-4408-9e92-92345fe962a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971752443 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.2971752443
Directory /workspace/42.clkmgr_smoke/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all.1887054651
Short name T478
Test name
Test status
Simulation time 7616617638 ps
CPU time 41.33 seconds
Started Jul 24 07:09:38 PM PDT 24
Finished Jul 24 07:10:20 PM PDT 24
Peak memory 200800 kb
Host smart-dcc2e6f2-00b0-4f88-a19e-c0a82dc6a0c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887054651 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_stress_all.1887054651
Directory /workspace/42.clkmgr_stress_all/latest

Test location /workspace/coverage/default/42.clkmgr_trans.159144184
Short name T789
Test name
Test status
Simulation time 43555854 ps
CPU time 0.83 seconds
Started Jul 24 07:09:29 PM PDT 24
Finished Jul 24 07:09:30 PM PDT 24
Peak memory 200488 kb
Host smart-d0136305-9db8-4a7e-ab7a-019804636ead
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159144184 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.159144184
Directory /workspace/42.clkmgr_trans/latest

Test location /workspace/coverage/default/43.clkmgr_alert_test.3304644326
Short name T808
Test name
Test status
Simulation time 18005590 ps
CPU time 0.85 seconds
Started Jul 24 07:09:39 PM PDT 24
Finished Jul 24 07:09:40 PM PDT 24
Peak memory 200548 kb
Host smart-2c607430-c7bf-4034-bc3a-103735e95505
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304644326 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clk
mgr_alert_test.3304644326
Directory /workspace/43.clkmgr_alert_test/latest

Test location /workspace/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.4093297275
Short name T784
Test name
Test status
Simulation time 18567380 ps
CPU time 0.76 seconds
Started Jul 24 07:09:44 PM PDT 24
Finished Jul 24 07:09:45 PM PDT 24
Peak memory 200684 kb
Host smart-603da0f1-1b87-481c-8dc9-176d5b9aad2d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093297275 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_clk_handshake_intersig_mubi.4093297275
Directory /workspace/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_clk_status.1488446455
Short name T795
Test name
Test status
Simulation time 29014060 ps
CPU time 0.72 seconds
Started Jul 24 07:09:42 PM PDT 24
Finished Jul 24 07:09:43 PM PDT 24
Peak memory 199664 kb
Host smart-a7901cb0-b6b4-48c5-92c9-537a0da24ac8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488446455 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.1488446455
Directory /workspace/43.clkmgr_clk_status/latest

Test location /workspace/coverage/default/43.clkmgr_div_intersig_mubi.200023604
Short name T347
Test name
Test status
Simulation time 86561265 ps
CPU time 1.04 seconds
Started Jul 24 07:09:38 PM PDT 24
Finished Jul 24 07:09:40 PM PDT 24
Peak memory 200444 kb
Host smart-decb0279-197f-4ad3-92e7-2398347678c7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200023604 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.clkmgr_div_intersig_mubi.200023604
Directory /workspace/43.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_extclk.3744901485
Short name T697
Test name
Test status
Simulation time 42547040 ps
CPU time 0.85 seconds
Started Jul 24 07:09:38 PM PDT 24
Finished Jul 24 07:09:39 PM PDT 24
Peak memory 200492 kb
Host smart-43bf7e95-1c58-4160-89d4-fc5bb36e6810
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744901485 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.3744901485
Directory /workspace/43.clkmgr_extclk/latest

Test location /workspace/coverage/default/43.clkmgr_frequency.3105405833
Short name T1
Test name
Test status
Simulation time 1229954993 ps
CPU time 6.07 seconds
Started Jul 24 07:09:39 PM PDT 24
Finished Jul 24 07:09:46 PM PDT 24
Peak memory 200388 kb
Host smart-78ffd8a7-fbe9-4b0f-825b-c0372a46c21c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105405833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.3105405833
Directory /workspace/43.clkmgr_frequency/latest

Test location /workspace/coverage/default/43.clkmgr_frequency_timeout.3638438768
Short name T644
Test name
Test status
Simulation time 1750585250 ps
CPU time 7.58 seconds
Started Jul 24 07:09:39 PM PDT 24
Finished Jul 24 07:09:48 PM PDT 24
Peak memory 200560 kb
Host smart-69f18ddb-513f-4842-bbdb-84f675c8efdb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638438768 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_t
imeout.3638438768
Directory /workspace/43.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/43.clkmgr_idle_intersig_mubi.1841605709
Short name T267
Test name
Test status
Simulation time 142767499 ps
CPU time 1.36 seconds
Started Jul 24 07:09:40 PM PDT 24
Finished Jul 24 07:09:42 PM PDT 24
Peak memory 200508 kb
Host smart-18449b0d-66a0-421c-b4bb-c560eff0b896
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841605709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_idle_intersig_mubi.1841605709
Directory /workspace/43.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.269080978
Short name T411
Test name
Test status
Simulation time 59185423 ps
CPU time 0.97 seconds
Started Jul 24 07:09:39 PM PDT 24
Finished Jul 24 07:09:40 PM PDT 24
Peak memory 200420 kb
Host smart-eadb3db3-cb32-458c-b66e-0a2a81eeff67
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269080978 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 43.clkmgr_lc_clk_byp_req_intersig_mubi.269080978
Directory /workspace/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.2331111799
Short name T378
Test name
Test status
Simulation time 62711291 ps
CPU time 0.98 seconds
Started Jul 24 07:09:39 PM PDT 24
Finished Jul 24 07:09:41 PM PDT 24
Peak memory 200444 kb
Host smart-42625d09-a986-4881-a67b-5016e22516a0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331111799 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 43.clkmgr_lc_ctrl_intersig_mubi.2331111799
Directory /workspace/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_peri.3055162475
Short name T77
Test name
Test status
Simulation time 17361247 ps
CPU time 0.77 seconds
Started Jul 24 07:09:42 PM PDT 24
Finished Jul 24 07:09:44 PM PDT 24
Peak memory 200444 kb
Host smart-eae8d01f-42eb-4a08-b4c4-8d1ba944dbdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055162475 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.3055162475
Directory /workspace/43.clkmgr_peri/latest

Test location /workspace/coverage/default/43.clkmgr_regwen.147672585
Short name T250
Test name
Test status
Simulation time 880613068 ps
CPU time 5.6 seconds
Started Jul 24 07:09:44 PM PDT 24
Finished Jul 24 07:09:50 PM PDT 24
Peak memory 200628 kb
Host smart-9fe13f33-f997-4db3-ac77-06464b682891
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147672585 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.147672585
Directory /workspace/43.clkmgr_regwen/latest

Test location /workspace/coverage/default/43.clkmgr_smoke.2052095293
Short name T721
Test name
Test status
Simulation time 36262213 ps
CPU time 0.93 seconds
Started Jul 24 07:09:43 PM PDT 24
Finished Jul 24 07:09:44 PM PDT 24
Peak memory 200416 kb
Host smart-96b706f9-cc91-44c4-bfa6-c74267f369fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052095293 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.2052095293
Directory /workspace/43.clkmgr_smoke/latest

Test location /workspace/coverage/default/43.clkmgr_stress_all.630175751
Short name T561
Test name
Test status
Simulation time 11212226987 ps
CPU time 38.43 seconds
Started Jul 24 07:09:37 PM PDT 24
Finished Jul 24 07:10:16 PM PDT 24
Peak memory 200788 kb
Host smart-26e3df41-49c0-4f44-9ad4-6f84acf56c79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630175751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_stress_all.630175751
Directory /workspace/43.clkmgr_stress_all/latest

Test location /workspace/coverage/default/43.clkmgr_trans.2120888410
Short name T650
Test name
Test status
Simulation time 33013488 ps
CPU time 0.85 seconds
Started Jul 24 07:09:37 PM PDT 24
Finished Jul 24 07:09:38 PM PDT 24
Peak memory 200468 kb
Host smart-9339fd0b-8679-4145-9722-ce2f0e999aaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120888410 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.2120888410
Directory /workspace/43.clkmgr_trans/latest

Test location /workspace/coverage/default/44.clkmgr_alert_test.879554829
Short name T634
Test name
Test status
Simulation time 36734254 ps
CPU time 0.81 seconds
Started Jul 24 07:09:38 PM PDT 24
Finished Jul 24 07:09:40 PM PDT 24
Peak memory 200540 kb
Host smart-18ab7eed-1d00-4ae5-9e5e-53ddbf88d287
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879554829 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkm
gr_alert_test.879554829
Directory /workspace/44.clkmgr_alert_test/latest

Test location /workspace/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.1246765123
Short name T280
Test name
Test status
Simulation time 20064363 ps
CPU time 0.74 seconds
Started Jul 24 07:09:43 PM PDT 24
Finished Jul 24 07:09:44 PM PDT 24
Peak memory 200396 kb
Host smart-357f9838-eb96-4c28-80b8-5c656dffd62e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246765123 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_clk_handshake_intersig_mubi.1246765123
Directory /workspace/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_clk_status.1648954123
Short name T159
Test name
Test status
Simulation time 29420375 ps
CPU time 0.77 seconds
Started Jul 24 07:09:39 PM PDT 24
Finished Jul 24 07:09:40 PM PDT 24
Peak memory 200384 kb
Host smart-2b813146-00db-4731-94c0-b29daf6d8fa4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648954123 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.1648954123
Directory /workspace/44.clkmgr_clk_status/latest

Test location /workspace/coverage/default/44.clkmgr_div_intersig_mubi.3906462485
Short name T457
Test name
Test status
Simulation time 42458831 ps
CPU time 0.99 seconds
Started Jul 24 07:09:41 PM PDT 24
Finished Jul 24 07:09:42 PM PDT 24
Peak memory 200508 kb
Host smart-ca3c0bb4-62cf-4f12-9876-a5519894454d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906462485 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_div_intersig_mubi.3906462485
Directory /workspace/44.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_extclk.486844105
Short name T735
Test name
Test status
Simulation time 43891507 ps
CPU time 0.9 seconds
Started Jul 24 07:09:39 PM PDT 24
Finished Jul 24 07:09:41 PM PDT 24
Peak memory 200472 kb
Host smart-a91fdb1c-2776-4d2d-a161-06813a9927ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486844105 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.486844105
Directory /workspace/44.clkmgr_extclk/latest

Test location /workspace/coverage/default/44.clkmgr_frequency.2692298223
Short name T515
Test name
Test status
Simulation time 1637113238 ps
CPU time 12.99 seconds
Started Jul 24 07:09:41 PM PDT 24
Finished Jul 24 07:09:54 PM PDT 24
Peak memory 200480 kb
Host smart-957df00a-b7e2-4129-aeba-8df92c64f25f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692298223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.2692298223
Directory /workspace/44.clkmgr_frequency/latest

Test location /workspace/coverage/default/44.clkmgr_frequency_timeout.2050005429
Short name T364
Test name
Test status
Simulation time 396150421 ps
CPU time 2.13 seconds
Started Jul 24 07:09:39 PM PDT 24
Finished Jul 24 07:09:41 PM PDT 24
Peak memory 200512 kb
Host smart-548a5c2d-5974-4b2c-83f8-46b3fb237594
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050005429 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_t
imeout.2050005429
Directory /workspace/44.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/44.clkmgr_idle_intersig_mubi.782919152
Short name T334
Test name
Test status
Simulation time 50453212 ps
CPU time 0.96 seconds
Started Jul 24 07:09:37 PM PDT 24
Finished Jul 24 07:09:38 PM PDT 24
Peak memory 200428 kb
Host smart-f9ed094a-90a8-4e59-ac02-9514463f2120
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782919152 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.clkmgr_idle_intersig_mubi.782919152
Directory /workspace/44.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.962575857
Short name T707
Test name
Test status
Simulation time 72844101 ps
CPU time 1.04 seconds
Started Jul 24 07:09:48 PM PDT 24
Finished Jul 24 07:09:50 PM PDT 24
Peak memory 200460 kb
Host smart-6eb58078-cb1a-4007-9629-095a754905a4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962575857 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 44.clkmgr_lc_clk_byp_req_intersig_mubi.962575857
Directory /workspace/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.1126501939
Short name T494
Test name
Test status
Simulation time 21790142 ps
CPU time 0.82 seconds
Started Jul 24 07:09:44 PM PDT 24
Finished Jul 24 07:09:45 PM PDT 24
Peak memory 200408 kb
Host smart-94d2e8c3-c448-49ae-83c8-2086e4cfa216
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126501939 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.clkmgr_lc_ctrl_intersig_mubi.1126501939
Directory /workspace/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_peri.722164242
Short name T756
Test name
Test status
Simulation time 52756469 ps
CPU time 0.88 seconds
Started Jul 24 07:09:46 PM PDT 24
Finished Jul 24 07:09:47 PM PDT 24
Peak memory 200548 kb
Host smart-803a99de-b262-4b53-a198-1b09396e7464
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722164242 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.722164242
Directory /workspace/44.clkmgr_peri/latest

Test location /workspace/coverage/default/44.clkmgr_regwen.1096983467
Short name T386
Test name
Test status
Simulation time 640892782 ps
CPU time 3.91 seconds
Started Jul 24 07:09:46 PM PDT 24
Finished Jul 24 07:09:50 PM PDT 24
Peak memory 200644 kb
Host smart-15804762-1c0d-4361-990c-d13d16a40087
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096983467 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.1096983467
Directory /workspace/44.clkmgr_regwen/latest

Test location /workspace/coverage/default/44.clkmgr_smoke.1453241167
Short name T456
Test name
Test status
Simulation time 22338517 ps
CPU time 0.86 seconds
Started Jul 24 07:09:39 PM PDT 24
Finished Jul 24 07:09:40 PM PDT 24
Peak memory 200476 kb
Host smart-aa423456-aba2-4bfa-8f2d-7065038dc745
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453241167 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.1453241167
Directory /workspace/44.clkmgr_smoke/latest

Test location /workspace/coverage/default/44.clkmgr_stress_all.1347932445
Short name T775
Test name
Test status
Simulation time 4599439088 ps
CPU time 19.31 seconds
Started Jul 24 07:09:40 PM PDT 24
Finished Jul 24 07:10:00 PM PDT 24
Peak memory 200776 kb
Host smart-e6fe29af-e234-49db-a270-cf4fa7750739
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347932445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_stress_all.1347932445
Directory /workspace/44.clkmgr_stress_all/latest

Test location /workspace/coverage/default/44.clkmgr_stress_all_with_rand_reset.88216569
Short name T704
Test name
Test status
Simulation time 156029271195 ps
CPU time 1030.26 seconds
Started Jul 24 07:09:39 PM PDT 24
Finished Jul 24 07:26:51 PM PDT 24
Peak memory 217300 kb
Host smart-892f8bbd-46df-4ab3-bf4a-b6c2cad66f6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=88216569 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all_with_rand_reset.88216569
Directory /workspace/44.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.clkmgr_trans.1797227675
Short name T452
Test name
Test status
Simulation time 23584824 ps
CPU time 0.92 seconds
Started Jul 24 07:09:41 PM PDT 24
Finished Jul 24 07:09:43 PM PDT 24
Peak memory 200436 kb
Host smart-7fa25779-2061-4c50-924b-d85ad6dc52e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797227675 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.1797227675
Directory /workspace/44.clkmgr_trans/latest

Test location /workspace/coverage/default/45.clkmgr_alert_test.1876133256
Short name T372
Test name
Test status
Simulation time 14745080 ps
CPU time 0.75 seconds
Started Jul 24 07:09:48 PM PDT 24
Finished Jul 24 07:09:49 PM PDT 24
Peak memory 200440 kb
Host smart-47effe12-efeb-4410-860e-704e40a0dc96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876133256 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clk
mgr_alert_test.1876133256
Directory /workspace/45.clkmgr_alert_test/latest

Test location /workspace/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.3639139627
Short name T653
Test name
Test status
Simulation time 65152223 ps
CPU time 0.98 seconds
Started Jul 24 07:09:47 PM PDT 24
Finished Jul 24 07:09:48 PM PDT 24
Peak memory 200400 kb
Host smart-275c97a4-716e-4b25-8823-a28fc75fc725
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639139627 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_clk_handshake_intersig_mubi.3639139627
Directory /workspace/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_clk_status.3433417559
Short name T370
Test name
Test status
Simulation time 87749554 ps
CPU time 0.92 seconds
Started Jul 24 07:10:04 PM PDT 24
Finished Jul 24 07:10:05 PM PDT 24
Peak memory 199680 kb
Host smart-37d5927b-bbcb-4b8e-8a50-6f4683011071
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433417559 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.3433417559
Directory /workspace/45.clkmgr_clk_status/latest

Test location /workspace/coverage/default/45.clkmgr_div_intersig_mubi.2310079906
Short name T207
Test name
Test status
Simulation time 45106531 ps
CPU time 0.81 seconds
Started Jul 24 07:09:47 PM PDT 24
Finished Jul 24 07:09:48 PM PDT 24
Peak memory 200468 kb
Host smart-981d4423-7d4b-4bf0-a747-077194363d4a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310079906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_div_intersig_mubi.2310079906
Directory /workspace/45.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_extclk.335886540
Short name T479
Test name
Test status
Simulation time 27033478 ps
CPU time 0.8 seconds
Started Jul 24 07:09:38 PM PDT 24
Finished Jul 24 07:09:39 PM PDT 24
Peak memory 200532 kb
Host smart-ba5d1982-dfeb-4d45-b8d5-35486b9c8751
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335886540 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.335886540
Directory /workspace/45.clkmgr_extclk/latest

Test location /workspace/coverage/default/45.clkmgr_frequency.1097231915
Short name T642
Test name
Test status
Simulation time 2000581689 ps
CPU time 15.77 seconds
Started Jul 24 07:09:39 PM PDT 24
Finished Jul 24 07:09:56 PM PDT 24
Peak memory 200688 kb
Host smart-5eb4dfa1-25ea-4fb0-8954-272e5e088bd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097231915 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.1097231915
Directory /workspace/45.clkmgr_frequency/latest

Test location /workspace/coverage/default/45.clkmgr_frequency_timeout.3856830426
Short name T361
Test name
Test status
Simulation time 195252088 ps
CPU time 1.3 seconds
Started Jul 24 07:09:49 PM PDT 24
Finished Jul 24 07:09:50 PM PDT 24
Peak memory 200420 kb
Host smart-d588b929-fe13-4d50-b493-d902dae24d78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856830426 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_t
imeout.3856830426
Directory /workspace/45.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/45.clkmgr_idle_intersig_mubi.2330622515
Short name T168
Test name
Test status
Simulation time 56702546 ps
CPU time 0.89 seconds
Started Jul 24 07:09:46 PM PDT 24
Finished Jul 24 07:09:47 PM PDT 24
Peak memory 200484 kb
Host smart-13cd0dfa-fc23-43d5-a5bf-cced3b75af4f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330622515 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_idle_intersig_mubi.2330622515
Directory /workspace/45.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.395475535
Short name T509
Test name
Test status
Simulation time 18524619 ps
CPU time 0.76 seconds
Started Jul 24 07:09:46 PM PDT 24
Finished Jul 24 07:09:47 PM PDT 24
Peak memory 200500 kb
Host smart-582c1921-685d-483a-9e74-2f1684045e7e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395475535 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 45.clkmgr_lc_clk_byp_req_intersig_mubi.395475535
Directory /workspace/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.1401271691
Short name T312
Test name
Test status
Simulation time 23231779 ps
CPU time 0.85 seconds
Started Jul 24 07:09:45 PM PDT 24
Finished Jul 24 07:09:46 PM PDT 24
Peak memory 200508 kb
Host smart-89341a6b-40e0-4fde-80fd-c8407b745d65
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401271691 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.clkmgr_lc_ctrl_intersig_mubi.1401271691
Directory /workspace/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_peri.2126129955
Short name T331
Test name
Test status
Simulation time 16406576 ps
CPU time 0.79 seconds
Started Jul 24 07:09:47 PM PDT 24
Finished Jul 24 07:09:48 PM PDT 24
Peak memory 200388 kb
Host smart-9b39ec35-4b00-4d9a-b1ce-9b70c617b5bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126129955 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.2126129955
Directory /workspace/45.clkmgr_peri/latest

Test location /workspace/coverage/default/45.clkmgr_regwen.2774460022
Short name T249
Test name
Test status
Simulation time 217301243 ps
CPU time 1.39 seconds
Started Jul 24 07:09:55 PM PDT 24
Finished Jul 24 07:09:56 PM PDT 24
Peak memory 200388 kb
Host smart-0af5aaf6-d9e1-40a3-91ef-379b5c012445
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774460022 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.2774460022
Directory /workspace/45.clkmgr_regwen/latest

Test location /workspace/coverage/default/45.clkmgr_smoke.1980075287
Short name T578
Test name
Test status
Simulation time 75762200 ps
CPU time 1.12 seconds
Started Jul 24 07:09:37 PM PDT 24
Finished Jul 24 07:09:39 PM PDT 24
Peak memory 200396 kb
Host smart-ce0820b0-e99f-4ef1-8b9f-f935e8444d8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980075287 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.1980075287
Directory /workspace/45.clkmgr_smoke/latest

Test location /workspace/coverage/default/45.clkmgr_stress_all.1429980832
Short name T37
Test name
Test status
Simulation time 10410203747 ps
CPU time 74.8 seconds
Started Jul 24 07:09:49 PM PDT 24
Finished Jul 24 07:11:04 PM PDT 24
Peak memory 200760 kb
Host smart-3ba5afdc-d9b6-4012-8884-b26d00cf87d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429980832 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_stress_all.1429980832
Directory /workspace/45.clkmgr_stress_all/latest

Test location /workspace/coverage/default/45.clkmgr_trans.1767077478
Short name T461
Test name
Test status
Simulation time 37138055 ps
CPU time 1.09 seconds
Started Jul 24 07:09:54 PM PDT 24
Finished Jul 24 07:09:55 PM PDT 24
Peak memory 200456 kb
Host smart-af7ed9ad-2263-434d-975e-96a43441aa2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767077478 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.1767077478
Directory /workspace/45.clkmgr_trans/latest

Test location /workspace/coverage/default/46.clkmgr_alert_test.3297750012
Short name T559
Test name
Test status
Simulation time 15879881 ps
CPU time 0.79 seconds
Started Jul 24 07:09:45 PM PDT 24
Finished Jul 24 07:09:46 PM PDT 24
Peak memory 200456 kb
Host smart-078db2b0-ac41-465d-9f9f-ed56da2111ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297750012 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clk
mgr_alert_test.3297750012
Directory /workspace/46.clkmgr_alert_test/latest

Test location /workspace/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.780532122
Short name T587
Test name
Test status
Simulation time 111985081 ps
CPU time 1.19 seconds
Started Jul 24 07:09:59 PM PDT 24
Finished Jul 24 07:10:00 PM PDT 24
Peak memory 200508 kb
Host smart-49d3c4f2-be9d-443e-b1e7-5168515b1c44
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780532122 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_clk_handshake_intersig_mubi.780532122
Directory /workspace/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_clk_status.1846507224
Short name T517
Test name
Test status
Simulation time 39814714 ps
CPU time 0.79 seconds
Started Jul 24 07:09:46 PM PDT 24
Finished Jul 24 07:09:47 PM PDT 24
Peak memory 199668 kb
Host smart-1bd3ae27-4949-41dc-be44-e171dcfb1281
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846507224 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.1846507224
Directory /workspace/46.clkmgr_clk_status/latest

Test location /workspace/coverage/default/46.clkmgr_div_intersig_mubi.50167831
Short name T399
Test name
Test status
Simulation time 21736332 ps
CPU time 0.86 seconds
Started Jul 24 07:09:45 PM PDT 24
Finished Jul 24 07:09:46 PM PDT 24
Peak memory 200476 kb
Host smart-b47cf056-4b11-4f17-8cff-63b81c757589
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50167831 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.clkmgr_div_intersig_mubi.50167831
Directory /workspace/46.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_extclk.2308010839
Short name T274
Test name
Test status
Simulation time 16472038 ps
CPU time 0.77 seconds
Started Jul 24 07:09:47 PM PDT 24
Finished Jul 24 07:09:48 PM PDT 24
Peak memory 200512 kb
Host smart-76c315a5-d9b1-470e-a65c-165aebd76e33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308010839 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.2308010839
Directory /workspace/46.clkmgr_extclk/latest

Test location /workspace/coverage/default/46.clkmgr_frequency.1338759275
Short name T609
Test name
Test status
Simulation time 803449573 ps
CPU time 5.77 seconds
Started Jul 24 07:09:54 PM PDT 24
Finished Jul 24 07:10:00 PM PDT 24
Peak memory 200468 kb
Host smart-4164ce91-1baa-4882-81e5-5a0e451e83c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338759275 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.1338759275
Directory /workspace/46.clkmgr_frequency/latest

Test location /workspace/coverage/default/46.clkmgr_frequency_timeout.1400899798
Short name T543
Test name
Test status
Simulation time 1503388805 ps
CPU time 5.45 seconds
Started Jul 24 07:09:53 PM PDT 24
Finished Jul 24 07:09:59 PM PDT 24
Peak memory 200540 kb
Host smart-8b750caa-8781-4bc3-9490-c17254563f77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400899798 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_t
imeout.1400899798
Directory /workspace/46.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/46.clkmgr_idle_intersig_mubi.1589824356
Short name T576
Test name
Test status
Simulation time 115408838 ps
CPU time 1.22 seconds
Started Jul 24 07:09:45 PM PDT 24
Finished Jul 24 07:09:47 PM PDT 24
Peak memory 200408 kb
Host smart-5f5a6031-507b-4d6e-b629-fa4873476c27
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589824356 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_idle_intersig_mubi.1589824356
Directory /workspace/46.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.3074309495
Short name T394
Test name
Test status
Simulation time 58145090 ps
CPU time 0.96 seconds
Started Jul 24 07:09:49 PM PDT 24
Finished Jul 24 07:09:50 PM PDT 24
Peak memory 200376 kb
Host smart-ecbbd07e-a737-4e9a-ac53-5c84c07260fe
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074309495 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.clkmgr_lc_clk_byp_req_intersig_mubi.3074309495
Directory /workspace/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.3989239678
Short name T271
Test name
Test status
Simulation time 46460348 ps
CPU time 1.01 seconds
Started Jul 24 07:09:57 PM PDT 24
Finished Jul 24 07:09:58 PM PDT 24
Peak memory 200448 kb
Host smart-a5e7a1d6-3425-4e25-bb08-e011ec92ef96
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989239678 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.clkmgr_lc_ctrl_intersig_mubi.3989239678
Directory /workspace/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_peri.3495852049
Short name T211
Test name
Test status
Simulation time 18841041 ps
CPU time 0.78 seconds
Started Jul 24 07:09:49 PM PDT 24
Finished Jul 24 07:09:50 PM PDT 24
Peak memory 200472 kb
Host smart-7c3a584f-dca3-4140-9b63-d0d3de7dffe8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495852049 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.3495852049
Directory /workspace/46.clkmgr_peri/latest

Test location /workspace/coverage/default/46.clkmgr_regwen.2624244099
Short name T623
Test name
Test status
Simulation time 345275141 ps
CPU time 1.73 seconds
Started Jul 24 07:09:46 PM PDT 24
Finished Jul 24 07:09:48 PM PDT 24
Peak memory 200488 kb
Host smart-6d8cd66a-0db8-4ea5-ab96-d806d07646d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624244099 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.2624244099
Directory /workspace/46.clkmgr_regwen/latest

Test location /workspace/coverage/default/46.clkmgr_smoke.569647072
Short name T344
Test name
Test status
Simulation time 17724237 ps
CPU time 0.86 seconds
Started Jul 24 07:09:46 PM PDT 24
Finished Jul 24 07:09:47 PM PDT 24
Peak memory 200376 kb
Host smart-c6d6f8ca-c1e0-4a68-bc0e-2c5b5048acd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569647072 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.569647072
Directory /workspace/46.clkmgr_smoke/latest

Test location /workspace/coverage/default/46.clkmgr_stress_all.3357561230
Short name T2
Test name
Test status
Simulation time 8123272637 ps
CPU time 43.93 seconds
Started Jul 24 07:09:53 PM PDT 24
Finished Jul 24 07:10:37 PM PDT 24
Peak memory 200796 kb
Host smart-e17dec10-e0ac-4d78-99b1-2c5eda6ab09b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357561230 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_stress_all.3357561230
Directory /workspace/46.clkmgr_stress_all/latest

Test location /workspace/coverage/default/46.clkmgr_trans.1272841442
Short name T261
Test name
Test status
Simulation time 65908475 ps
CPU time 0.92 seconds
Started Jul 24 07:09:46 PM PDT 24
Finished Jul 24 07:09:47 PM PDT 24
Peak memory 200532 kb
Host smart-b1f6032d-c4f0-4376-9a8b-f73b930f9f3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272841442 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.1272841442
Directory /workspace/46.clkmgr_trans/latest

Test location /workspace/coverage/default/47.clkmgr_alert_test.2095330182
Short name T554
Test name
Test status
Simulation time 20172988 ps
CPU time 0.85 seconds
Started Jul 24 07:10:01 PM PDT 24
Finished Jul 24 07:10:02 PM PDT 24
Peak memory 200548 kb
Host smart-c3fe50b7-cbe9-4e62-8ae5-8069eb11a30e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095330182 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clk
mgr_alert_test.2095330182
Directory /workspace/47.clkmgr_alert_test/latest

Test location /workspace/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.2022096255
Short name T773
Test name
Test status
Simulation time 23316925 ps
CPU time 0.78 seconds
Started Jul 24 07:09:56 PM PDT 24
Finished Jul 24 07:09:57 PM PDT 24
Peak memory 200528 kb
Host smart-e22ea78b-4274-4321-98c9-58be37932472
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022096255 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_clk_handshake_intersig_mubi.2022096255
Directory /workspace/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_clk_status.261554539
Short name T241
Test name
Test status
Simulation time 27991224 ps
CPU time 0.76 seconds
Started Jul 24 07:09:54 PM PDT 24
Finished Jul 24 07:09:55 PM PDT 24
Peak memory 200404 kb
Host smart-293a650c-35f1-4f0a-b357-6bcc8e6d4784
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261554539 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.261554539
Directory /workspace/47.clkmgr_clk_status/latest

Test location /workspace/coverage/default/47.clkmgr_div_intersig_mubi.2390679469
Short name T262
Test name
Test status
Simulation time 25018152 ps
CPU time 0.9 seconds
Started Jul 24 07:09:55 PM PDT 24
Finished Jul 24 07:09:56 PM PDT 24
Peak memory 200692 kb
Host smart-e25cd812-bb44-4cca-ac5b-82a44fe506ea
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390679469 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_div_intersig_mubi.2390679469
Directory /workspace/47.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_extclk.1357743055
Short name T352
Test name
Test status
Simulation time 42354036 ps
CPU time 0.83 seconds
Started Jul 24 07:09:56 PM PDT 24
Finished Jul 24 07:09:57 PM PDT 24
Peak memory 200408 kb
Host smart-aab8f7b0-0511-4ef7-a048-198afb5e1103
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357743055 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.1357743055
Directory /workspace/47.clkmgr_extclk/latest

Test location /workspace/coverage/default/47.clkmgr_frequency.2825420669
Short name T732
Test name
Test status
Simulation time 443604323 ps
CPU time 3.86 seconds
Started Jul 24 07:10:14 PM PDT 24
Finished Jul 24 07:10:18 PM PDT 24
Peak memory 200492 kb
Host smart-911721cf-6fd1-4287-bf8d-efa568bd8917
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825420669 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.2825420669
Directory /workspace/47.clkmgr_frequency/latest

Test location /workspace/coverage/default/47.clkmgr_frequency_timeout.1954833925
Short name T290
Test name
Test status
Simulation time 2041798103 ps
CPU time 8.58 seconds
Started Jul 24 07:09:56 PM PDT 24
Finished Jul 24 07:10:04 PM PDT 24
Peak memory 200532 kb
Host smart-6b27b2fe-a675-414e-a34c-2577bed155a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954833925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_t
imeout.1954833925
Directory /workspace/47.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/47.clkmgr_idle_intersig_mubi.1555379940
Short name T112
Test name
Test status
Simulation time 65894318 ps
CPU time 0.87 seconds
Started Jul 24 07:10:04 PM PDT 24
Finished Jul 24 07:10:05 PM PDT 24
Peak memory 200460 kb
Host smart-f88e5e93-0cc7-46b8-bd46-b0ec913923b5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555379940 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_idle_intersig_mubi.1555379940
Directory /workspace/47.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.1769639789
Short name T282
Test name
Test status
Simulation time 30459879 ps
CPU time 0.87 seconds
Started Jul 24 07:09:53 PM PDT 24
Finished Jul 24 07:09:54 PM PDT 24
Peak memory 200412 kb
Host smart-a4227bb0-e26d-45f3-bf0c-b574f1799427
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769639789 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.clkmgr_lc_clk_byp_req_intersig_mubi.1769639789
Directory /workspace/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.92883574
Short name T673
Test name
Test status
Simulation time 21755878 ps
CPU time 0.91 seconds
Started Jul 24 07:10:01 PM PDT 24
Finished Jul 24 07:10:03 PM PDT 24
Peak memory 200476 kb
Host smart-3a27d0cd-15fb-4c07-aac6-b0843a03fb70
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92883574 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_lc_ctrl_intersig_mubi.92883574
Directory /workspace/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_peri.1711118891
Short name T391
Test name
Test status
Simulation time 184035760 ps
CPU time 1.25 seconds
Started Jul 24 07:09:54 PM PDT 24
Finished Jul 24 07:09:55 PM PDT 24
Peak memory 200428 kb
Host smart-43678722-ceaa-4636-802f-5f037cac84f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711118891 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.1711118891
Directory /workspace/47.clkmgr_peri/latest

Test location /workspace/coverage/default/47.clkmgr_regwen.2033079410
Short name T790
Test name
Test status
Simulation time 216927288 ps
CPU time 1.23 seconds
Started Jul 24 07:10:04 PM PDT 24
Finished Jul 24 07:10:05 PM PDT 24
Peak memory 200420 kb
Host smart-773aad84-f60b-459d-be57-3ae2180405fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033079410 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.2033079410
Directory /workspace/47.clkmgr_regwen/latest

Test location /workspace/coverage/default/47.clkmgr_smoke.560361729
Short name T528
Test name
Test status
Simulation time 16554561 ps
CPU time 0.83 seconds
Started Jul 24 07:09:46 PM PDT 24
Finished Jul 24 07:09:47 PM PDT 24
Peak memory 200468 kb
Host smart-41062828-112e-4000-92b7-bb1b8c06f16f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560361729 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.560361729
Directory /workspace/47.clkmgr_smoke/latest

Test location /workspace/coverage/default/47.clkmgr_stress_all.1864737670
Short name T251
Test name
Test status
Simulation time 43476726 ps
CPU time 0.88 seconds
Started Jul 24 07:09:56 PM PDT 24
Finished Jul 24 07:09:57 PM PDT 24
Peak memory 200412 kb
Host smart-ccfc6d4e-9977-4ac9-8419-949dd85c0bae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864737670 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_stress_all.1864737670
Directory /workspace/47.clkmgr_stress_all/latest

Test location /workspace/coverage/default/47.clkmgr_trans.3704483608
Short name T32
Test name
Test status
Simulation time 19011264 ps
CPU time 0.8 seconds
Started Jul 24 07:09:58 PM PDT 24
Finished Jul 24 07:09:59 PM PDT 24
Peak memory 200524 kb
Host smart-7650bada-9013-41af-a569-d8926c285a69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704483608 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.3704483608
Directory /workspace/47.clkmgr_trans/latest

Test location /workspace/coverage/default/48.clkmgr_alert_test.2203794884
Short name T451
Test name
Test status
Simulation time 37590953 ps
CPU time 0.86 seconds
Started Jul 24 07:10:06 PM PDT 24
Finished Jul 24 07:10:07 PM PDT 24
Peak memory 200560 kb
Host smart-3e714c88-2df1-48f2-a39e-655545b32e64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203794884 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clk
mgr_alert_test.2203794884
Directory /workspace/48.clkmgr_alert_test/latest

Test location /workspace/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.2718036586
Short name T88
Test name
Test status
Simulation time 19684676 ps
CPU time 0.93 seconds
Started Jul 24 07:09:56 PM PDT 24
Finished Jul 24 07:09:58 PM PDT 24
Peak memory 200544 kb
Host smart-93bb676a-8e80-4cf2-abc3-6b4a2b2514df
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718036586 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_clk_handshake_intersig_mubi.2718036586
Directory /workspace/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_clk_status.3565921077
Short name T332
Test name
Test status
Simulation time 27162681 ps
CPU time 0.77 seconds
Started Jul 24 07:09:57 PM PDT 24
Finished Jul 24 07:09:58 PM PDT 24
Peak memory 199716 kb
Host smart-73d245ee-4ef3-4115-ac4a-0a982756a71b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565921077 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.3565921077
Directory /workspace/48.clkmgr_clk_status/latest

Test location /workspace/coverage/default/48.clkmgr_div_intersig_mubi.474884146
Short name T246
Test name
Test status
Simulation time 53265042 ps
CPU time 0.96 seconds
Started Jul 24 07:10:02 PM PDT 24
Finished Jul 24 07:10:03 PM PDT 24
Peak memory 200448 kb
Host smart-56a6242c-27ad-4bee-acd4-b240f8eef17b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474884146 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.clkmgr_div_intersig_mubi.474884146
Directory /workspace/48.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_extclk.3780271646
Short name T247
Test name
Test status
Simulation time 73694451 ps
CPU time 1.03 seconds
Started Jul 24 07:10:00 PM PDT 24
Finished Jul 24 07:10:01 PM PDT 24
Peak memory 200476 kb
Host smart-45fd8990-a559-40b4-bf98-7bcadc2d75f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780271646 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.3780271646
Directory /workspace/48.clkmgr_extclk/latest

Test location /workspace/coverage/default/48.clkmgr_frequency.1018743227
Short name T348
Test name
Test status
Simulation time 1868353930 ps
CPU time 7.2 seconds
Started Jul 24 07:10:04 PM PDT 24
Finished Jul 24 07:10:11 PM PDT 24
Peak memory 200492 kb
Host smart-93e8e29b-ffd8-439e-ac9f-567dd21e2b69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018743227 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.1018743227
Directory /workspace/48.clkmgr_frequency/latest

Test location /workspace/coverage/default/48.clkmgr_frequency_timeout.1011499557
Short name T292
Test name
Test status
Simulation time 2060343700 ps
CPU time 14.95 seconds
Started Jul 24 07:10:03 PM PDT 24
Finished Jul 24 07:10:18 PM PDT 24
Peak memory 200732 kb
Host smart-35903344-d44d-46a3-a56a-9d0cab32c0e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011499557 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_t
imeout.1011499557
Directory /workspace/48.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/48.clkmgr_idle_intersig_mubi.1840373923
Short name T810
Test name
Test status
Simulation time 15054649 ps
CPU time 0.75 seconds
Started Jul 24 07:09:53 PM PDT 24
Finished Jul 24 07:09:59 PM PDT 24
Peak memory 200444 kb
Host smart-1377ed5d-1964-4dcd-be11-2cab84066f78
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840373923 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_idle_intersig_mubi.1840373923
Directory /workspace/48.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.3346325893
Short name T630
Test name
Test status
Simulation time 82093591 ps
CPU time 1.01 seconds
Started Jul 24 07:10:11 PM PDT 24
Finished Jul 24 07:10:12 PM PDT 24
Peak memory 200476 kb
Host smart-a56be6b9-a732-437f-850c-032cde9702e0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346325893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.clkmgr_lc_clk_byp_req_intersig_mubi.3346325893
Directory /workspace/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.550480985
Short name T698
Test name
Test status
Simulation time 74481261 ps
CPU time 1.01 seconds
Started Jul 24 07:09:58 PM PDT 24
Finished Jul 24 07:10:00 PM PDT 24
Peak memory 200468 kb
Host smart-3ca0e211-9375-43d7-90f7-94f9d39474b8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550480985 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 48.clkmgr_lc_ctrl_intersig_mubi.550480985
Directory /workspace/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_peri.3312651741
Short name T174
Test name
Test status
Simulation time 67533908 ps
CPU time 0.9 seconds
Started Jul 24 07:09:55 PM PDT 24
Finished Jul 24 07:09:56 PM PDT 24
Peak memory 200464 kb
Host smart-9bf7a2e1-cfb9-423a-acba-5c4f34302995
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312651741 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.3312651741
Directory /workspace/48.clkmgr_peri/latest

Test location /workspace/coverage/default/48.clkmgr_regwen.2375479289
Short name T700
Test name
Test status
Simulation time 1137019832 ps
CPU time 5.02 seconds
Started Jul 24 07:10:05 PM PDT 24
Finished Jul 24 07:10:10 PM PDT 24
Peak memory 200640 kb
Host smart-c6ab8f77-914f-4d87-b75b-d30ca935ad3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375479289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.2375479289
Directory /workspace/48.clkmgr_regwen/latest

Test location /workspace/coverage/default/48.clkmgr_smoke.778518422
Short name T319
Test name
Test status
Simulation time 54270180 ps
CPU time 0.91 seconds
Started Jul 24 07:10:05 PM PDT 24
Finished Jul 24 07:10:06 PM PDT 24
Peak memory 200436 kb
Host smart-bef489bc-9788-4de2-8d7c-f7f32cd14bf8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778518422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.778518422
Directory /workspace/48.clkmgr_smoke/latest

Test location /workspace/coverage/default/48.clkmgr_stress_all.2236172433
Short name T677
Test name
Test status
Simulation time 2493064599 ps
CPU time 10.96 seconds
Started Jul 24 07:10:04 PM PDT 24
Finished Jul 24 07:10:15 PM PDT 24
Peak memory 200736 kb
Host smart-c8e6910e-6e41-45db-bca2-f0169145f9fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236172433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_stress_all.2236172433
Directory /workspace/48.clkmgr_stress_all/latest

Test location /workspace/coverage/default/48.clkmgr_trans.799131390
Short name T786
Test name
Test status
Simulation time 239036124 ps
CPU time 1.67 seconds
Started Jul 24 07:09:59 PM PDT 24
Finished Jul 24 07:10:01 PM PDT 24
Peak memory 200420 kb
Host smart-d56ee21c-eeab-4bab-bb2c-f4d8c9cb8741
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799131390 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.799131390
Directory /workspace/48.clkmgr_trans/latest

Test location /workspace/coverage/default/49.clkmgr_alert_test.742672165
Short name T366
Test name
Test status
Simulation time 15482566 ps
CPU time 0.77 seconds
Started Jul 24 07:10:02 PM PDT 24
Finished Jul 24 07:10:03 PM PDT 24
Peak memory 200528 kb
Host smart-2f14d1c3-3713-4f29-9e50-7b7a0c81fd31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742672165 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkm
gr_alert_test.742672165
Directory /workspace/49.clkmgr_alert_test/latest

Test location /workspace/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.3400102741
Short name T21
Test name
Test status
Simulation time 49770083 ps
CPU time 0.88 seconds
Started Jul 24 07:10:10 PM PDT 24
Finished Jul 24 07:10:11 PM PDT 24
Peak memory 200512 kb
Host smart-abfa73d3-56ed-4824-854d-eb9d4114fac7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400102741 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_clk_handshake_intersig_mubi.3400102741
Directory /workspace/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_clk_status.4156010138
Short name T586
Test name
Test status
Simulation time 21411794 ps
CPU time 0.72 seconds
Started Jul 24 07:10:03 PM PDT 24
Finished Jul 24 07:10:04 PM PDT 24
Peak memory 199700 kb
Host smart-ebfda3cf-d03d-4922-a9ac-19d11e66033b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156010138 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.4156010138
Directory /workspace/49.clkmgr_clk_status/latest

Test location /workspace/coverage/default/49.clkmgr_div_intersig_mubi.3323319118
Short name T183
Test name
Test status
Simulation time 87487635 ps
CPU time 1.09 seconds
Started Jul 24 07:10:02 PM PDT 24
Finished Jul 24 07:10:04 PM PDT 24
Peak memory 200472 kb
Host smart-c378185b-48b9-48be-99b7-6f0f50ae5bff
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323319118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_div_intersig_mubi.3323319118
Directory /workspace/49.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_extclk.3285161693
Short name T22
Test name
Test status
Simulation time 21732852 ps
CPU time 0.92 seconds
Started Jul 24 07:10:02 PM PDT 24
Finished Jul 24 07:10:03 PM PDT 24
Peak memory 200496 kb
Host smart-5c44b4d0-35b0-4482-ac11-fe7ed897b908
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285161693 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.3285161693
Directory /workspace/49.clkmgr_extclk/latest

Test location /workspace/coverage/default/49.clkmgr_frequency.4289190858
Short name T720
Test name
Test status
Simulation time 2141042526 ps
CPU time 9.67 seconds
Started Jul 24 07:10:06 PM PDT 24
Finished Jul 24 07:10:16 PM PDT 24
Peak memory 200632 kb
Host smart-63389a91-8fb8-4b9d-bafc-371a1ddc8f69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289190858 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.4289190858
Directory /workspace/49.clkmgr_frequency/latest

Test location /workspace/coverage/default/49.clkmgr_frequency_timeout.1119547633
Short name T204
Test name
Test status
Simulation time 1478192923 ps
CPU time 7.02 seconds
Started Jul 24 07:09:58 PM PDT 24
Finished Jul 24 07:10:05 PM PDT 24
Peak memory 200560 kb
Host smart-2b79c368-7d13-40ab-a9bd-cc50e06ab4d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119547633 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_t
imeout.1119547633
Directory /workspace/49.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/49.clkmgr_idle_intersig_mubi.986233195
Short name T377
Test name
Test status
Simulation time 58037554 ps
CPU time 1.08 seconds
Started Jul 24 07:10:00 PM PDT 24
Finished Jul 24 07:10:02 PM PDT 24
Peak memory 200712 kb
Host smart-8ff8b61d-b886-4259-8876-21c02f74bb50
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986233195 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.clkmgr_idle_intersig_mubi.986233195
Directory /workspace/49.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.3121498242
Short name T199
Test name
Test status
Simulation time 46727353 ps
CPU time 0.85 seconds
Started Jul 24 07:09:56 PM PDT 24
Finished Jul 24 07:09:57 PM PDT 24
Peak memory 200468 kb
Host smart-ab74d9b9-de01-4ce3-8901-857cf7263222
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121498242 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.clkmgr_lc_clk_byp_req_intersig_mubi.3121498242
Directory /workspace/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.2741424459
Short name T28
Test name
Test status
Simulation time 14835083 ps
CPU time 0.78 seconds
Started Jul 24 07:09:56 PM PDT 24
Finished Jul 24 07:09:57 PM PDT 24
Peak memory 200448 kb
Host smart-fa942b39-2313-4298-9551-f3048cfb0ec7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741424459 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.clkmgr_lc_ctrl_intersig_mubi.2741424459
Directory /workspace/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_peri.2698359589
Short name T448
Test name
Test status
Simulation time 22842703 ps
CPU time 0.83 seconds
Started Jul 24 07:10:06 PM PDT 24
Finished Jul 24 07:10:07 PM PDT 24
Peak memory 200456 kb
Host smart-5e00fd65-5f9b-46a4-8973-7901b0984277
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698359589 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.2698359589
Directory /workspace/49.clkmgr_peri/latest

Test location /workspace/coverage/default/49.clkmgr_regwen.831504355
Short name T614
Test name
Test status
Simulation time 630289843 ps
CPU time 3.13 seconds
Started Jul 24 07:09:59 PM PDT 24
Finished Jul 24 07:10:02 PM PDT 24
Peak memory 200608 kb
Host smart-dc9b933d-8686-4eb5-a33f-1315ef3e3e06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831504355 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.831504355
Directory /workspace/49.clkmgr_regwen/latest

Test location /workspace/coverage/default/49.clkmgr_smoke.1875720676
Short name T300
Test name
Test status
Simulation time 23887244 ps
CPU time 0.85 seconds
Started Jul 24 07:09:58 PM PDT 24
Finished Jul 24 07:09:59 PM PDT 24
Peak memory 200460 kb
Host smart-543d1d88-ab82-461e-ba88-5629bce96bfd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875720676 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.1875720676
Directory /workspace/49.clkmgr_smoke/latest

Test location /workspace/coverage/default/49.clkmgr_stress_all.742323609
Short name T15
Test name
Test status
Simulation time 2348410554 ps
CPU time 13.47 seconds
Started Jul 24 07:10:04 PM PDT 24
Finished Jul 24 07:10:17 PM PDT 24
Peak memory 200784 kb
Host smart-f8b09464-c154-4044-a78d-a1bf8a25d2ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742323609 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_stress_all.742323609
Directory /workspace/49.clkmgr_stress_all/latest

Test location /workspace/coverage/default/49.clkmgr_stress_all_with_rand_reset.3676351499
Short name T152
Test name
Test status
Simulation time 125615784271 ps
CPU time 1136.5 seconds
Started Jul 24 07:09:57 PM PDT 24
Finished Jul 24 07:28:54 PM PDT 24
Peak memory 215420 kb
Host smart-716a7bc5-5287-43e3-a257-35001f241ba3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3676351499 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all_with_rand_reset.3676351499
Directory /workspace/49.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.clkmgr_trans.2457553536
Short name T664
Test name
Test status
Simulation time 38997260 ps
CPU time 1.05 seconds
Started Jul 24 07:10:06 PM PDT 24
Finished Jul 24 07:10:07 PM PDT 24
Peak memory 200452 kb
Host smart-4bbc638d-d527-40fe-b2f8-7ac21f25200d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457553536 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.2457553536
Directory /workspace/49.clkmgr_trans/latest

Test location /workspace/coverage/default/5.clkmgr_alert_test.306195582
Short name T466
Test name
Test status
Simulation time 22407502 ps
CPU time 0.8 seconds
Started Jul 24 07:08:06 PM PDT 24
Finished Jul 24 07:08:07 PM PDT 24
Peak memory 200544 kb
Host smart-89ba7d0f-d2e7-42ac-a071-eb1681186c8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306195582 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmg
r_alert_test.306195582
Directory /workspace/5.clkmgr_alert_test/latest

Test location /workspace/coverage/default/5.clkmgr_clk_status.1582643056
Short name T648
Test name
Test status
Simulation time 16826201 ps
CPU time 0.76 seconds
Started Jul 24 07:08:02 PM PDT 24
Finished Jul 24 07:08:03 PM PDT 24
Peak memory 199644 kb
Host smart-3efe4db7-12b4-4c20-a3f4-999a7fc232e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582643056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.1582643056
Directory /workspace/5.clkmgr_clk_status/latest

Test location /workspace/coverage/default/5.clkmgr_div_intersig_mubi.2323480675
Short name T176
Test name
Test status
Simulation time 27057807 ps
CPU time 0.8 seconds
Started Jul 24 07:08:00 PM PDT 24
Finished Jul 24 07:08:01 PM PDT 24
Peak memory 200312 kb
Host smart-b536678e-522c-405c-a929-036bec2bb7f2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323480675 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_div_intersig_mubi.2323480675
Directory /workspace/5.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_extclk.3961130291
Short name T799
Test name
Test status
Simulation time 61071645 ps
CPU time 0.9 seconds
Started Jul 24 07:08:03 PM PDT 24
Finished Jul 24 07:08:04 PM PDT 24
Peak memory 200452 kb
Host smart-1ac86fc6-140b-43ad-95a4-6ce505f58d45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961130291 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.3961130291
Directory /workspace/5.clkmgr_extclk/latest

Test location /workspace/coverage/default/5.clkmgr_frequency.1310363137
Short name T529
Test name
Test status
Simulation time 1194875880 ps
CPU time 5.49 seconds
Started Jul 24 07:08:03 PM PDT 24
Finished Jul 24 07:08:09 PM PDT 24
Peak memory 200412 kb
Host smart-1704b992-e4c7-44e8-8fed-ffadac30b099
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310363137 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.1310363137
Directory /workspace/5.clkmgr_frequency/latest

Test location /workspace/coverage/default/5.clkmgr_frequency_timeout.2206306039
Short name T255
Test name
Test status
Simulation time 2307407432 ps
CPU time 12.52 seconds
Started Jul 24 07:08:01 PM PDT 24
Finished Jul 24 07:08:13 PM PDT 24
Peak memory 200740 kb
Host smart-6315d82a-a86c-42d6-9f43-b86ef74a5ca5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206306039 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_ti
meout.2206306039
Directory /workspace/5.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/5.clkmgr_idle_intersig_mubi.1408989354
Short name T343
Test name
Test status
Simulation time 19342147 ps
CPU time 0.83 seconds
Started Jul 24 07:08:04 PM PDT 24
Finished Jul 24 07:08:05 PM PDT 24
Peak memory 200520 kb
Host smart-fa608300-7488-4714-bf9f-299d66dca6e7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408989354 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_idle_intersig_mubi.1408989354
Directory /workspace/5.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.110499545
Short name T418
Test name
Test status
Simulation time 23593540 ps
CPU time 0.83 seconds
Started Jul 24 07:08:06 PM PDT 24
Finished Jul 24 07:08:07 PM PDT 24
Peak memory 200412 kb
Host smart-1e2ccd62-77e2-4e86-b994-c8cfba8ff396
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110499545 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.clkmgr_lc_clk_byp_req_intersig_mubi.110499545
Directory /workspace/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.3196371575
Short name T636
Test name
Test status
Simulation time 61098846 ps
CPU time 0.98 seconds
Started Jul 24 07:08:05 PM PDT 24
Finished Jul 24 07:08:06 PM PDT 24
Peak memory 200488 kb
Host smart-6e1b50fa-d41f-4dfa-a9d0-7b4892bdbeb9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196371575 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.clkmgr_lc_ctrl_intersig_mubi.3196371575
Directory /workspace/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_peri.680239518
Short name T309
Test name
Test status
Simulation time 55897750 ps
CPU time 0.91 seconds
Started Jul 24 07:08:02 PM PDT 24
Finished Jul 24 07:08:03 PM PDT 24
Peak memory 200404 kb
Host smart-47222b79-6c9d-4bd2-b558-159951762ec6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680239518 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.680239518
Directory /workspace/5.clkmgr_peri/latest

Test location /workspace/coverage/default/5.clkmgr_regwen.2793681844
Short name T702
Test name
Test status
Simulation time 672311823 ps
CPU time 4.26 seconds
Started Jul 24 07:08:06 PM PDT 24
Finished Jul 24 07:08:10 PM PDT 24
Peak memory 200616 kb
Host smart-a87910b4-c03f-408f-b76c-bbcbc49aaa73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793681844 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.2793681844
Directory /workspace/5.clkmgr_regwen/latest

Test location /workspace/coverage/default/5.clkmgr_smoke.692504042
Short name T388
Test name
Test status
Simulation time 51473422 ps
CPU time 0.93 seconds
Started Jul 24 07:08:03 PM PDT 24
Finished Jul 24 07:08:05 PM PDT 24
Peak memory 200396 kb
Host smart-3c856057-c38f-44eb-873d-872c3b454d72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692504042 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.692504042
Directory /workspace/5.clkmgr_smoke/latest

Test location /workspace/coverage/default/5.clkmgr_stress_all.1422673558
Short name T680
Test name
Test status
Simulation time 8664067528 ps
CPU time 37.86 seconds
Started Jul 24 07:08:02 PM PDT 24
Finished Jul 24 07:08:40 PM PDT 24
Peak memory 200812 kb
Host smart-61a0c157-9a27-4d1f-82a3-25e98d35bdcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422673558 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_stress_all.1422673558
Directory /workspace/5.clkmgr_stress_all/latest

Test location /workspace/coverage/default/5.clkmgr_trans.2236558153
Short name T717
Test name
Test status
Simulation time 67486499 ps
CPU time 1 seconds
Started Jul 24 07:08:05 PM PDT 24
Finished Jul 24 07:08:06 PM PDT 24
Peak memory 200508 kb
Host smart-d9cb0643-85a3-46e6-95e4-72c6a1ab54b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236558153 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.2236558153
Directory /workspace/5.clkmgr_trans/latest

Test location /workspace/coverage/default/6.clkmgr_alert_test.1573854947
Short name T826
Test name
Test status
Simulation time 39820677 ps
CPU time 0.85 seconds
Started Jul 24 07:08:09 PM PDT 24
Finished Jul 24 07:08:10 PM PDT 24
Peak memory 200548 kb
Host smart-824ad2f1-99c0-4155-99a9-2e9f9bb74b68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573854947 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkm
gr_alert_test.1573854947
Directory /workspace/6.clkmgr_alert_test/latest

Test location /workspace/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.1413678096
Short name T26
Test name
Test status
Simulation time 23740810 ps
CPU time 0.94 seconds
Started Jul 24 07:08:05 PM PDT 24
Finished Jul 24 07:08:06 PM PDT 24
Peak memory 200520 kb
Host smart-8f23b3ed-833b-4274-bd69-d1d49fb73f48
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413678096 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_clk_handshake_intersig_mubi.1413678096
Directory /workspace/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_clk_status.1949963716
Short name T155
Test name
Test status
Simulation time 14830792 ps
CPU time 0.74 seconds
Started Jul 24 07:08:03 PM PDT 24
Finished Jul 24 07:08:03 PM PDT 24
Peak memory 199700 kb
Host smart-8a109cba-70ad-49f2-b821-58820240ae64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949963716 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.1949963716
Directory /workspace/6.clkmgr_clk_status/latest

Test location /workspace/coverage/default/6.clkmgr_div_intersig_mubi.4016457963
Short name T335
Test name
Test status
Simulation time 32765258 ps
CPU time 0.82 seconds
Started Jul 24 07:08:00 PM PDT 24
Finished Jul 24 07:08:01 PM PDT 24
Peak memory 200468 kb
Host smart-7c8a0b10-ae17-4e14-84e0-c50938ddc19d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016457963 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_div_intersig_mubi.4016457963
Directory /workspace/6.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_extclk.4086575927
Short name T390
Test name
Test status
Simulation time 50820017 ps
CPU time 0.91 seconds
Started Jul 24 07:08:06 PM PDT 24
Finished Jul 24 07:08:07 PM PDT 24
Peak memory 200476 kb
Host smart-115c65a9-ca43-4bed-a7a3-acfd67937411
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086575927 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.4086575927
Directory /workspace/6.clkmgr_extclk/latest

Test location /workspace/coverage/default/6.clkmgr_frequency.4169963147
Short name T31
Test name
Test status
Simulation time 1884731832 ps
CPU time 10.53 seconds
Started Jul 24 07:08:01 PM PDT 24
Finished Jul 24 07:08:12 PM PDT 24
Peak memory 200732 kb
Host smart-a8141632-f701-41eb-ac36-c95a8dac1ffb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169963147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.4169963147
Directory /workspace/6.clkmgr_frequency/latest

Test location /workspace/coverage/default/6.clkmgr_frequency_timeout.1221502452
Short name T592
Test name
Test status
Simulation time 596761660 ps
CPU time 2.23 seconds
Started Jul 24 07:08:01 PM PDT 24
Finished Jul 24 07:08:03 PM PDT 24
Peak memory 200524 kb
Host smart-7573a40d-ad03-462a-8a33-1063fe45a326
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221502452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_ti
meout.1221502452
Directory /workspace/6.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/6.clkmgr_idle_intersig_mubi.1606474551
Short name T506
Test name
Test status
Simulation time 67700170 ps
CPU time 0.89 seconds
Started Jul 24 07:08:02 PM PDT 24
Finished Jul 24 07:08:03 PM PDT 24
Peak memory 200436 kb
Host smart-39f8c7db-c016-4de7-9568-70313619911e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606474551 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_idle_intersig_mubi.1606474551
Directory /workspace/6.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.3971880818
Short name T248
Test name
Test status
Simulation time 66462620 ps
CPU time 0.95 seconds
Started Jul 24 07:08:09 PM PDT 24
Finished Jul 24 07:08:10 PM PDT 24
Peak memory 200452 kb
Host smart-ab78db33-3aef-409d-8ded-825f04ae0be2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971880818 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.clkmgr_lc_clk_byp_req_intersig_mubi.3971880818
Directory /workspace/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.4184620496
Short name T172
Test name
Test status
Simulation time 19154209 ps
CPU time 0.78 seconds
Started Jul 24 07:08:05 PM PDT 24
Finished Jul 24 07:08:06 PM PDT 24
Peak memory 200484 kb
Host smart-a3f27623-2ea5-4b48-bbe8-ce65ab4cf677
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184620496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.clkmgr_lc_ctrl_intersig_mubi.4184620496
Directory /workspace/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_peri.2859120466
Short name T236
Test name
Test status
Simulation time 111393035 ps
CPU time 0.97 seconds
Started Jul 24 07:08:05 PM PDT 24
Finished Jul 24 07:08:06 PM PDT 24
Peak memory 200424 kb
Host smart-1cbc165b-9d7b-4f32-a561-8c751bd7e812
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859120466 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.2859120466
Directory /workspace/6.clkmgr_peri/latest

Test location /workspace/coverage/default/6.clkmgr_regwen.3923661510
Short name T4
Test name
Test status
Simulation time 298956936 ps
CPU time 1.7 seconds
Started Jul 24 07:08:10 PM PDT 24
Finished Jul 24 07:08:12 PM PDT 24
Peak memory 200448 kb
Host smart-2c0ab664-d2e7-44f4-978b-65c66001ef94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923661510 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.3923661510
Directory /workspace/6.clkmgr_regwen/latest

Test location /workspace/coverage/default/6.clkmgr_smoke.3874589917
Short name T202
Test name
Test status
Simulation time 21361034 ps
CPU time 0.84 seconds
Started Jul 24 07:08:01 PM PDT 24
Finished Jul 24 07:08:02 PM PDT 24
Peak memory 200420 kb
Host smart-0b577145-cde7-4aab-91ff-d484d8612369
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874589917 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.3874589917
Directory /workspace/6.clkmgr_smoke/latest

Test location /workspace/coverage/default/6.clkmgr_stress_all.2821094496
Short name T647
Test name
Test status
Simulation time 1200298385 ps
CPU time 10.11 seconds
Started Jul 24 07:08:08 PM PDT 24
Finished Jul 24 07:08:18 PM PDT 24
Peak memory 200436 kb
Host smart-0c55a3d2-6214-4779-a077-e9a5413ac47f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821094496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_stress_all.2821094496
Directory /workspace/6.clkmgr_stress_all/latest

Test location /workspace/coverage/default/6.clkmgr_stress_all_with_rand_reset.2262738568
Short name T652
Test name
Test status
Simulation time 108710780704 ps
CPU time 736.02 seconds
Started Jul 24 07:08:10 PM PDT 24
Finished Jul 24 07:20:26 PM PDT 24
Peak memory 213500 kb
Host smart-404b133b-f61a-4193-9533-fa0d66bfb11e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2262738568 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all_with_rand_reset.2262738568
Directory /workspace/6.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.clkmgr_trans.4258950080
Short name T678
Test name
Test status
Simulation time 185375071 ps
CPU time 1.26 seconds
Started Jul 24 07:08:02 PM PDT 24
Finished Jul 24 07:08:04 PM PDT 24
Peak memory 200380 kb
Host smart-6cdbbe3a-fe5c-41fa-9c31-0aae8470d4d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258950080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.4258950080
Directory /workspace/6.clkmgr_trans/latest

Test location /workspace/coverage/default/7.clkmgr_alert_test.889344629
Short name T222
Test name
Test status
Simulation time 32773705 ps
CPU time 0.85 seconds
Started Jul 24 07:08:22 PM PDT 24
Finished Jul 24 07:08:24 PM PDT 24
Peak memory 200540 kb
Host smart-bc62c346-9afb-4657-b155-924900fa3cb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889344629 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmg
r_alert_test.889344629
Directory /workspace/7.clkmgr_alert_test/latest

Test location /workspace/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.245750709
Short name T579
Test name
Test status
Simulation time 20095452 ps
CPU time 0.82 seconds
Started Jul 24 07:08:22 PM PDT 24
Finished Jul 24 07:08:23 PM PDT 24
Peak memory 200476 kb
Host smart-b6206879-eccc-46ec-a86f-c2de6b8ce34b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245750709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_clk_handshake_intersig_mubi.245750709
Directory /workspace/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_clk_status.25240138
Short name T734
Test name
Test status
Simulation time 20999772 ps
CPU time 0.73 seconds
Started Jul 24 07:08:13 PM PDT 24
Finished Jul 24 07:08:14 PM PDT 24
Peak memory 200412 kb
Host smart-a93f5a99-c330-4c26-84d9-ef2043872d13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25240138 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.25240138
Directory /workspace/7.clkmgr_clk_status/latest

Test location /workspace/coverage/default/7.clkmgr_div_intersig_mubi.150669968
Short name T279
Test name
Test status
Simulation time 106101179 ps
CPU time 1.11 seconds
Started Jul 24 07:08:09 PM PDT 24
Finished Jul 24 07:08:11 PM PDT 24
Peak memory 200376 kb
Host smart-5088f646-eaf2-4410-9e54-a5f46d9e09fb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150669968 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.clkmgr_div_intersig_mubi.150669968
Directory /workspace/7.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_extclk.322491297
Short name T755
Test name
Test status
Simulation time 22887022 ps
CPU time 0.86 seconds
Started Jul 24 07:08:13 PM PDT 24
Finished Jul 24 07:08:13 PM PDT 24
Peak memory 200464 kb
Host smart-d6be5cf0-6ef4-4f61-8ebd-f2de433c5b50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322491297 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.322491297
Directory /workspace/7.clkmgr_extclk/latest

Test location /workspace/coverage/default/7.clkmgr_frequency.170438560
Short name T524
Test name
Test status
Simulation time 794749494 ps
CPU time 3.58 seconds
Started Jul 24 07:08:09 PM PDT 24
Finished Jul 24 07:08:13 PM PDT 24
Peak memory 200468 kb
Host smart-884b2f84-bbc6-420f-a080-e79bdb7c594d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170438560 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.170438560
Directory /workspace/7.clkmgr_frequency/latest

Test location /workspace/coverage/default/7.clkmgr_frequency_timeout.3048953964
Short name T542
Test name
Test status
Simulation time 1236980933 ps
CPU time 5.12 seconds
Started Jul 24 07:08:06 PM PDT 24
Finished Jul 24 07:08:12 PM PDT 24
Peak memory 200516 kb
Host smart-b9fe9517-a69e-472e-9315-d5171cece62f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048953964 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_ti
meout.3048953964
Directory /workspace/7.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/7.clkmgr_idle_intersig_mubi.225382436
Short name T167
Test name
Test status
Simulation time 81915644 ps
CPU time 0.98 seconds
Started Jul 24 07:08:16 PM PDT 24
Finished Jul 24 07:08:17 PM PDT 24
Peak memory 200368 kb
Host smart-4c722cd8-1175-4215-9721-007b1cbbb956
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225382436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.clkmgr_idle_intersig_mubi.225382436
Directory /workspace/7.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.1725832444
Short name T520
Test name
Test status
Simulation time 31168558 ps
CPU time 0.84 seconds
Started Jul 24 07:08:07 PM PDT 24
Finished Jul 24 07:08:08 PM PDT 24
Peak memory 200476 kb
Host smart-bbd38878-812a-42c5-8618-9e767f82150b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725832444 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_clk_byp_req_intersig_mubi.1725832444
Directory /workspace/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.3162805744
Short name T701
Test name
Test status
Simulation time 23759639 ps
CPU time 0.86 seconds
Started Jul 24 07:08:10 PM PDT 24
Finished Jul 24 07:08:11 PM PDT 24
Peak memory 200464 kb
Host smart-4ec56814-3280-4c23-add5-88d9ceee54f2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162805744 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_ctrl_intersig_mubi.3162805744
Directory /workspace/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_peri.1869297470
Short name T185
Test name
Test status
Simulation time 18310628 ps
CPU time 0.77 seconds
Started Jul 24 07:08:08 PM PDT 24
Finished Jul 24 07:08:09 PM PDT 24
Peak memory 200488 kb
Host smart-57b847c9-6bed-4704-a8f5-dac32376e1b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869297470 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.1869297470
Directory /workspace/7.clkmgr_peri/latest

Test location /workspace/coverage/default/7.clkmgr_regwen.2167361462
Short name T98
Test name
Test status
Simulation time 913508120 ps
CPU time 4.94 seconds
Started Jul 24 07:08:09 PM PDT 24
Finished Jul 24 07:08:15 PM PDT 24
Peak memory 200624 kb
Host smart-06efd88c-7d50-4a6b-a8b3-c98ff64e8e64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167361462 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.2167361462
Directory /workspace/7.clkmgr_regwen/latest

Test location /workspace/coverage/default/7.clkmgr_smoke.548634210
Short name T823
Test name
Test status
Simulation time 76075329 ps
CPU time 1.04 seconds
Started Jul 24 07:08:14 PM PDT 24
Finished Jul 24 07:08:15 PM PDT 24
Peak memory 200416 kb
Host smart-293857f3-363a-4613-b8db-c43d70278461
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548634210 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.548634210
Directory /workspace/7.clkmgr_smoke/latest

Test location /workspace/coverage/default/7.clkmgr_stress_all.2394438891
Short name T329
Test name
Test status
Simulation time 4167108558 ps
CPU time 31.12 seconds
Started Jul 24 07:08:25 PM PDT 24
Finished Jul 24 07:08:56 PM PDT 24
Peak memory 200748 kb
Host smart-8b2d009b-dd0c-4e83-86bd-4ee5bffa9b12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394438891 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_stress_all.2394438891
Directory /workspace/7.clkmgr_stress_all/latest

Test location /workspace/coverage/default/7.clkmgr_trans.814725757
Short name T415
Test name
Test status
Simulation time 64481191 ps
CPU time 0.94 seconds
Started Jul 24 07:08:11 PM PDT 24
Finished Jul 24 07:08:12 PM PDT 24
Peak memory 200520 kb
Host smart-5f5ed570-0056-45cd-9ca7-e3bc62ed4022
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814725757 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.814725757
Directory /workspace/7.clkmgr_trans/latest

Test location /workspace/coverage/default/8.clkmgr_alert_test.167154252
Short name T687
Test name
Test status
Simulation time 17606334 ps
CPU time 0.83 seconds
Started Jul 24 07:08:23 PM PDT 24
Finished Jul 24 07:08:24 PM PDT 24
Peak memory 200536 kb
Host smart-daf86e08-55ac-45cf-8d2d-d962c54e894a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167154252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmg
r_alert_test.167154252
Directory /workspace/8.clkmgr_alert_test/latest

Test location /workspace/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.3522025890
Short name T91
Test name
Test status
Simulation time 214609179 ps
CPU time 1.45 seconds
Started Jul 24 07:08:10 PM PDT 24
Finished Jul 24 07:08:11 PM PDT 24
Peak memory 200484 kb
Host smart-4307f2cc-90ca-4d45-9549-dbe50d1c5f07
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522025890 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_clk_handshake_intersig_mubi.3522025890
Directory /workspace/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_clk_status.1514356878
Short name T662
Test name
Test status
Simulation time 29420938 ps
CPU time 0.73 seconds
Started Jul 24 07:08:10 PM PDT 24
Finished Jul 24 07:08:11 PM PDT 24
Peak memory 199652 kb
Host smart-addb4d6f-d6a5-40eb-92a8-3c9128a6dda2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514356878 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.1514356878
Directory /workspace/8.clkmgr_clk_status/latest

Test location /workspace/coverage/default/8.clkmgr_div_intersig_mubi.2894308089
Short name T710
Test name
Test status
Simulation time 12927062 ps
CPU time 0.75 seconds
Started Jul 24 07:08:14 PM PDT 24
Finished Jul 24 07:08:15 PM PDT 24
Peak memory 200472 kb
Host smart-0c5c46b1-5bea-4602-b588-b9f20bae5b6e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894308089 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_div_intersig_mubi.2894308089
Directory /workspace/8.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_extclk.3862514881
Short name T812
Test name
Test status
Simulation time 13224219 ps
CPU time 0.75 seconds
Started Jul 24 07:08:19 PM PDT 24
Finished Jul 24 07:08:20 PM PDT 24
Peak memory 200492 kb
Host smart-51ca6de9-f756-4b32-bf7c-6e53052f6139
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862514881 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.3862514881
Directory /workspace/8.clkmgr_extclk/latest

Test location /workspace/coverage/default/8.clkmgr_frequency.2519265003
Short name T454
Test name
Test status
Simulation time 201337488 ps
CPU time 2.04 seconds
Started Jul 24 07:08:06 PM PDT 24
Finished Jul 24 07:08:08 PM PDT 24
Peak memory 200440 kb
Host smart-3f7b608a-8b03-4bed-ae64-4050c92643f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519265003 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.2519265003
Directory /workspace/8.clkmgr_frequency/latest

Test location /workspace/coverage/default/8.clkmgr_frequency_timeout.1984923115
Short name T670
Test name
Test status
Simulation time 1467255531 ps
CPU time 7.13 seconds
Started Jul 24 07:08:13 PM PDT 24
Finished Jul 24 07:08:20 PM PDT 24
Peak memory 200508 kb
Host smart-3f4df316-ae99-4aea-a390-69409c55ac35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984923115 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_ti
meout.1984923115
Directory /workspace/8.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/8.clkmgr_idle_intersig_mubi.204799822
Short name T358
Test name
Test status
Simulation time 98624630 ps
CPU time 1.23 seconds
Started Jul 24 07:08:22 PM PDT 24
Finished Jul 24 07:08:23 PM PDT 24
Peak memory 200452 kb
Host smart-6422c648-eec8-4009-a126-ca41e5a45dfc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204799822 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.clkmgr_idle_intersig_mubi.204799822
Directory /workspace/8.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.3172943730
Short name T54
Test name
Test status
Simulation time 14398285 ps
CPU time 0.74 seconds
Started Jul 24 07:08:10 PM PDT 24
Finished Jul 24 07:08:11 PM PDT 24
Peak memory 200456 kb
Host smart-813a0c2a-e174-49c0-b581-bfcb0f49d14e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172943730 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.clkmgr_lc_clk_byp_req_intersig_mubi.3172943730
Directory /workspace/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.3846559683
Short name T197
Test name
Test status
Simulation time 78798127 ps
CPU time 1.06 seconds
Started Jul 24 07:08:10 PM PDT 24
Finished Jul 24 07:08:11 PM PDT 24
Peak memory 200456 kb
Host smart-4e9554d3-2d79-4051-989b-d3c999782483
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846559683 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.clkmgr_lc_ctrl_intersig_mubi.3846559683
Directory /workspace/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_peri.791252073
Short name T212
Test name
Test status
Simulation time 19337951 ps
CPU time 0.79 seconds
Started Jul 24 07:08:10 PM PDT 24
Finished Jul 24 07:08:11 PM PDT 24
Peak memory 200360 kb
Host smart-4affab29-59c1-466c-ac6a-043afa844be5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791252073 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.791252073
Directory /workspace/8.clkmgr_peri/latest

Test location /workspace/coverage/default/8.clkmgr_smoke.541254680
Short name T30
Test name
Test status
Simulation time 21612278 ps
CPU time 0.87 seconds
Started Jul 24 07:08:13 PM PDT 24
Finished Jul 24 07:08:14 PM PDT 24
Peak memory 200468 kb
Host smart-0e19c714-a04f-49f6-9429-c3692ad40a30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541254680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.541254680
Directory /workspace/8.clkmgr_smoke/latest

Test location /workspace/coverage/default/8.clkmgr_stress_all.4241204492
Short name T195
Test name
Test status
Simulation time 12877223644 ps
CPU time 95.16 seconds
Started Jul 24 07:08:27 PM PDT 24
Finished Jul 24 07:10:02 PM PDT 24
Peak memory 200804 kb
Host smart-608b4d6d-4a93-458b-8162-c54a08a22f53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241204492 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_stress_all.4241204492
Directory /workspace/8.clkmgr_stress_all/latest

Test location /workspace/coverage/default/8.clkmgr_trans.2508455028
Short name T518
Test name
Test status
Simulation time 185836599 ps
CPU time 1.42 seconds
Started Jul 24 07:08:19 PM PDT 24
Finished Jul 24 07:08:21 PM PDT 24
Peak memory 200460 kb
Host smart-163638f9-12da-4d98-b714-bc6718b31170
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508455028 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.2508455028
Directory /workspace/8.clkmgr_trans/latest

Test location /workspace/coverage/default/9.clkmgr_alert_test.267664641
Short name T25
Test name
Test status
Simulation time 43823718 ps
CPU time 0.85 seconds
Started Jul 24 07:08:28 PM PDT 24
Finished Jul 24 07:08:29 PM PDT 24
Peak memory 200552 kb
Host smart-28dbfc66-8250-4d57-a638-f88aeaa86c29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267664641 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmg
r_alert_test.267664641
Directory /workspace/9.clkmgr_alert_test/latest

Test location /workspace/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.1664000904
Short name T181
Test name
Test status
Simulation time 16626145 ps
CPU time 0.75 seconds
Started Jul 24 07:08:25 PM PDT 24
Finished Jul 24 07:08:26 PM PDT 24
Peak memory 200500 kb
Host smart-4e722b68-cc5e-4883-9a00-fdc7876b07b4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664000904 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_clk_handshake_intersig_mubi.1664000904
Directory /workspace/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_clk_status.4033988222
Short name T519
Test name
Test status
Simulation time 19765365 ps
CPU time 0.7 seconds
Started Jul 24 07:08:17 PM PDT 24
Finished Jul 24 07:08:18 PM PDT 24
Peak memory 200296 kb
Host smart-2fd4b4e3-2f40-46db-ae5f-cd38038af8cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033988222 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.4033988222
Directory /workspace/9.clkmgr_clk_status/latest

Test location /workspace/coverage/default/9.clkmgr_div_intersig_mubi.3183987578
Short name T715
Test name
Test status
Simulation time 29374398 ps
CPU time 0.93 seconds
Started Jul 24 07:08:31 PM PDT 24
Finished Jul 24 07:08:32 PM PDT 24
Peak memory 200476 kb
Host smart-4ed4f2db-2491-4c26-b4ab-3759f1c4e0d3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183987578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_div_intersig_mubi.3183987578
Directory /workspace/9.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_extclk.1357318923
Short name T635
Test name
Test status
Simulation time 15559737 ps
CPU time 0.78 seconds
Started Jul 24 07:08:19 PM PDT 24
Finished Jul 24 07:08:20 PM PDT 24
Peak memory 200448 kb
Host smart-431de275-e6fd-4018-be22-5129706b9d2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357318923 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.1357318923
Directory /workspace/9.clkmgr_extclk/latest

Test location /workspace/coverage/default/9.clkmgr_frequency.1226406084
Short name T527
Test name
Test status
Simulation time 2006525354 ps
CPU time 11.71 seconds
Started Jul 24 07:08:19 PM PDT 24
Finished Jul 24 07:08:31 PM PDT 24
Peak memory 200672 kb
Host smart-42d81bb8-21b0-4f2e-8627-742c7ac879ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226406084 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.1226406084
Directory /workspace/9.clkmgr_frequency/latest

Test location /workspace/coverage/default/9.clkmgr_frequency_timeout.234565684
Short name T330
Test name
Test status
Simulation time 619936754 ps
CPU time 4.76 seconds
Started Jul 24 07:08:12 PM PDT 24
Finished Jul 24 07:08:17 PM PDT 24
Peak memory 200536 kb
Host smart-b31eb9b1-99f5-42a4-a807-00a1f0e2d050
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234565684 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_tim
eout.234565684
Directory /workspace/9.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/9.clkmgr_idle_intersig_mubi.134824002
Short name T170
Test name
Test status
Simulation time 50029455 ps
CPU time 0.86 seconds
Started Jul 24 07:08:28 PM PDT 24
Finished Jul 24 07:08:29 PM PDT 24
Peak memory 200480 kb
Host smart-10e766ca-8dcf-4d19-a531-2a3c922c40d3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134824002 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.clkmgr_idle_intersig_mubi.134824002
Directory /workspace/9.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.1241882830
Short name T699
Test name
Test status
Simulation time 139937526 ps
CPU time 1.28 seconds
Started Jul 24 07:08:31 PM PDT 24
Finished Jul 24 07:08:33 PM PDT 24
Peak memory 200492 kb
Host smart-725748b6-c5f8-4bf7-89bf-eeec7c2ff708
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241882830 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.clkmgr_lc_clk_byp_req_intersig_mubi.1241882830
Directory /workspace/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.1918424608
Short name T667
Test name
Test status
Simulation time 51232368 ps
CPU time 0.95 seconds
Started Jul 24 07:08:24 PM PDT 24
Finished Jul 24 07:08:25 PM PDT 24
Peak memory 200488 kb
Host smart-2c848305-00b5-40fa-a5ad-2853a9e5cc3b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918424608 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.clkmgr_lc_ctrl_intersig_mubi.1918424608
Directory /workspace/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_peri.819628625
Short name T764
Test name
Test status
Simulation time 48388565 ps
CPU time 0.9 seconds
Started Jul 24 07:08:24 PM PDT 24
Finished Jul 24 07:08:25 PM PDT 24
Peak memory 200460 kb
Host smart-c3b99454-4869-4d4f-8d61-a4d559604fc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819628625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.819628625
Directory /workspace/9.clkmgr_peri/latest

Test location /workspace/coverage/default/9.clkmgr_regwen.3970737720
Short name T151
Test name
Test status
Simulation time 882690452 ps
CPU time 5.35 seconds
Started Jul 24 07:08:24 PM PDT 24
Finished Jul 24 07:08:30 PM PDT 24
Peak memory 200564 kb
Host smart-b974c73e-e56f-440c-b0f9-38941cf71fbb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970737720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.3970737720
Directory /workspace/9.clkmgr_regwen/latest

Test location /workspace/coverage/default/9.clkmgr_smoke.540371312
Short name T675
Test name
Test status
Simulation time 76068478 ps
CPU time 1.02 seconds
Started Jul 24 07:08:16 PM PDT 24
Finished Jul 24 07:08:18 PM PDT 24
Peak memory 200500 kb
Host smart-f0be653d-92f8-4898-86d4-3afcc2f66c5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540371312 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.540371312
Directory /workspace/9.clkmgr_smoke/latest

Test location /workspace/coverage/default/9.clkmgr_stress_all.2046558511
Short name T189
Test name
Test status
Simulation time 2851382029 ps
CPU time 11.52 seconds
Started Jul 24 07:08:22 PM PDT 24
Finished Jul 24 07:08:34 PM PDT 24
Peak memory 200820 kb
Host smart-ed3bfd9e-94ed-40eb-8d8f-134a1076d2ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046558511 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_stress_all.2046558511
Directory /workspace/9.clkmgr_stress_all/latest

Test location /workspace/coverage/default/9.clkmgr_trans.1470317743
Short name T669
Test name
Test status
Simulation time 27501642 ps
CPU time 0.92 seconds
Started Jul 24 07:08:24 PM PDT 24
Finished Jul 24 07:08:25 PM PDT 24
Peak memory 200460 kb
Host smart-2a2be5b2-36e2-4d1a-a3fc-b2ccd6689bae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470317743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.1470317743
Directory /workspace/9.clkmgr_trans/latest
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