Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	291289	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1383038

1

T7

17

T8

9

T9

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	430374	1			T7	18		T8	7		T9	6
values[0x0]	575020	1			T7	14		T8	5		T9	7
values[0x1]	668933	1			T7	11		T8	10		T9	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	173135	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1501192

1

T7

20

T8

11

T9

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5896	1			T1	321		T3	1		T12	4
valid_sources[0x01]	6913	1			T1	297		T18	1		T179	2
valid_sources[0x02]	6257	1			T6	1		T39	2		T44	1
valid_sources[0x03]	6496	1			T6	1		T44	1		T159	2
valid_sources[0x04]	6517	1			T1	340		T3	3		T116	1
valid_sources[0x05]	6242	1			T7	2		T26	1		T44	1
valid_sources[0x06]	6607	1			T1	298		T3	1		T12	6
valid_sources[0x07]	7055	1			T6	4		T44	2		T1	281
valid_sources[0x08]	9007	1			T6	2		T27	2		T44	1
valid_sources[0x09]	7812	1			T1	329		T183	1		T12	3
valid_sources[0x0a]	6266	1			T6	1		T39	1		T44	2
valid_sources[0x0b]	6387	1			T6	3		T37	1		T1	319
valid_sources[0x0c]	6256	1			T1	287		T24	6		T116	1
valid_sources[0x0d]	6176	1			T37	1		T44	3		T1	305
valid_sources[0x0e]	6213	1			T28	11		T1	311		T18	1
valid_sources[0x0f]	7473	1			T6	8		T44	1		T1	282
valid_sources[0x10]	6647	1			T1	303		T116	2		T12	1
valid_sources[0x11]	6172	1			T27	3		T37	1		T44	2
valid_sources[0x12]	6979	1			T6	1		T1	310		T19	2
valid_sources[0x13]	6783	1			T6	1		T1	304		T3	3
valid_sources[0x14]	6290	1			T25	1		T44	5		T1	276
valid_sources[0x15]	6252	1			T1	312		T22	1		T3	2
valid_sources[0x16]	5942	1			T44	3		T1	259		T19	3
valid_sources[0x17]	6635	1			T6	2		T27	1		T114	4
valid_sources[0x18]	6047	1			T28	7		T159	1		T1	320
valid_sources[0x19]	5572	1			T6	2		T1	289		T12	3
valid_sources[0x1a]	6286	1			T26	1		T6	3		T27	4
valid_sources[0x1b]	6269	1			T6	1		T1	312		T24	17
valid_sources[0x1c]	6152	1			T44	2		T1	294		T19	8
valid_sources[0x1d]	7765	1			T7	1		T1	309		T12	6
valid_sources[0x1e]	6866	1			T44	2		T1	324		T19	1
valid_sources[0x1f]	7327	1			T6	4		T159	1		T1	321
valid_sources[0x20]	5983	1			T7	2		T1	302		T3	2
valid_sources[0x21]	7099	1			T1	287		T18	1		T19	16
valid_sources[0x22]	6197	1			T6	2		T1	284		T24	5
valid_sources[0x23]	6378	1			T6	4		T115	140		T1	291
valid_sources[0x24]	6463	1			T6	2		T37	1		T44	1
valid_sources[0x25]	5815	1			T6	3		T1	303		T3	1
valid_sources[0x26]	7010	1			T6	2		T1	332		T3	2
valid_sources[0x27]	6729	1			T25	1		T1	297		T24	1
valid_sources[0x28]	6314	1			T6	1		T44	1		T1	314
valid_sources[0x29]	6004	1			T37	1		T1	326		T21	2
valid_sources[0x2a]	6780	1			T27	3		T1	304		T24	1
valid_sources[0x2b]	6243	1			T6	3		T1	292		T21	1
valid_sources[0x2c]	7124	1			T6	9		T114	1		T44	1
valid_sources[0x2d]	6279	1			T6	1		T1	293		T3	1
valid_sources[0x2e]	6850	1			T7	4		T6	5		T4	846
valid_sources[0x2f]	6077	1			T44	1		T1	330		T19	2
valid_sources[0x30]	6332	1			T1	338		T12	3		T84	3
valid_sources[0x31]	7040	1			T6	1		T27	8		T1	302
valid_sources[0x32]	5963	1			T1	279		T18	1		T183	1
valid_sources[0x33]	6222	1			T9	19		T25	1		T26	1
valid_sources[0x34]	6450	1			T6	6		T1	337		T20	25
valid_sources[0x35]	6053	1			T25	1		T1	335		T3	2
valid_sources[0x36]	6583	1			T7	4		T25	1		T6	2
valid_sources[0x37]	6466	1			T6	1		T44	3		T1	310
valid_sources[0x38]	6480	1			T1	323		T116	1		T12	9
valid_sources[0x39]	6130	1			T6	1		T1	301		T3	1
valid_sources[0x3a]	6125	1			T37	1		T1	307		T24	8
valid_sources[0x3b]	6835	1			T7	2		T6	1		T1	286
valid_sources[0x3c]	6243	1			T6	1		T1	289		T21	17
valid_sources[0x3d]	6565	1			T39	1		T1	300		T21	1
valid_sources[0x3e]	7389	1			T44	1		T1	308		T150	2
valid_sources[0x3f]	5913	1			T1	284		T18	1		T24	8
valid_sources[0x40]	6391	1			T6	5		T44	3		T1	320
valid_sources[0x41]	6907	1			T7	1		T1	298		T19	1
valid_sources[0x42]	6077	1			T1	317		T3	1		T117	2
valid_sources[0x43]	6664	1			T25	1		T1	332		T24	4
valid_sources[0x44]	5933	1			T6	1		T114	1		T1	300
valid_sources[0x45]	6110	1			T159	1		T1	330		T12	6
valid_sources[0x46]	6872	1			T27	2		T44	1		T1	325
valid_sources[0x47]	6750	1			T7	2		T25	1		T6	3
valid_sources[0x48]	6258	1			T6	1		T1	297		T180	2
valid_sources[0x49]	7385	1			T1	298		T116	1		T12	3
valid_sources[0x4a]	5865	1			T37	1		T1	309		T24	2
valid_sources[0x4b]	6111	1			T1	328		T24	4		T116	1
valid_sources[0x4c]	6891	1			T37	1		T1	315		T24	2
valid_sources[0x4d]	5960	1			T6	3		T37	1		T1	302
valid_sources[0x4e]	6773	1			T159	1		T1	320		T3	1
valid_sources[0x4f]	6258	1			T26	1		T44	1		T1	329
valid_sources[0x50]	6369	1			T1	326		T18	1		T3	3
valid_sources[0x51]	6262	1			T39	4		T1	292		T19	5
valid_sources[0x52]	6429	1			T44	1		T1	316		T18	2
valid_sources[0x53]	8195	1			T1	343		T12	2		T80	1
valid_sources[0x54]	6507	1			T25	1		T44	1		T1	305
valid_sources[0x55]	6282	1			T7	1		T6	9		T114	1
valid_sources[0x56]	6853	1			T44	1		T1	290		T3	3
valid_sources[0x57]	6765	1			T6	6		T39	1		T1	313
valid_sources[0x58]	6776	1			T6	5		T37	1		T159	1
valid_sources[0x59]	6157	1			T25	2		T1	319		T3	2
valid_sources[0x5a]	7720	1			T6	3		T44	2		T1	288
valid_sources[0x5b]	6588	1			T6	2		T114	1		T1	283
valid_sources[0x5c]	7445	1			T1	285		T12	6		T84	4
valid_sources[0x5d]	7067	1			T6	8		T44	1		T1	280
valid_sources[0x5e]	6409	1			T1	338		T116	1		T12	5
valid_sources[0x5f]	6064	1			T6	1		T1	283		T3	1
valid_sources[0x60]	5754	1			T25	1		T6	4		T1	289
valid_sources[0x61]	6046	1			T44	1		T1	304		T21	3
valid_sources[0x62]	6027	1			T1	308		T19	3		T24	6
valid_sources[0x63]	6747	1			T1	307		T3	2		T24	3
valid_sources[0x64]	6612	1			T25	2		T6	4		T1	294
valid_sources[0x65]	7670	1			T6	6		T39	1		T1	303
valid_sources[0x66]	5789	1			T1	286		T24	2		T12	2
valid_sources[0x67]	5987	1			T114	6		T1	301		T3	1
valid_sources[0x68]	6360	1			T44	2		T1	345		T24	11
valid_sources[0x69]	6666	1			T6	5		T37	1		T1	330
valid_sources[0x6a]	6370	1			T1	305		T18	1		T22	1
valid_sources[0x6b]	7103	1			T6	1		T1	332		T116	4
valid_sources[0x6c]	6054	1			T1	314		T22	1		T24	2
valid_sources[0x6d]	6198	1			T6	3		T1	353		T24	6
valid_sources[0x6e]	7552	1			T44	2		T1	336		T24	1
valid_sources[0x6f]	6455	1			T6	2		T1	265		T24	3
valid_sources[0x70]	6107	1			T6	3		T1	324		T22	1
valid_sources[0x71]	8239	1			T6	1		T28	8		T114	1
valid_sources[0x72]	6704	1			T7	2		T44	2		T1	307
valid_sources[0x73]	5960	1			T25	1		T1	290		T3	3
valid_sources[0x74]	5930	1			T6	1		T1	302		T3	1
valid_sources[0x75]	6489	1			T6	9		T44	2		T1	309
valid_sources[0x76]	6261	1			T6	2		T1	308		T3	1
valid_sources[0x77]	6359	1			T25	1		T39	1		T1	294
valid_sources[0x78]	6091	1			T1	290		T18	1		T22	1
valid_sources[0x79]	6823	1			T1	315		T24	4		T116	2
valid_sources[0x7a]	6029	1			T1	280		T24	2		T180	1
valid_sources[0x7b]	6165	1			T1	300		T3	1		T180	2
valid_sources[0x7c]	6285	1			T7	2		T39	1		T1	293
valid_sources[0x7d]	6101	1			T114	3		T1	305		T19	1
valid_sources[0x7e]	6449	1			T25	1		T28	1		T1	319
valid_sources[0x7f]	6006	1			T6	2		T114	1		T1	291
valid_sources[0x80]	6003	1			T1	278		T3	2		T24	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

356436

1

T7

13

T8

5

T9

4

values[0x0]

all_enables

biggest_size

526140

1

T7

3

T8

3

T9

2

values[0x1]

all_enables

biggest_size

500462

1

T7

1

T8

1

T5

19