Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T29,T4
0	1	Covered	T6,T37,T159
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T29,T4
1	0	Covered	T45,T46,T47
1	1	Covered	T7,T8,T9

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	461799559	7710	0	0
GateOpen_A	461799559	13294	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461799559	7710	0	0
T1	0	52	0	0
T2	0	99	0	0
T4	276071	0	0	0
T6	257025	5	0	0
T12	0	68	0	0
T27	10728	0	0	0
T28	3583	0	0	0
T29	7629	10	0	0
T32	7363	0	0	0
T37	9604	30	0	0
T38	6008	0	0	0
T39	5967	0	0	0
T45	0	20	0	0
T48	7218	0	0	0
T49	0	4	0	0
T159	0	40	0	0
T184	0	41	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461799559	13294	0	0
T4	276071	72	0	0
T5	120366	0	0	0
T6	257025	9	0	0
T25	10031	4	0	0
T26	5737	4	0	0
T27	10728	4	0	0
T28	3583	0	0	0
T29	7629	14	0	0
T32	7363	0	0	0
T37	9604	30	0	0
T44	0	4	0	0
T48	0	4	0	0
T114	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T29,T4
0	1	Covered	T6,T37,T159
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T29,T4
1	0	Covered	T45,T46,T47
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	50815973	1863	0	0
GateOpen_A	50815973	3258	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50815973	1863	0	0
T1	0	14	0	0
T2	0	28	0	0
T4	21545	0	0	0
T6	27610	2	0	0
T12	0	13	0	0
T27	1282	0	0	0
T28	385	0	0	0
T29	830	2	0	0
T32	873	0	0	0
T37	1050	8	0	0
T38	693	0	0	0
T39	659	0	0	0
T45	0	5	0	0
T48	798	0	0	0
T49	0	1	0	0
T159	0	11	0	0
T184	0	11	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50815973	3258	0	0
T4	21545	18	0	0
T5	13352	0	0	0
T6	27610	3	0	0
T25	1099	1	0	0
T26	659	1	0	0
T27	1282	1	0	0
T28	385	0	0	0
T29	830	3	0	0
T32	873	0	0	0
T37	1050	8	0	0
T44	0	1	0	0
T48	0	1	0	0
T114	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T29,T4
0	1	Covered	T6,T37,T159
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T29,T4
1	0	Covered	T45,T46,T47
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	101632288	1958	0	0
GateOpen_A	101632288	3353	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101632288	1958	0	0
T1	0	13	0	0
T2	0	23	0	0
T4	43092	0	0	0
T6	55222	1	0	0
T12	0	18	0	0
T27	2567	0	0	0
T28	770	0	0	0
T29	1660	3	0	0
T32	1743	0	0	0
T37	2099	7	0	0
T38	1387	0	0	0
T39	1318	0	0	0
T45	0	5	0	0
T48	1596	0	0	0
T49	0	1	0	0
T159	0	11	0	0
T184	0	10	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101632288	3353	0	0
T4	43092	18	0	0
T5	26703	0	0	0
T6	55222	2	0	0
T25	2198	1	0	0
T26	1318	1	0	0
T27	2567	1	0	0
T28	770	0	0	0
T29	1660	4	0	0
T32	1743	0	0	0
T37	2099	7	0	0
T44	0	1	0	0
T48	0	1	0	0
T114	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T29,T4
0	1	Covered	T6,T37,T159
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T29,T4
1	0	Covered	T45,T46,T47
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	204665379	1968	0	0
GateOpen_A	204665379	3365	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204665379	1968	0	0
T1	0	13	0	0
T2	0	23	0	0
T4	140954	0	0	0
T6	110368	1	0	0
T12	0	18	0	0
T27	4586	0	0	0
T28	1619	0	0	0
T29	3426	2	0	0
T32	3165	0	0	0
T37	4303	7	0	0
T38	2618	0	0	0
T39	2660	0	0	0
T45	0	5	0	0
T48	3216	0	0	0
T49	0	1	0	0
T159	0	9	0	0
T184	0	11	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204665379	3365	0	0
T4	140954	18	0	0
T5	53540	0	0	0
T6	110368	2	0	0
T25	4489	1	0	0
T26	2507	1	0	0
T27	4586	1	0	0
T28	1619	0	0	0
T29	3426	3	0	0
T32	3165	0	0	0
T37	4303	7	0	0
T44	0	1	0	0
T48	0	1	0	0
T114	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T29,T4
0	1	Covered	T6,T37,T159
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T29,T4
1	0	Covered	T45,T46,T47
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	104685919	1921	0	0
GateOpen_A	104685919	3318	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104685919	1921	0	0
T1	0	12	0	0
T2	0	25	0	0
T4	70480	0	0	0
T6	63825	1	0	0
T12	0	19	0	0
T27	2293	0	0	0
T28	809	0	0	0
T29	1713	3	0	0
T32	1582	0	0	0
T37	2152	8	0	0
T38	1310	0	0	0
T39	1330	0	0	0
T45	0	5	0	0
T48	1608	0	0	0
T49	0	1	0	0
T159	0	9	0	0
T184	0	9	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104685919	3318	0	0
T4	70480	18	0	0
T5	26771	0	0	0
T6	63825	2	0	0
T25	2245	1	0	0
T26	1253	1	0	0
T27	2293	1	0	0
T28	809	0	0	0
T29	1713	4	0	0
T32	1582	0	0	0
T37	2152	8	0	0
T44	0	1	0	0
T48	0	1	0	0
T114	0	1	0	0