Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	351462515	36764	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351462515	36764	0	0
T1	1539725	650	0	0
T2	3115595	571	0	0
T3	59515	112	0	0
T11	0	183	0	0
T12	0	385	0	0
T13	0	285	0	0
T14	0	218	0	0
T15	0	836	0	0
T16	0	86	0	0
T17	0	83	0	0
T18	10005	0	0	0
T19	151620	0	0	0
T20	6735	0	0	0
T21	11215	0	0	0
T22	9195	0	0	0
T23	14965	0	0	0
T24	467380	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	70292503	5460	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70292503	5460	0	0
T1	307945	125	0	0
T2	623119	73	0	0
T3	11903	20	0	0
T11	0	25	0	0
T12	0	50	0	0
T13	0	42	0	0
T14	0	33	0	0
T15	0	123	0	0
T16	0	11	0	0
T17	0	13	0	0
T18	2001	0	0	0
T19	30324	0	0	0
T20	1347	0	0	0
T21	2243	0	0	0
T22	1839	0	0	0
T23	2993	0	0	0
T24	93476	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	70292503	5432	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70292503	5432	0	0
T1	307945	125	0	0
T2	623119	71	0	0
T3	11903	20	0	0
T11	0	23	0	0
T12	0	49	0	0
T13	0	41	0	0
T14	0	27	0	0
T15	0	106	0	0
T16	0	11	0	0
T17	0	13	0	0
T18	2001	0	0	0
T19	30324	0	0	0
T20	1347	0	0	0
T21	2243	0	0	0
T22	1839	0	0	0
T23	2993	0	0	0
T24	93476	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	70292503	7456	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70292503	7456	0	0
T1	307945	125	0	0
T2	623119	116	0	0
T3	11903	22	0	0
T11	0	39	0	0
T12	0	78	0	0
T13	0	57	0	0
T14	0	43	0	0
T15	0	164	0	0
T16	0	17	0	0
T17	0	17	0	0
T18	2001	0	0	0
T19	30324	0	0	0
T20	1347	0	0	0
T21	2243	0	0	0
T22	1839	0	0	0
T23	2993	0	0	0
T24	93476	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	70292503	7341	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70292503	7341	0	0
T1	307945	125	0	0
T2	623119	118	0	0
T3	11903	22	0	0
T11	0	37	0	0
T12	0	80	0	0
T13	0	57	0	0
T14	0	44	0	0
T15	0	168	0	0
T16	0	18	0	0
T17	0	17	0	0
T18	2001	0	0	0
T19	30324	0	0	0
T20	1347	0	0	0
T21	2243	0	0	0
T22	1839	0	0	0
T23	2993	0	0	0
T24	93476	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	70292503	11075	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70292503	11075	0	0
T1	307945	150	0	0
T2	623119	193	0	0
T3	11903	28	0	0
T11	0	59	0	0
T12	0	128	0	0
T13	0	88	0	0
T14	0	71	0	0
T15	0	275	0	0
T16	0	29	0	0
T17	0	23	0	0
T18	2001	0	0	0
T19	30324	0	0	0
T20	1347	0	0	0
T21	2243	0	0	0
T22	1839	0	0	0
T23	2993	0	0	0
T24	93476	0	0	0