Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T4,T1,T2

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	70292503	68362453	0	0
AllClkBypReqTrue_A	70292503	79029	0	0
IoClkBypReqFalse_A	70292503	68311564	0	2328
IoClkBypReqTrue_A	70292503	126076	0	0
LcClkBypAckFalse_A	70292503	68366939	0	0
LcClkBypAckTrue_A	70292503	74543	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70292503	68362453	0	0
T5	61154	60957	0	0
T6	138967	138676	0	0
T7	1657	1414	0	0
T8	1605	1511	0	0
T9	1478	1272	0	0
T25	1121	1073	0	0
T26	1305	1096	0	0
T27	2341	2214	0	0
T28	1685	1572	0	0
T29	891	852	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70292503	79029	0	0
T1	0	1394	0	0
T5	61154	0	0	0
T6	138967	107	0	0
T7	1657	185	0	0
T8	1605	0	0	0
T9	1478	148	0	0
T18	0	162	0	0
T25	1121	0	0	0
T26	1305	102	0	0
T27	2341	29	0	0
T28	1685	0	0	0
T29	891	0	0	0
T32	0	62	0	0
T38	0	240	0	0
T114	0	281	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70292503	68311564	0	2328
T5	61154	60955	0	3
T6	138967	138611	0	3
T7	1657	1296	0	3
T8	1605	1401	0	3
T9	1478	1359	0	3
T25	1121	1071	0	3
T26	1305	1095	0	3
T27	2341	1719	0	3
T28	1685	1570	0	3
T29	891	850	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70292503	126076	0	0
T1	0	1879	0	0
T5	61154	0	0	0
T6	138967	170	0	0
T7	1657	301	0	0
T8	1605	108	0	0
T9	1478	59	0	0
T25	1121	0	0	0
T26	1305	101	0	0
T27	2341	522	0	0
T28	1685	0	0	0
T29	891	0	0	0
T32	0	41	0	0
T38	0	355	0	0
T114	0	437	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70292503	68366939	0	0
T5	61154	60957	0	0
T6	138967	138657	0	0
T7	1657	1415	0	0
T8	1605	1459	0	0
T9	1478	1368	0	0
T25	1121	1073	0	0
T26	1305	1132	0	0
T27	2341	1919	0	0
T28	1685	1572	0	0
T29	891	852	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70292503	74543	0	0
T1	0	1048	0	0
T5	61154	0	0	0
T6	138967	126	0	0
T7	1657	184	0	0
T8	1605	52	0	0
T9	1478	52	0	0
T25	1121	0	0	0
T26	1305	66	0	0
T27	2341	324	0	0
T28	1685	0	0	0
T29	891	0	0	0
T32	0	37	0	0
T38	0	157	0	0
T114	0	247	0	0