Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	872440664	8118	0	0
TransStop_A	872440664	4189	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872440664	8118	0	0
T1	0	199	0	0
T2	0	26	0	0
T4	587328	0	0	0
T5	199084	0	0	0
T6	459872	7	0	0
T23	0	26	0	0
T25	18704	11	0	0
T26	10448	0	0	0
T27	19108	0	0	0
T28	6744	0	0	0
T29	14276	0	0	0
T32	13192	0	0	0
T37	17932	0	0	0
T44	0	31	0	0
T49	0	4	0	0
T115	0	35	0	0
T116	0	28	0	0
T117	0	25	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872440664	4189	0	0
T1	0	109	0	0
T2	0	21	0	0
T4	587328	0	0	0
T5	199084	0	0	0
T6	459872	2	0	0
T23	0	7	0	0
T25	18704	4	0	0
T26	10448	0	0	0
T27	19108	0	0	0
T28	6744	0	0	0
T29	14276	0	0	0
T32	13192	0	0	0
T37	17932	0	0	0
T44	0	21	0	0
T49	0	4	0	0
T115	0	20	0	0
T116	0	18	0	0
T117	0	13	0	0
T118	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	218110166	2070	0	0
TransStop_A	218110166	1062	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218110166	2070	0	0
T1	0	59	0	0
T2	0	4	0	0
T4	146832	0	0	0
T5	49771	0	0	0
T6	114968	1	0	0
T23	0	8	0	0
T25	4676	4	0	0
T26	2612	0	0	0
T27	4777	0	0	0
T28	1686	0	0	0
T29	3569	0	0	0
T32	3298	0	0	0
T37	4483	0	0	0
T44	0	7	0	0
T49	0	1	0	0
T115	0	11	0	0
T116	0	8	0	0
T117	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218110166	1062	0	0
T1	0	32	0	0
T2	0	3	0	0
T4	146832	0	0	0
T5	49771	0	0	0
T6	114968	0	0	0
T23	0	2	0	0
T25	4676	1	0	0
T26	2612	0	0	0
T27	4777	0	0	0
T28	1686	0	0	0
T29	3569	0	0	0
T32	3298	0	0	0
T37	4483	0	0	0
T44	0	6	0	0
T49	0	1	0	0
T115	0	6	0	0
T116	0	5	0	0
T117	0	1	0	0
T118	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	218110166	2001	0	0
TransStop_A	218110166	1042	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218110166	2001	0	0
T1	0	43	0	0
T2	0	7	0	0
T4	146832	0	0	0
T5	49771	0	0	0
T6	114968	1	0	0
T23	0	6	0	0
T25	4676	3	0	0
T26	2612	0	0	0
T27	4777	0	0	0
T28	1686	0	0	0
T29	3569	0	0	0
T32	3298	0	0	0
T37	4483	0	0	0
T44	0	7	0	0
T49	0	1	0	0
T115	0	6	0	0
T116	0	6	0	0
T117	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218110166	1042	0	0
T1	0	26	0	0
T2	0	6	0	0
T4	146832	0	0	0
T5	49771	0	0	0
T6	114968	0	0	0
T23	0	2	0	0
T25	4676	1	0	0
T26	2612	0	0	0
T27	4777	0	0	0
T28	1686	0	0	0
T29	3569	0	0	0
T32	3298	0	0	0
T37	4483	0	0	0
T44	0	5	0	0
T49	0	1	0	0
T115	0	3	0	0
T116	0	4	0	0
T117	0	4	0	0
T118	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	218110166	2011	0	0
TransStop_A	218110166	1065	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218110166	2011	0	0
T1	0	50	0	0
T2	0	7	0	0
T4	146832	0	0	0
T5	49771	0	0	0
T6	114968	2	0	0
T23	0	7	0	0
T25	4676	2	0	0
T26	2612	0	0	0
T27	4777	0	0	0
T28	1686	0	0	0
T29	3569	0	0	0
T32	3298	0	0	0
T37	4483	0	0	0
T44	0	7	0	0
T49	0	1	0	0
T115	0	10	0	0
T116	0	5	0	0
T117	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218110166	1065	0	0
T1	0	29	0	0
T2	0	6	0	0
T4	146832	0	0	0
T5	49771	0	0	0
T6	114968	1	0	0
T23	0	2	0	0
T25	4676	1	0	0
T26	2612	0	0	0
T27	4777	0	0	0
T28	1686	0	0	0
T29	3569	0	0	0
T32	3298	0	0	0
T37	4483	0	0	0
T44	0	4	0	0
T49	0	1	0	0
T115	0	6	0	0
T116	0	4	0	0
T117	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	218110166	2036	0	0
TransStop_A	218110166	1020	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218110166	2036	0	0
T1	0	47	0	0
T2	0	8	0	0
T4	146832	0	0	0
T5	49771	0	0	0
T6	114968	3	0	0
T23	0	5	0	0
T25	4676	2	0	0
T26	2612	0	0	0
T27	4777	0	0	0
T28	1686	0	0	0
T29	3569	0	0	0
T32	3298	0	0	0
T37	4483	0	0	0
T44	0	10	0	0
T49	0	1	0	0
T115	0	8	0	0
T116	0	9	0	0
T117	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218110166	1020	0	0
T1	0	22	0	0
T2	0	6	0	0
T4	146832	0	0	0
T5	49771	0	0	0
T6	114968	1	0	0
T23	0	1	0	0
T25	4676	1	0	0
T26	2612	0	0	0
T27	4777	0	0	0
T28	1686	0	0	0
T29	3569	0	0	0
T32	3298	0	0	0
T37	4483	0	0	0
T44	0	6	0	0
T49	0	1	0	0
T115	0	5	0	0
T116	0	5	0	0
T117	0	4	0	0