Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	71211163	1936741	0	0
clk_enables_rd_A	71211163	13604	0	0
clk_hints_rd_A	71211163	11726	0	0
extclk_ctrl_rd_A	71211163	17597	0	0
extclk_ctrl_regwen_rd_A	71211163	11518	0	0
jitter_enable_rd_A	71211163	18877	0	0
jitter_regwen_rd_A	71211163	12220	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	1936741	0	0
T1	307945	104652	0	0
T2	623119	0	0	0
T3	11903	0	0	0
T15	0	58019	0	0
T18	2001	0	0	0
T19	30324	0	0	0
T20	1347	0	0	0
T21	2243	0	0	0
T22	1839	0	0	0
T23	2993	0	0	0
T24	93476	0	0	0
T31	0	76803	0	0
T41	0	130157	0	0
T74	0	101581	0	0
T75	0	62515	0	0
T76	0	117046	0	0
T77	0	149050	0	0
T78	0	67312	0	0
T79	0	42637	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	13604	0	0
T2	623119	5	0	0
T3	11903	0	0	0
T11	182180	0	0	0
T19	30324	0	0	0
T20	1347	0	0	0
T21	2243	0	0	0
T22	1839	0	0	0
T23	2993	0	0	0
T24	93476	0	0	0
T31	0	2920	0	0
T49	1532	0	0	0
T78	0	2673	0	0
T141	0	6	0	0
T142	0	4	0	0
T143	0	7	0	0
T144	0	7	0	0
T145	0	3	0	0
T146	0	4	0	0
T147	0	6	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	11726	0	0
T2	623119	8	0	0
T3	11903	0	0	0
T11	182180	0	0	0
T19	30324	0	0	0
T20	1347	0	0	0
T21	2243	0	0	0
T22	1839	0	0	0
T23	2993	0	0	0
T24	93476	0	0	0
T31	0	2590	0	0
T49	1532	0	0	0
T78	0	2248	0	0
T141	0	10	0	0
T142	0	9	0	0
T143	0	1	0	0
T144	0	13	0	0
T145	0	5	0	0
T148	0	1	0	0
T149	0	1	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	17597	0	0
T2	0	125	0	0
T4	0	159	0	0
T5	61154	0	0	0
T6	138967	0	0	0
T7	1657	19	0	0
T8	1605	0	0	0
T9	1478	9	0	0
T18	0	34	0	0
T25	1121	0	0	0
T26	1305	26	0	0
T27	2341	0	0	0
T28	1685	0	0	0
T29	891	0	0	0
T114	0	41	0	0
T150	0	37	0	0
T151	0	9	0	0
T152	0	20	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	11518	0	0
T1	307945	0	0	0
T4	36707	54	0	0
T31	0	2567	0	0
T37	1075	0	0	0
T38	2564	0	0	0
T39	1358	0	0	0
T44	3409	0	0	0
T48	770	0	0	0
T78	0	2323	0	0
T113	0	51	0	0
T114	2320	0	0	0
T115	3069	0	0	0
T153	0	51	0	0
T154	0	9	0	0
T155	0	75	0	0
T156	0	19	0	0
T157	0	32	0	0
T158	0	28	0	0
T159	1253	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	18877	0	0
T2	623119	305	0	0
T3	11903	0	0	0
T11	182180	0	0	0
T19	30324	0	0	0
T20	1347	0	0	0
T21	2243	0	0	0
T22	1839	0	0	0
T23	2993	0	0	0
T24	93476	0	0	0
T31	0	4227	0	0
T49	1532	0	0	0
T78	0	2437	0	0
T141	0	107	0	0
T142	0	138	0	0
T143	0	126	0	0
T144	0	305	0	0
T145	0	126	0	0
T148	0	134	0	0
T149	0	90	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	12220	0	0
T31	259341	3182	0	0
T35	307279	0	0	0
T78	0	2288	0	0
T97	0	20	0	0
T102	0	1	0	0
T103	0	3	0	0
T104	0	27	0	0
T153	75863	0	0	0
T160	0	1812	0	0
T161	0	1313	0	0
T162	0	1982	0	0
T163	0	8	0	0
T164	1366	0	0	0
T165	1247	0	0	0
T166	35524	0	0	0
T167	1338	0	0	0
T168	997	0	0	0
T169	1331	0	0	0
T170	1931	0	0	0