Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T24
1	0	Covered	T5,T6,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	712111630	784692	0	0
DstReqKnown_A	1375001176	1353986126	0	0
SrcAckBusyChk_A	712111630	153811	0	0
SrcBusyKnown_A	712111630	692505370	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	712111630	784692	0	0
T1	0	9425	0	0
T2	0	8642	0	0
T3	0	358	0	0
T4	367070	1877	0	0
T5	611540	777	0	0
T6	1389670	1974	0	0
T11	0	2700	0	0
T19	0	527	0	0
T24	0	3395	0	0
T26	13050	0	0	0
T27	23410	0	0	0
T28	16850	0	0	0
T29	8910	0	0	0
T32	15170	0	0	0
T33	0	891	0	0
T37	10750	0	0	0
T38	25640	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1375001176	1353986126	0	0
T5	340266	339216	0	0
T6	743978	742962	0	0
T7	45222	43888	0	0
T8	21548	20502	0	0
T9	23116	22392	0	0
T25	29410	28306	0	0
T26	16692	15454	0	0
T27	31008	29940	0	0
T28	10536	9948	0	0
T29	22390	21572	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	712111630	153811	0	0
T1	0	3625	0	0
T2	0	1040	0	0
T3	0	140	0	0
T4	367070	531	0	0
T5	611540	100	0	0
T6	1389670	220	0	0
T11	0	340	0	0
T19	0	60	0	0
T24	0	428	0	0
T26	13050	0	0	0
T27	23410	0	0	0
T28	16850	0	0	0
T29	8910	0	0	0
T32	15170	0	0	0
T33	0	340	0	0
T37	10750	0	0	0
T38	25640	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	712111630	692505370	0	0
T5	611540	609580	0	0
T6	1389670	1387840	0	0
T7	16570	16000	0	0
T8	16050	15120	0	0
T9	14780	14210	0	0
T25	11210	10740	0	0
T26	13050	11990	0	0
T27	23410	22440	0	0
T28	16850	15730	0	0
T29	8910	8530	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T5,T6,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	71211163	43139	0	0
DstReqKnown_A	206993064	203386452	0	0
SrcAckBusyChk_A	71211163	12541	0	0
SrcBusyKnown_A	71211163	69250537	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	43139	0	0
T1	0	903	0	0
T2	0	542	0	0
T3	0	34	0	0
T4	36707	95	0	0
T5	61154	49	0	0
T6	138967	120	0	0
T11	0	174	0	0
T19	0	38	0	0
T24	0	150	0	0
T26	1305	0	0	0
T27	2341	0	0	0
T28	1685	0	0	0
T29	891	0	0	0
T32	1517	0	0	0
T33	0	85	0	0
T37	1075	0	0	0
T38	2564	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206993064	203386452	0	0
T5	53539	53349	0	0
T6	110367	110191	0	0
T7	6632	6402	0	0
T8	3279	3090	0	0
T9	3460	3326	0	0
T25	4488	4299	0	0
T26	2506	2303	0	0
T27	4586	4396	0	0
T28	1619	1511	0	0
T29	3426	3277	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	12541	0	0
T1	0	360	0	0
T2	0	104	0	0
T3	0	14	0	0
T4	36707	36	0	0
T5	61154	10	0	0
T6	138967	22	0	0
T11	0	34	0	0
T19	0	6	0	0
T24	0	30	0	0
T26	1305	0	0	0
T27	2341	0	0	0
T28	1685	0	0	0
T29	891	0	0	0
T32	1517	0	0	0
T33	0	34	0	0
T37	1075	0	0	0
T38	2564	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	69250537	0	0
T5	61154	60958	0	0
T6	138967	138784	0	0
T7	1657	1600	0	0
T8	1605	1512	0	0
T9	1478	1421	0	0
T25	1121	1074	0	0
T26	1305	1199	0	0
T27	2341	2244	0	0
T28	1685	1573	0	0
T29	891	853	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T5,T6,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	71211163	61424	0	0
DstReqKnown_A	102748875	101862378	0	0
SrcAckBusyChk_A	71211163	12541	0	0
SrcBusyKnown_A	71211163	69250537	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	61424	0	0
T1	0	903	0	0
T2	0	865	0	0
T3	0	34	0	0
T4	36707	131	0	0
T5	61154	79	0	0
T6	138967	190	0	0
T11	0	275	0	0
T19	0	55	0	0
T24	0	240	0	0
T26	1305	0	0	0
T27	2341	0	0	0
T28	1685	0	0	0
T29	891	0	0	0
T32	1517	0	0	0
T33	0	85	0	0
T37	1075	0	0	0
T38	2564	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102748875	101862378	0	0
T5	26702	26674	0	0
T6	55222	55181	0	0
T7	3836	3781	0	0
T8	1626	1598	0	0
T9	1843	1829	0	0
T25	2198	2150	0	0
T26	1317	1248	0	0
T27	2567	2532	0	0
T28	770	756	0	0
T29	1659	1638	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	12541	0	0
T1	0	360	0	0
T2	0	104	0	0
T3	0	14	0	0
T4	36707	36	0	0
T5	61154	10	0	0
T6	138967	22	0	0
T11	0	34	0	0
T19	0	6	0	0
T24	0	30	0	0
T26	1305	0	0	0
T27	2341	0	0	0
T28	1685	0	0	0
T29	891	0	0	0
T32	1517	0	0	0
T33	0	34	0	0
T37	1075	0	0	0
T38	2564	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	69250537	0	0
T5	61154	60958	0	0
T6	138967	138784	0	0
T7	1657	1600	0	0
T8	1605	1512	0	0
T9	1478	1421	0	0
T25	1121	1074	0	0
T26	1305	1199	0	0
T27	2341	2244	0	0
T28	1685	1573	0	0
T29	891	853	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T5,T6,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	71211163	97157	0	0
DstReqKnown_A	51374076	50930942	0	0
SrcAckBusyChk_A	71211163	12541	0	0
SrcBusyKnown_A	71211163	69250537	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	97157	0	0
T1	0	1083	0	0
T2	0	1502	0	0
T3	0	48	0	0
T4	36707	190	0	0
T5	61154	143	0	0
T6	138967	346	0	0
T11	0	462	0	0
T19	0	89	0	0
T24	0	404	0	0
T26	1305	0	0	0
T27	2341	0	0	0
T28	1685	0	0	0
T29	891	0	0	0
T32	1517	0	0	0
T33	0	107	0	0
T37	1075	0	0	0
T38	2564	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51374076	50930942	0	0
T5	13351	13337	0	0
T6	27609	27588	0	0
T7	1918	1891	0	0
T8	813	799	0	0
T9	921	914	0	0
T25	1099	1075	0	0
T26	659	625	0	0
T27	1281	1264	0	0
T28	385	378	0	0
T29	830	820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	12541	0	0
T1	0	360	0	0
T2	0	104	0	0
T3	0	14	0	0
T4	36707	36	0	0
T5	61154	10	0	0
T6	138967	22	0	0
T11	0	34	0	0
T19	0	6	0	0
T24	0	30	0	0
T26	1305	0	0	0
T27	2341	0	0	0
T28	1685	0	0	0
T29	891	0	0	0
T32	1517	0	0	0
T33	0	34	0	0
T37	1075	0	0	0
T38	2564	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	69250537	0	0
T5	61154	60958	0	0
T6	138967	138784	0	0
T7	1657	1600	0	0
T8	1605	1512	0	0
T9	1478	1421	0	0
T25	1121	1074	0	0
T26	1305	1199	0	0
T27	2341	2244	0	0
T28	1685	1573	0	0
T29	891	853	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T5,T6,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	71211163	43043	0	0
DstReqKnown_A	220534961	216773775	0	0
SrcAckBusyChk_A	71211163	12541	0	0
SrcBusyKnown_A	71211163	69250537	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	43043	0	0
T1	0	903	0	0
T2	0	523	0	0
T3	0	34	0	0
T4	36707	91	0	0
T5	61154	47	0	0
T6	138967	138	0	0
T11	0	165	0	0
T19	0	32	0	0
T24	0	142	0	0
T26	1305	0	0	0
T27	2341	0	0	0
T28	1685	0	0	0
T29	891	0	0	0
T32	1517	0	0	0
T33	0	85	0	0
T37	1075	0	0	0
T38	2564	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220534961	216773775	0	0
T5	49771	49573	0	0
T6	114967	114784	0	0
T7	6909	6669	0	0
T8	3416	3219	0	0
T9	3604	3464	0	0
T25	4676	4479	0	0
T26	2611	2399	0	0
T27	4777	4580	0	0
T28	1685	1573	0	0
T29	3568	3413	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	12541	0	0
T1	0	360	0	0
T2	0	104	0	0
T3	0	14	0	0
T4	36707	36	0	0
T5	61154	10	0	0
T6	138967	22	0	0
T11	0	34	0	0
T19	0	6	0	0
T24	0	30	0	0
T26	1305	0	0	0
T27	2341	0	0	0
T28	1685	0	0	0
T29	891	0	0	0
T32	1517	0	0	0
T33	0	34	0	0
T37	1075	0	0	0
T38	2564	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	69250537	0	0
T5	61154	60958	0	0
T6	138967	138784	0	0
T7	1657	1600	0	0
T8	1605	1512	0	0
T9	1478	1421	0	0
T25	1121	1074	0	0
T26	1305	1199	0	0
T27	2341	2244	0	0
T28	1685	1573	0	0
T29	891	853	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T5,T6,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	71211163	60328	0	0
DstReqKnown_A	105849612	104039516	0	0
SrcAckBusyChk_A	71211163	12096	0	0
SrcBusyKnown_A	71211163	69250537	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	60328	0	0
T1	0	903	0	0
T2	0	870	0	0
T3	0	34	0	0
T4	36707	120	0	0
T5	61154	74	0	0
T6	138967	192	0	0
T11	0	265	0	0
T19	0	50	0	0
T24	0	131	0	0
T26	1305	0	0	0
T27	2341	0	0	0
T28	1685	0	0	0
T29	891	0	0	0
T32	1517	0	0	0
T33	0	85	0	0
T37	1075	0	0	0
T38	2564	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105849612	104039516	0	0
T5	26770	26675	0	0
T6	63824	63737	0	0
T7	3316	3201	0	0
T8	1640	1545	0	0
T9	1730	1663	0	0
T25	2244	2150	0	0
T26	1253	1152	0	0
T27	2293	2198	0	0
T28	809	756	0	0
T29	1712	1638	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	12096	0	0
T1	0	360	0	0
T2	0	104	0	0
T3	0	14	0	0
T4	36707	27	0	0
T5	61154	10	0	0
T6	138967	22	0	0
T11	0	34	0	0
T19	0	6	0	0
T24	0	15	0	0
T26	1305	0	0	0
T27	2341	0	0	0
T28	1685	0	0	0
T29	891	0	0	0
T32	1517	0	0	0
T33	0	34	0	0
T37	1075	0	0	0
T38	2564	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	69250537	0	0
T5	61154	60958	0	0
T6	138967	138784	0	0
T7	1657	1600	0	0
T8	1605	1512	0	0
T9	1478	1421	0	0
T25	1121	1074	0	0
T26	1305	1199	0	0
T27	2341	2244	0	0
T28	1685	1573	0	0
T29	891	853	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T24
1	0	Covered	T5,T6,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	71211163	66015	0	0
DstReqKnown_A	206993064	203386452	0	0
SrcAckBusyChk_A	71211163	18288	0	0
SrcBusyKnown_A	71211163	69250537	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	66015	0	0
T1	0	910	0	0
T2	0	541	0	0
T3	0	32	0	0
T4	36707	185	0	0
T5	61154	48	0	0
T6	138967	121	0	0
T11	0	173	0	0
T19	0	38	0	0
T24	0	295	0	0
T26	1305	0	0	0
T27	2341	0	0	0
T28	1685	0	0	0
T29	891	0	0	0
T32	1517	0	0	0
T33	0	85	0	0
T37	1075	0	0	0
T38	2564	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206993064	203386452	0	0
T5	53539	53349	0	0
T6	110367	110191	0	0
T7	6632	6402	0	0
T8	3279	3090	0	0
T9	3460	3326	0	0
T25	4488	4299	0	0
T26	2506	2303	0	0
T27	4586	4396	0	0
T28	1619	1511	0	0
T29	3426	3277	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	18288	0	0
T1	0	365	0	0
T2	0	104	0	0
T3	0	14	0	0
T4	36707	72	0	0
T5	61154	10	0	0
T6	138967	22	0	0
T11	0	34	0	0
T19	0	6	0	0
T24	0	60	0	0
T26	1305	0	0	0
T27	2341	0	0	0
T28	1685	0	0	0
T29	891	0	0	0
T32	1517	0	0	0
T33	0	34	0	0
T37	1075	0	0	0
T38	2564	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	69250537	0	0
T5	61154	60958	0	0
T6	138967	138784	0	0
T7	1657	1600	0	0
T8	1605	1512	0	0
T9	1478	1421	0	0
T25	1121	1074	0	0
T26	1305	1199	0	0
T27	2341	2244	0	0
T28	1685	1573	0	0
T29	891	853	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T24
1	0	Covered	T5,T6,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	71211163	95568	0	0
DstReqKnown_A	102748875	101862378	0	0
SrcAckBusyChk_A	71211163	18368	0	0
SrcBusyKnown_A	71211163	69250537	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	95568	0	0
T1	0	910	0	0
T2	0	873	0	0
T3	0	32	0	0
T4	36707	257	0	0
T5	61154	79	0	0
T6	138967	194	0	0
T11	0	268	0	0
T19	0	52	0	0
T24	0	470	0	0
T26	1305	0	0	0
T27	2341	0	0	0
T28	1685	0	0	0
T29	891	0	0	0
T32	1517	0	0	0
T33	0	85	0	0
T37	1075	0	0	0
T38	2564	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102748875	101862378	0	0
T5	26702	26674	0	0
T6	55222	55181	0	0
T7	3836	3781	0	0
T8	1626	1598	0	0
T9	1843	1829	0	0
T25	2198	2150	0	0
T26	1317	1248	0	0
T27	2567	2532	0	0
T28	770	756	0	0
T29	1659	1638	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	18368	0	0
T1	0	365	0	0
T2	0	104	0	0
T3	0	14	0	0
T4	36707	72	0	0
T5	61154	10	0	0
T6	138967	22	0	0
T11	0	34	0	0
T19	0	6	0	0
T24	0	60	0	0
T26	1305	0	0	0
T27	2341	0	0	0
T28	1685	0	0	0
T29	891	0	0	0
T32	1517	0	0	0
T33	0	34	0	0
T37	1075	0	0	0
T38	2564	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	69250537	0	0
T5	61154	60958	0	0
T6	138967	138784	0	0
T7	1657	1600	0	0
T8	1605	1512	0	0
T9	1478	1421	0	0
T25	1121	1074	0	0
T26	1305	1199	0	0
T27	2341	2244	0	0
T28	1685	1573	0	0
T29	891	853	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T24
1	0	Covered	T5,T6,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	71211163	155525	0	0
DstReqKnown_A	51374076	50930942	0	0
SrcAckBusyChk_A	71211163	18458	0	0
SrcBusyKnown_A	71211163	69250537	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	155525	0	0
T1	0	1090	0	0
T2	0	1530	0	0
T3	0	46	0	0
T4	36707	372	0	0
T5	61154	134	0	0
T6	138967	345	0	0
T11	0	481	0	0
T19	0	92	0	0
T24	0	824	0	0
T26	1305	0	0	0
T27	2341	0	0	0
T28	1685	0	0	0
T29	891	0	0	0
T32	1517	0	0	0
T33	0	104	0	0
T37	1075	0	0	0
T38	2564	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51374076	50930942	0	0
T5	13351	13337	0	0
T6	27609	27588	0	0
T7	1918	1891	0	0
T8	813	799	0	0
T9	921	914	0	0
T25	1099	1075	0	0
T26	659	625	0	0
T27	1281	1264	0	0
T28	385	378	0	0
T29	830	820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	18458	0	0
T1	0	365	0	0
T2	0	104	0	0
T3	0	14	0	0
T4	36707	72	0	0
T5	61154	10	0	0
T6	138967	22	0	0
T11	0	34	0	0
T19	0	6	0	0
T24	0	60	0	0
T26	1305	0	0	0
T27	2341	0	0	0
T28	1685	0	0	0
T29	891	0	0	0
T32	1517	0	0	0
T33	0	34	0	0
T37	1075	0	0	0
T38	2564	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	69250537	0	0
T5	61154	60958	0	0
T6	138967	138784	0	0
T7	1657	1600	0	0
T8	1605	1512	0	0
T9	1478	1421	0	0
T25	1121	1074	0	0
T26	1305	1199	0	0
T27	2341	2244	0	0
T28	1685	1573	0	0
T29	891	853	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T24
1	0	Covered	T5,T6,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	71211163	66905	0	0
DstReqKnown_A	220534961	216773775	0	0
SrcAckBusyChk_A	71211163	18416	0	0
SrcBusyKnown_A	71211163	69250537	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	66905	0	0
T1	0	910	0	0
T2	0	527	0	0
T3	0	32	0	0
T4	36707	181	0	0
T5	61154	48	0	0
T6	138967	138	0	0
T11	0	167	0	0
T19	0	31	0	0
T24	0	288	0	0
T26	1305	0	0	0
T27	2341	0	0	0
T28	1685	0	0	0
T29	891	0	0	0
T32	1517	0	0	0
T33	0	85	0	0
T37	1075	0	0	0
T38	2564	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220534961	216773775	0	0
T5	49771	49573	0	0
T6	114967	114784	0	0
T7	6909	6669	0	0
T8	3416	3219	0	0
T9	3604	3464	0	0
T25	4676	4479	0	0
T26	2611	2399	0	0
T27	4777	4580	0	0
T28	1685	1573	0	0
T29	3568	3413	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	18416	0	0
T1	0	365	0	0
T2	0	104	0	0
T3	0	14	0	0
T4	36707	72	0	0
T5	61154	10	0	0
T6	138967	22	0	0
T11	0	34	0	0
T19	0	6	0	0
T24	0	60	0	0
T26	1305	0	0	0
T27	2341	0	0	0
T28	1685	0	0	0
T29	891	0	0	0
T32	1517	0	0	0
T33	0	34	0	0
T37	1075	0	0	0
T38	2564	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	69250537	0	0
T5	61154	60958	0	0
T6	138967	138784	0	0
T7	1657	1600	0	0
T8	1605	1512	0	0
T9	1478	1421	0	0
T25	1121	1074	0	0
T26	1305	1199	0	0
T27	2341	2244	0	0
T28	1685	1573	0	0
T29	891	853	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T24
1	0	Covered	T5,T6,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	71211163	95588	0	0
DstReqKnown_A	105849612	104039516	0	0
SrcAckBusyChk_A	71211163	18021	0	0
SrcBusyKnown_A	71211163	69250537	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	95588	0	0
T1	0	910	0	0
T2	0	869	0	0
T3	0	32	0	0
T4	36707	255	0	0
T5	61154	76	0	0
T6	138967	190	0	0
T11	0	270	0	0
T19	0	50	0	0
T24	0	451	0	0
T26	1305	0	0	0
T27	2341	0	0	0
T28	1685	0	0	0
T29	891	0	0	0
T32	1517	0	0	0
T33	0	85	0	0
T37	1075	0	0	0
T38	2564	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105849612	104039516	0	0
T5	26770	26675	0	0
T6	63824	63737	0	0
T7	3316	3201	0	0
T8	1640	1545	0	0
T9	1730	1663	0	0
T25	2244	2150	0	0
T26	1253	1152	0	0
T27	2293	2198	0	0
T28	809	756	0	0
T29	1712	1638	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	18021	0	0
T1	0	365	0	0
T2	0	104	0	0
T3	0	14	0	0
T4	36707	72	0	0
T5	61154	10	0	0
T6	138967	22	0	0
T11	0	34	0	0
T19	0	6	0	0
T24	0	53	0	0
T26	1305	0	0	0
T27	2341	0	0	0
T28	1685	0	0	0
T29	891	0	0	0
T32	1517	0	0	0
T33	0	34	0	0
T37	1075	0	0	0
T38	2564	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71211163	69250537	0	0
T5	61154	60958	0	0
T6	138967	138784	0	0
T7	1657	1600	0	0
T8	1605	1512	0	0
T9	1478	1421	0	0
T25	1121	1074	0	0
T26	1305	1199	0	0
T27	2341	2244	0	0
T28	1685	1573	0	0
T29	891	853	0	0