Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	210877509	454	0	0
StatusRise_A	210877509	454	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210877509	454	0	0
T1	307945	0	0	0
T2	623119	0	0	0
T18	2001	0	0	0
T19	30324	0	0	0
T33	42460	0	0	0
T39	1358	0	0	0
T44	3409	0	0	0
T45	2496	15	0	0
T46	0	14	0	0
T47	0	11	0	0
T48	770	1	0	0
T114	2320	0	0	0
T115	3069	0	0	0
T117	5506	0	0	0
T118	3428	0	0	0
T150	2546	0	0	0
T159	1253	0	0	0
T165	0	2	0	0
T171	0	1	0	0
T172	0	18	0	0
T173	0	13	0	0
T174	0	10	0	0
T175	0	9	0	0
T176	0	11	0	0
T177	0	1	0	0
T178	0	7	0	0
T179	1924	0	0	0
T180	3610	0	0	0
T181	3646	0	0	0
T182	1848	0	0	0
T183	2358	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210877509	454	0	0
T1	307945	0	0	0
T2	623119	0	0	0
T18	2001	0	0	0
T19	30324	0	0	0
T33	42460	0	0	0
T39	1358	0	0	0
T44	3409	0	0	0
T45	2496	15	0	0
T46	0	14	0	0
T47	0	11	0	0
T48	770	1	0	0
T114	2320	0	0	0
T115	3069	0	0	0
T117	5506	0	0	0
T118	3428	0	0	0
T150	2546	0	0	0
T159	1253	0	0	0
T165	0	2	0	0
T171	0	1	0	0
T172	0	18	0	0
T173	0	13	0	0
T174	0	10	0	0
T175	0	9	0	0
T176	0	11	0	0
T177	0	1	0	0
T178	0	7	0	0
T179	1924	0	0	0
T180	3610	0	0	0
T181	3646	0	0	0
T182	1848	0	0	0
T183	2358	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	70292503	150	0	0
StatusRise_A	70292503	150	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70292503	150	0	0
T1	307945	0	0	0
T2	623119	0	0	0
T18	2001	0	0	0
T19	30324	0	0	0
T39	1358	0	0	0
T44	3409	0	0	0
T45	0	5	0	0
T46	0	4	0	0
T47	0	3	0	0
T48	770	1	0	0
T114	2320	0	0	0
T115	3069	0	0	0
T159	1253	0	0	0
T165	0	1	0	0
T172	0	5	0	0
T173	0	4	0	0
T174	0	4	0	0
T175	0	3	0	0
T176	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70292503	150	0	0
T1	307945	0	0	0
T2	623119	0	0	0
T18	2001	0	0	0
T19	30324	0	0	0
T39	1358	0	0	0
T44	3409	0	0	0
T45	0	5	0	0
T46	0	4	0	0
T47	0	3	0	0
T48	770	1	0	0
T114	2320	0	0	0
T115	3069	0	0	0
T159	1253	0	0	0
T165	0	1	0	0
T172	0	5	0	0
T173	0	4	0	0
T174	0	4	0	0
T175	0	3	0	0
T176	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	70292503	155	0	0
StatusRise_A	70292503	155	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70292503	155	0	0
T33	21230	0	0	0
T45	1248	5	0	0
T46	0	6	0	0
T47	0	4	0	0
T117	2753	0	0	0
T118	1714	0	0	0
T150	1273	0	0	0
T165	0	1	0	0
T171	0	1	0	0
T172	0	6	0	0
T173	0	5	0	0
T174	0	4	0	0
T175	0	3	0	0
T176	0	4	0	0
T179	962	0	0	0
T180	1805	0	0	0
T181	1823	0	0	0
T182	924	0	0	0
T183	1179	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70292503	155	0	0
T33	21230	0	0	0
T45	1248	5	0	0
T46	0	6	0	0
T47	0	4	0	0
T117	2753	0	0	0
T118	1714	0	0	0
T150	1273	0	0	0
T165	0	1	0	0
T171	0	1	0	0
T172	0	6	0	0
T173	0	5	0	0
T174	0	4	0	0
T175	0	3	0	0
T176	0	4	0	0
T179	962	0	0	0
T180	1805	0	0	0
T181	1823	0	0	0
T182	924	0	0	0
T183	1179	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	70292503	149	0	0
StatusRise_A	70292503	149	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70292503	149	0	0
T33	21230	0	0	0
T45	1248	5	0	0
T46	0	4	0	0
T47	0	4	0	0
T117	2753	0	0	0
T118	1714	0	0	0
T150	1273	0	0	0
T172	0	7	0	0
T173	0	4	0	0
T174	0	2	0	0
T175	0	3	0	0
T176	0	4	0	0
T177	0	1	0	0
T178	0	7	0	0
T179	962	0	0	0
T180	1805	0	0	0
T181	1823	0	0	0
T182	924	0	0	0
T183	1179	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70292503	149	0	0
T33	21230	0	0	0
T45	1248	5	0	0
T46	0	4	0	0
T47	0	4	0	0
T117	2753	0	0	0
T118	1714	0	0	0
T150	1273	0	0	0
T172	0	7	0	0
T173	0	4	0	0
T174	0	2	0	0
T175	0	3	0	0
T176	0	4	0	0
T177	0	1	0	0
T178	0	7	0	0
T179	962	0	0	0
T180	1805	0	0	0
T181	1823	0	0	0
T182	924	0	0	0
T183	1179	0	0	0