Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T48,T1
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	29322	0	0
CgEnOn_A	2147483647	21636	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	29322	0	0
T5	143363	3	0	0
T6	308165	16	0	0
T7	12386	3	0	0
T8	5718	3	0	0
T9	6224	3	0	0
T15	0	5	0	0
T25	12461	7	0	0
T26	7093	3	0	0
T27	13211	3	0	0
T28	4459	3	0	0
T29	9483	10	0	0
T32	3297	0	0	0
T33	366823	0	0	0
T45	8238	25	0	0
T46	0	30	0	0
T47	0	20	0	0
T48	0	1	0	0
T74	0	5	0	0
T117	6099	0	0	0
T118	28417	0	0	0
T150	20669	0	0	0
T165	0	5	0	0
T171	0	5	0	0
T172	0	30	0	0
T173	0	25	0	0
T174	0	20	0	0
T179	8172	0	0	0
T180	8321	0	0	0
T181	3967	0	0	0
T182	7842	0	0	0
T183	21804	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21636	0	0
T1	0	40	0	0
T2	0	71	0	0
T4	352420	0	0	0
T6	308165	9	0	0
T12	0	61	0	0
T15	0	4	0	0
T25	4676	0	0	0
T27	13211	0	0	0
T28	4459	0	0	0
T29	9483	5	0	0
T32	9077	0	0	0
T33	366823	0	0	0
T37	11933	24	0	0
T38	4697	0	0	0
T39	4637	0	0	0
T45	8238	35	0	0
T46	0	30	0	0
T47	0	20	0	0
T48	5608	0	0	0
T49	0	2	0	0
T74	0	4	0	0
T117	6099	0	0	0
T118	28417	0	0	0
T150	20669	0	0	0
T159	0	25	0	0
T165	0	5	0	0
T171	0	5	0	0
T172	0	30	0	0
T173	0	25	0	0
T174	0	20	0	0
T175	0	3	0	0
T176	0	4	0	0
T179	8172	0	0	0
T180	8321	0	0	0
T181	3967	0	0	0
T182	7842	0	0	0
T183	21804	0	0	0
T184	0	31	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	101631881	159	0	0
CgEnOn_A	101631881	159	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101631881	159	0	0
T15	0	1	0	0
T33	81495	0	0	0
T45	1816	5	0	0
T46	0	6	0	0
T47	0	4	0	0
T74	0	1	0	0
T117	1350	0	0	0
T118	6303	0	0	0
T150	4774	0	0	0
T165	0	1	0	0
T171	0	1	0	0
T172	0	6	0	0
T173	0	5	0	0
T174	0	4	0	0
T179	1846	0	0	0
T180	1913	0	0	0
T181	873	0	0	0
T182	1716	0	0	0
T183	5891	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101631881	159	0	0
T15	0	1	0	0
T33	81495	0	0	0
T45	1816	5	0	0
T46	0	6	0	0
T47	0	4	0	0
T74	0	1	0	0
T117	1350	0	0	0
T118	6303	0	0	0
T150	4774	0	0	0
T165	0	1	0	0
T171	0	1	0	0
T172	0	6	0	0
T173	0	5	0	0
T174	0	4	0	0
T179	1846	0	0	0
T180	1913	0	0	0
T181	873	0	0	0
T182	1716	0	0	0
T183	5891	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	50815584	159	0	0
CgEnOn_A	50815584	159	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50815584	159	0	0
T15	0	1	0	0
T33	40748	0	0	0
T45	908	5	0	0
T46	0	6	0	0
T47	0	4	0	0
T74	0	1	0	0
T117	675	0	0	0
T118	3152	0	0	0
T150	2386	0	0	0
T165	0	1	0	0
T171	0	1	0	0
T172	0	6	0	0
T173	0	5	0	0
T174	0	4	0	0
T179	923	0	0	0
T180	957	0	0	0
T181	436	0	0	0
T182	858	0	0	0
T183	2945	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50815584	159	0	0
T15	0	1	0	0
T33	40748	0	0	0
T45	908	5	0	0
T46	0	6	0	0
T47	0	4	0	0
T74	0	1	0	0
T117	675	0	0	0
T118	3152	0	0	0
T150	2386	0	0	0
T165	0	1	0	0
T171	0	1	0	0
T172	0	6	0	0
T173	0	5	0	0
T174	0	4	0	0
T179	923	0	0	0
T180	957	0	0	0
T181	436	0	0	0
T182	858	0	0	0
T183	2945	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	50815584	159	0	0
CgEnOn_A	50815584	159	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50815584	159	0	0
T15	0	1	0	0
T33	40748	0	0	0
T45	908	5	0	0
T46	0	6	0	0
T47	0	4	0	0
T74	0	1	0	0
T117	675	0	0	0
T118	3152	0	0	0
T150	2386	0	0	0
T165	0	1	0	0
T171	0	1	0	0
T172	0	6	0	0
T173	0	5	0	0
T174	0	4	0	0
T179	923	0	0	0
T180	957	0	0	0
T181	436	0	0	0
T182	858	0	0	0
T183	2945	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50815584	159	0	0
T15	0	1	0	0
T33	40748	0	0	0
T45	908	5	0	0
T46	0	6	0	0
T47	0	4	0	0
T74	0	1	0	0
T117	675	0	0	0
T118	3152	0	0	0
T150	2386	0	0	0
T165	0	1	0	0
T171	0	1	0	0
T172	0	6	0	0
T173	0	5	0	0
T174	0	4	0	0
T179	923	0	0	0
T180	957	0	0	0
T181	436	0	0	0
T182	858	0	0	0
T183	2945	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	50815584	159	0	0
CgEnOn_A	50815584	159	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50815584	159	0	0
T15	0	1	0	0
T33	40748	0	0	0
T45	908	5	0	0
T46	0	6	0	0
T47	0	4	0	0
T74	0	1	0	0
T117	675	0	0	0
T118	3152	0	0	0
T150	2386	0	0	0
T165	0	1	0	0
T171	0	1	0	0
T172	0	6	0	0
T173	0	5	0	0
T174	0	4	0	0
T179	923	0	0	0
T180	957	0	0	0
T181	436	0	0	0
T182	858	0	0	0
T183	2945	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50815584	159	0	0
T15	0	1	0	0
T33	40748	0	0	0
T45	908	5	0	0
T46	0	6	0	0
T47	0	4	0	0
T74	0	1	0	0
T117	675	0	0	0
T118	3152	0	0	0
T150	2386	0	0	0
T165	0	1	0	0
T171	0	1	0	0
T172	0	6	0	0
T173	0	5	0	0
T174	0	4	0	0
T179	923	0	0	0
T180	957	0	0	0
T181	436	0	0	0
T182	858	0	0	0
T183	2945	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	204664949	159	0	0
CgEnOn_A	204664949	155	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204664949	159	0	0
T15	0	1	0	0
T33	163084	0	0	0
T45	3698	5	0	0
T46	0	6	0	0
T47	0	4	0	0
T74	0	1	0	0
T117	2724	0	0	0
T118	12658	0	0	0
T150	8737	0	0	0
T165	0	1	0	0
T171	0	1	0	0
T172	0	6	0	0
T173	0	5	0	0
T174	0	4	0	0
T179	3557	0	0	0
T180	3537	0	0	0
T181	1786	0	0	0
T182	3552	0	0	0
T183	7078	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204664949	155	0	0
T33	163084	0	0	0
T45	3698	5	0	0
T46	0	6	0	0
T47	0	4	0	0
T117	2724	0	0	0
T118	12658	0	0	0
T150	8737	0	0	0
T165	0	1	0	0
T171	0	1	0	0
T172	0	6	0	0
T173	0	5	0	0
T174	0	4	0	0
T175	0	3	0	0
T176	0	4	0	0
T179	3557	0	0	0
T180	3537	0	0	0
T181	1786	0	0	0
T182	3552	0	0	0
T183	7078	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T48,T1
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	218109731	152	0	0
CgEnOn_A	218109731	151	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218109731	152	0	0
T1	384032	0	0	0
T2	623830	0	0	0
T18	2084	0	0	0
T19	31589	0	0	0
T39	2771	0	0	0
T44	3625	0	0	0
T45	0	5	0	0
T46	0	4	0	0
T47	0	3	0	0
T48	3311	1	0	0
T77	0	1	0	0
T114	2367	0	0	0
T115	12790	0	0	0
T159	3057	0	0	0
T165	0	1	0	0
T172	0	5	0	0
T173	0	4	0	0
T174	0	4	0	0
T175	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218109731	151	0	0
T1	384032	0	0	0
T2	623830	0	0	0
T18	2084	0	0	0
T19	31589	0	0	0
T39	2771	0	0	0
T44	3625	0	0	0
T45	0	5	0	0
T46	0	4	0	0
T47	0	3	0	0
T48	3311	1	0	0
T77	0	1	0	0
T114	2367	0	0	0
T115	12790	0	0	0
T159	3057	0	0	0
T165	0	1	0	0
T172	0	5	0	0
T173	0	4	0	0
T174	0	4	0	0
T175	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T48,T1
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	218109731	152	0	0
CgEnOn_A	218109731	151	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218109731	152	0	0
T1	384032	0	0	0
T2	623830	0	0	0
T18	2084	0	0	0
T19	31589	0	0	0
T39	2771	0	0	0
T44	3625	0	0	0
T45	0	5	0	0
T46	0	4	0	0
T47	0	3	0	0
T48	3311	1	0	0
T77	0	1	0	0
T114	2367	0	0	0
T115	12790	0	0	0
T159	3057	0	0	0
T165	0	1	0	0
T172	0	5	0	0
T173	0	4	0	0
T174	0	4	0	0
T175	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218109731	151	0	0
T1	384032	0	0	0
T2	623830	0	0	0
T18	2084	0	0	0
T19	31589	0	0	0
T39	2771	0	0	0
T44	3625	0	0	0
T45	0	5	0	0
T46	0	4	0	0
T47	0	3	0	0
T48	3311	1	0	0
T77	0	1	0	0
T114	2367	0	0	0
T115	12790	0	0	0
T159	3057	0	0	0
T165	0	1	0	0
T172	0	5	0	0
T173	0	4	0	0
T174	0	4	0	0
T175	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	104685527	149	0	0
CgEnOn_A	104685527	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104685527	149	0	0
T33	110346	0	0	0
T45	2049	5	0	0
T46	0	4	0	0
T47	0	4	0	0
T117	1362	0	0	0
T118	6329	0	0	0
T150	4369	0	0	0
T172	0	7	0	0
T173	0	4	0	0
T174	0	2	0	0
T175	0	3	0	0
T176	0	4	0	0
T177	0	1	0	0
T178	0	7	0	0
T179	1778	0	0	0
T180	1768	0	0	0
T181	892	0	0	0
T182	1776	0	0	0
T183	3540	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104685527	149	0	0
T33	110346	0	0	0
T45	2049	5	0	0
T46	0	4	0	0
T47	0	4	0	0
T117	1362	0	0	0
T118	6329	0	0	0
T150	4369	0	0	0
T172	0	7	0	0
T173	0	4	0	0
T174	0	2	0	0
T175	0	3	0	0
T176	0	4	0	0
T177	0	1	0	0
T178	0	7	0	0
T179	1778	0	0	0
T180	1768	0	0	0
T181	892	0	0	0
T182	1776	0	0	0
T183	3540	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T45,T46,T47
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	50815584	4827	0	0
CgEnOn_A	50815584	2910	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50815584	4827	0	0
T5	13351	1	0	0
T6	27609	6	0	0
T7	1918	1	0	0
T8	813	1	0	0
T9	921	1	0	0
T25	1099	1	0	0
T26	659	1	0	0
T27	1281	1	0	0
T28	385	1	0	0
T29	830	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50815584	2910	0	0
T1	0	20	0	0
T2	0	38	0	0
T4	21544	0	0	0
T6	27609	5	0	0
T12	0	29	0	0
T27	1281	0	0	0
T28	385	0	0	0
T29	830	2	0	0
T32	872	0	0	0
T37	1049	13	0	0
T38	692	0	0	0
T39	659	0	0	0
T45	0	5	0	0
T48	798	0	0	0
T49	0	1	0	0
T159	0	13	0	0
T184	0	16	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T45,T46,T47
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	101631881	4837	0	0
CgEnOn_A	101631881	2920	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101631881	4837	0	0
T5	26702	1	0	0
T6	55222	5	0	0
T7	3836	1	0	0
T8	1626	1	0	0
T9	1843	1	0	0
T25	2198	1	0	0
T26	1317	1	0	0
T27	2567	1	0	0
T28	770	1	0	0
T29	1659	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101631881	2920	0	0
T1	0	20	0	0
T2	0	33	0	0
T4	43091	0	0	0
T6	55222	4	0	0
T12	0	32	0	0
T27	2567	0	0	0
T28	770	0	0	0
T29	1659	3	0	0
T32	1743	0	0	0
T37	2098	11	0	0
T38	1387	0	0	0
T39	1318	0	0	0
T45	0	5	0	0
T48	1595	0	0	0
T49	0	1	0	0
T159	0	12	0	0
T184	0	15	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T45,T46,T47
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	204664949	4861	0	0
CgEnOn_A	204664949	2940	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204664949	4861	0	0
T5	53539	1	0	0
T6	110367	4	0	0
T7	6632	1	0	0
T8	3279	1	0	0
T9	3460	1	0	0
T25	4488	1	0	0
T26	2506	1	0	0
T27	4586	1	0	0
T28	1619	1	0	0
T29	3426	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204664949	2940	0	0
T1	0	20	0	0
T2	0	38	0	0
T4	140953	0	0	0
T6	110367	3	0	0
T12	0	33	0	0
T27	4586	0	0	0
T28	1619	0	0	0
T29	3426	2	0	0
T32	3165	0	0	0
T37	4303	12	0	0
T38	2618	0	0	0
T39	2660	0	0	0
T45	0	5	0	0
T48	3215	0	0	0
T49	0	1	0	0
T159	0	12	0	0
T184	0	17	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T45,T46,T47
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	104685527	4823	0	0
CgEnOn_A	104685527	2902	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104685527	4823	0	0
T5	26770	1	0	0
T6	63824	5	0	0
T7	3316	1	0	0
T8	1640	1	0	0
T9	1730	1	0	0
T25	2244	1	0	0
T26	1253	1	0	0
T27	2293	1	0	0
T28	809	1	0	0
T29	1712	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104685527	2902	0	0
T1	0	20	0	0
T2	0	36	0	0
T4	70479	0	0	0
T6	63824	4	0	0
T12	0	32	0	0
T27	2293	0	0	0
T28	809	0	0	0
T29	1712	3	0	0
T32	1582	0	0	0
T37	2151	13	0	0
T38	1309	0	0	0
T39	1330	0	0	0
T45	0	5	0	0
T48	1608	0	0	0
T49	0	1	0	0
T159	0	11	0	0
T184	0	17	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T48,T1
1	0	Covered	T25,T6,T44
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	218109731	2222	0	0
CgEnOn_A	218109731	2221	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218109731	2222	0	0
T1	0	59	0	0
T2	0	4	0	0
T4	146832	0	0	0
T5	49771	0	0	0
T6	114967	1	0	0
T23	0	8	0	0
T25	4676	4	0	0
T26	2611	0	0	0
T27	4777	0	0	0
T28	1685	0	0	0
T29	3568	0	0	0
T32	3297	0	0	0
T37	4483	0	0	0
T44	0	7	0	0
T48	0	1	0	0
T49	0	1	0	0
T115	0	11	0	0
T116	0	8	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218109731	2221	0	0
T1	0	59	0	0
T2	0	4	0	0
T4	146832	0	0	0
T5	49771	0	0	0
T6	114967	1	0	0
T23	0	8	0	0
T25	4676	4	0	0
T26	2611	0	0	0
T27	4777	0	0	0
T28	1685	0	0	0
T29	3568	0	0	0
T32	3297	0	0	0
T37	4483	0	0	0
T44	0	7	0	0
T48	0	1	0	0
T49	0	1	0	0
T115	0	11	0	0
T116	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T48,T1
1	0	Covered	T25,T6,T44
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	218109731	2153	0	0
CgEnOn_A	218109731	2152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218109731	2153	0	0
T1	0	43	0	0
T2	0	7	0	0
T4	146832	0	0	0
T5	49771	0	0	0
T6	114967	1	0	0
T23	0	6	0	0
T25	4676	3	0	0
T26	2611	0	0	0
T27	4777	0	0	0
T28	1685	0	0	0
T29	3568	0	0	0
T32	3297	0	0	0
T37	4483	0	0	0
T44	0	7	0	0
T48	0	1	0	0
T49	0	1	0	0
T115	0	6	0	0
T116	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218109731	2152	0	0
T1	0	43	0	0
T2	0	7	0	0
T4	146832	0	0	0
T5	49771	0	0	0
T6	114967	1	0	0
T23	0	6	0	0
T25	4676	3	0	0
T26	2611	0	0	0
T27	4777	0	0	0
T28	1685	0	0	0
T29	3568	0	0	0
T32	3297	0	0	0
T37	4483	0	0	0
T44	0	7	0	0
T48	0	1	0	0
T49	0	1	0	0
T115	0	6	0	0
T116	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T48,T1
1	0	Covered	T25,T6,T44
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	218109731	2163	0	0
CgEnOn_A	218109731	2162	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218109731	2163	0	0
T1	0	50	0	0
T2	0	7	0	0
T4	146832	0	0	0
T5	49771	0	0	0
T6	114967	2	0	0
T23	0	7	0	0
T25	4676	2	0	0
T26	2611	0	0	0
T27	4777	0	0	0
T28	1685	0	0	0
T29	3568	0	0	0
T32	3297	0	0	0
T37	4483	0	0	0
T44	0	7	0	0
T48	0	1	0	0
T49	0	1	0	0
T115	0	10	0	0
T116	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218109731	2162	0	0
T1	0	50	0	0
T2	0	7	0	0
T4	146832	0	0	0
T5	49771	0	0	0
T6	114967	2	0	0
T23	0	7	0	0
T25	4676	2	0	0
T26	2611	0	0	0
T27	4777	0	0	0
T28	1685	0	0	0
T29	3568	0	0	0
T32	3297	0	0	0
T37	4483	0	0	0
T44	0	7	0	0
T48	0	1	0	0
T49	0	1	0	0
T115	0	10	0	0
T116	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T48,T1
1	0	Covered	T25,T6,T44
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	218109731	2188	0	0
CgEnOn_A	218109731	2187	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218109731	2188	0	0
T1	0	47	0	0
T2	0	8	0	0
T4	146832	0	0	0
T5	49771	0	0	0
T6	114967	3	0	0
T23	0	5	0	0
T25	4676	2	0	0
T26	2611	0	0	0
T27	4777	0	0	0
T28	1685	0	0	0
T29	3568	0	0	0
T32	3297	0	0	0
T37	4483	0	0	0
T44	0	10	0	0
T48	0	1	0	0
T49	0	1	0	0
T115	0	8	0	0
T116	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218109731	2187	0	0
T1	0	47	0	0
T2	0	8	0	0
T4	146832	0	0	0
T5	49771	0	0	0
T6	114967	3	0	0
T23	0	5	0	0
T25	4676	2	0	0
T26	2611	0	0	0
T27	4777	0	0	0
T28	1685	0	0	0
T29	3568	0	0	0
T32	3297	0	0	0
T37	4483	0	0	0
T44	0	10	0	0
T48	0	1	0	0
T49	0	1	0	0
T115	0	8	0	0
T116	0	9	0	0