Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	233645	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

908550

1

T5

1

T6

20

T4

68

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	303641	1			T6	20		T4	12		T1	44
values[0x0]	389048	1			T5	2		T6	21		T4	60
values[0x1]	449506	1			T6	20		T4	68		T1	206

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	146319	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

995876

1

T5

1

T6

24

T4

97

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4621	1			T6	16		T41	3		T8	311
valid_sources[0x01]	4733	1			T2	2		T16	1		T18	1
valid_sources[0x02]	4898	1			T16	1		T20	1		T8	276
valid_sources[0x03]	3949	1			T18	1		T3	1		T91	2
valid_sources[0x04]	4114	1			T4	1		T3	1		T20	2
valid_sources[0x05]	4145	1			T18	1		T8	248		T118	1
valid_sources[0x06]	4231	1			T4	6		T3	1		T34	2
valid_sources[0x07]	4590	1			T4	1		T20	2		T8	250
valid_sources[0x08]	4703	1			T3	2		T20	1		T34	1
valid_sources[0x09]	4413	1			T4	1		T18	1		T3	1
valid_sources[0x0a]	4487	1			T18	1		T41	3		T8	238
valid_sources[0x0b]	5036	1			T3	1		T91	1		T34	2
valid_sources[0x0c]	4176	1			T2	2		T19	1		T91	1
valid_sources[0x0d]	4333	1			T34	1		T8	264		T9	2
valid_sources[0x0e]	4835	1			T18	1		T19	1		T3	2
valid_sources[0x0f]	4124	1			T2	3		T3	3		T8	263
valid_sources[0x10]	4408	1			T8	274		T9	1		T28	6
valid_sources[0x11]	4662	1			T3	1		T91	2		T34	1
valid_sources[0x12]	4288	1			T2	1		T16	1		T3	2
valid_sources[0x13]	4019	1			T3	1		T20	1		T34	1
valid_sources[0x14]	4431	1			T34	1		T8	233		T9	1
valid_sources[0x15]	4752	1			T4	5		T19	5		T3	3
valid_sources[0x16]	4306	1			T4	3		T3	1		T20	5
valid_sources[0x17]	4270	1			T4	2		T3	2		T91	1
valid_sources[0x18]	4121	1			T3	2		T34	1		T8	245
valid_sources[0x19]	4030	1			T2	1		T19	1		T3	1
valid_sources[0x1a]	3836	1			T4	3		T3	3		T20	1
valid_sources[0x1b]	5563	1			T3	1		T91	1		T8	283
valid_sources[0x1c]	4268	1			T20	1		T8	247		T9	2
valid_sources[0x1d]	4543	1			T18	1		T20	1		T8	264
valid_sources[0x1e]	4328	1			T2	5		T3	1		T34	1
valid_sources[0x1f]	3981	1			T18	1		T19	4		T3	4
valid_sources[0x20]	4521	1			T6	1		T16	2		T8	300
valid_sources[0x21]	4388	1			T18	3		T3	2		T8	245
valid_sources[0x22]	4221	1			T20	2		T8	208		T9	2
valid_sources[0x23]	4418	1			T8	211		T9	2		T79	2
valid_sources[0x24]	4465	1			T6	3		T8	234		T79	2
valid_sources[0x25]	4927	1			T91	1		T8	306		T28	7
valid_sources[0x26]	4473	1			T3	2		T20	2		T8	291
valid_sources[0x27]	4413	1			T2	1		T18	1		T91	1
valid_sources[0x28]	3981	1			T2	3		T3	1		T38	1
valid_sources[0x29]	4256	1			T4	1		T3	2		T20	1
valid_sources[0x2a]	6643	1			T18	1		T8	240		T75	2
valid_sources[0x2b]	4629	1			T2	1		T19	1		T41	2
valid_sources[0x2c]	4101	1			T2	3		T18	1		T19	1
valid_sources[0x2d]	4728	1			T4	1		T3	3		T8	252
valid_sources[0x2e]	4683	1			T18	1		T3	1		T34	1
valid_sources[0x2f]	4258	1			T19	9		T3	2		T91	1
valid_sources[0x30]	4520	1			T4	4		T3	3		T20	3
valid_sources[0x31]	4175	1			T20	2		T8	241		T9	2
valid_sources[0x32]	4193	1			T3	1		T8	260		T9	2
valid_sources[0x33]	4186	1			T18	1		T3	1		T20	2
valid_sources[0x34]	5550	1			T4	3		T3	1		T20	1
valid_sources[0x35]	4832	1			T18	1		T3	1		T8	277
valid_sources[0x36]	4298	1			T4	1		T18	1		T3	1
valid_sources[0x37]	4014	1			T2	1		T3	3		T41	1
valid_sources[0x38]	4465	1			T3	1		T8	270		T9	1
valid_sources[0x39]	3749	1			T6	1		T18	2		T3	2
valid_sources[0x3a]	5006	1			T3	2		T8	273		T28	1
valid_sources[0x3b]	4707	1			T3	3		T8	270		T9	3
valid_sources[0x3c]	4815	1			T20	3		T8	245		T9	1
valid_sources[0x3d]	4797	1			T18	1		T3	2		T34	2
valid_sources[0x3e]	4921	1			T4	4		T2	2		T3	1
valid_sources[0x3f]	4214	1			T4	1		T19	3		T3	4
valid_sources[0x40]	4215	1			T4	1		T18	1		T8	228
valid_sources[0x41]	4206	1			T4	1		T8	249		T9	3
valid_sources[0x42]	4757	1			T4	1		T3	4		T8	269
valid_sources[0x43]	4573	1			T2	1		T16	1		T3	2
valid_sources[0x44]	4571	1			T2	1		T18	1		T3	1
valid_sources[0x45]	4319	1			T4	2		T3	2		T20	1
valid_sources[0x46]	5100	1			T2	1		T3	1		T20	1
valid_sources[0x47]	4636	1			T3	1		T8	245		T9	5
valid_sources[0x48]	4597	1			T4	1		T2	1		T18	1
valid_sources[0x49]	4445	1			T4	1		T16	1		T18	1
valid_sources[0x4a]	4583	1			T4	1		T3	1		T91	1
valid_sources[0x4b]	4560	1			T8	264		T9	3		T26	1
valid_sources[0x4c]	4160	1			T2	1		T8	267		T75	4
valid_sources[0x4d]	5803	1			T18	1		T3	1		T20	2
valid_sources[0x4e]	4543	1			T4	1		T2	2		T18	1
valid_sources[0x4f]	4683	1			T2	1		T20	3		T91	1
valid_sources[0x50]	4354	1			T3	2		T20	1		T41	2
valid_sources[0x51]	4437	1			T6	1		T4	1		T8	206
valid_sources[0x52]	4557	1			T3	1		T8	266		T9	1
valid_sources[0x53]	3776	1			T4	3		T18	1		T41	3
valid_sources[0x54]	4819	1			T18	1		T3	2		T8	281
valid_sources[0x55]	4493	1			T3	1		T8	250		T9	6
valid_sources[0x56]	4420	1			T3	1		T8	246		T9	3
valid_sources[0x57]	4279	1			T4	1		T2	1		T3	3
valid_sources[0x58]	3579	1			T4	1		T3	1		T20	2
valid_sources[0x59]	4429	1			T2	2		T18	1		T8	244
valid_sources[0x5a]	4158	1			T4	2		T18	1		T3	1
valid_sources[0x5b]	4278	1			T3	1		T8	240		T9	2
valid_sources[0x5c]	4075	1			T6	2		T2	2		T18	2
valid_sources[0x5d]	4372	1			T4	1		T2	1		T18	1
valid_sources[0x5e]	4444	1			T104	2		T8	260		T26	6
valid_sources[0x5f]	4615	1			T3	1		T8	256		T9	1
valid_sources[0x60]	3986	1			T2	1		T18	1		T3	1
valid_sources[0x61]	4324	1			T3	1		T91	1		T8	274
valid_sources[0x62]	4231	1			T18	2		T3	1		T8	235
valid_sources[0x63]	4417	1			T2	1		T3	3		T8	259
valid_sources[0x64]	4447	1			T2	2		T104	3		T8	285
valid_sources[0x65]	3909	1			T4	1		T18	1		T41	3
valid_sources[0x66]	4748	1			T4	3		T19	1		T3	2
valid_sources[0x67]	4533	1			T2	1		T3	2		T91	1
valid_sources[0x68]	4249	1			T16	1		T19	3		T3	3
valid_sources[0x69]	4595	1			T8	332		T26	3		T28	16
valid_sources[0x6a]	4388	1			T8	301		T9	2		T79	1
valid_sources[0x6b]	4545	1			T8	220		T9	2		T117	4
valid_sources[0x6c]	4560	1			T1	466		T2	1		T8	207
valid_sources[0x6d]	3971	1			T3	2		T8	315		T79	1
valid_sources[0x6e]	4389	1			T4	1		T2	1		T18	1
valid_sources[0x6f]	4164	1			T8	249		T9	1		T77	3
valid_sources[0x70]	4392	1			T3	2		T20	4		T104	3
valid_sources[0x71]	4076	1			T3	2		T91	1		T8	254
valid_sources[0x72]	4465	1			T2	2		T3	1		T91	3
valid_sources[0x73]	4750	1			T2	1		T3	1		T8	253
valid_sources[0x74]	3923	1			T3	3		T8	220		T9	3
valid_sources[0x75]	4030	1			T18	1		T19	1		T8	260
valid_sources[0x76]	4418	1			T2	4		T18	2		T91	1
valid_sources[0x77]	4474	1			T4	1		T8	272		T9	1
valid_sources[0x78]	4306	1			T6	1		T2	1		T8	293
valid_sources[0x79]	4533	1			T8	311		T147	6		T28	1
valid_sources[0x7a]	4219	1			T18	1		T3	1		T91	1
valid_sources[0x7b]	4394	1			T6	3		T4	1		T18	1
valid_sources[0x7c]	4540	1			T19	3		T34	1		T8	302
valid_sources[0x7d]	4300	1			T4	3		T16	1		T18	2
valid_sources[0x7e]	4054	1			T4	1		T34	1		T8	257
valid_sources[0x7f]	3944	1			T18	2		T3	2		T91	1
valid_sources[0x80]	4842	1			T2	3		T18	1		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

237628

1

T6

11

T4

5

T1

23

values[0x0]

all_enables

biggest_size

346687

1

T5

1

T6

4

T4

40

values[0x1]

all_enables

biggest_size

324235

1

T6

5

T4

23

T1

75