Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_peri_cg_wrap::peri_cg

Group : clkmgr_env_pkg::clkmgr_peri_cg_wrap::peri_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
PeriDiv2	100.00	1	100	1	64	64
PeriDiv4	100.00	1	100	1	64	64
PeriIo	100.00	1	100	1	64	64
PeriUsb	100.00	1	100	1	64	64

---

Group Instance : PeriDiv2

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance PeriDiv2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	6	0	6	100.00

Variables for Group Instance PeriDiv2

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_enable_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance PeriDiv2

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
peri_cross	6	0	6	100.00	100	1	1	0

---

Group Instance : PeriDiv4

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance PeriDiv4

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	6	0	6	100.00

Variables for Group Instance PeriDiv4

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_enable_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance PeriDiv4

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
peri_cross	6	0	6	100.00	100	1	1	0

---

Group Instance : PeriIo

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance PeriIo

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	6	0	6	100.00

Variables for Group Instance PeriIo

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_enable_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance PeriIo

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
peri_cross	6	0	6	100.00	100	1	1	0

---

Group Instance : PeriUsb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance PeriUsb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	6	0	6	100.00

Variables for Group Instance PeriUsb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_enable_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance PeriUsb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
peri_cross	6	0	6	100.00	100	1	1	0

Summary for Variable csr_enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

210321

1

T5

2

T6

2

T4

2

auto[1]

101448537

1

T5

2289

T6

4542

T4

32542

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7683

1

T5

2

T6

2

T4

2

auto[1]

101651175

1

T5

2289

T6

4542

T4

32542

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58334806

1

T5

2255

T6

3947

T4

32539

auto[1]

43324052

1

T5

36

T6

597

T4

5

---

Summary for Cross peri_cross

Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	6	0	6	100.00
Automatically Generated Cross Bins	6	0	6	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for peri_cross

Bins

csr_enable_cp

ip_clk_en_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

5104

1

T6

2

T1

2

T2

2

auto[0]

auto[0]

auto[1]

1268

1

T5

2

T4

2

T16

2

auto[0]

auto[1]

auto[0]

171884

1

T19

6

T41

70

T8

952

auto[0]

auto[1]

auto[1]

32065

1

T41

65

T8

843

T10

66

auto[1]

auto[1]

auto[0]

58156507

1

T5

2255

T6

3945

T4

32539

auto[1]

auto[1]

auto[1]

43290719

1

T5

34

T6

597

T4

3

User Defined Cross Bins for peri_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_enable_off	0	Excluded

Summary for Variable csr_enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104540

1

T5

2

T6

2

T4

2

auto[1]

50723892

1

T5

1143

T6

2264

T4

16269

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7041

1

T5

2

T6

2

T4

2

auto[1]

50821391

1

T5

1143

T6

2264

T4

16269

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29166376

1

T5

1128

T6

1968

T4

16269

auto[1]

21662056

1

T5

17

T6

298

T4

2

---

Summary for Cross peri_cross

Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	6	0	6	100.00
Automatically Generated Cross Bins	6	0	6	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for peri_cross

Bins

csr_enable_cp

ip_clk_en_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

5104

1

T6

2

T1

2

T2

2

auto[0]

auto[0]

auto[1]

1268

1

T5

2

T4

2

T16

2

auto[0]

auto[1]

auto[0]

81455

1

T19

3

T41

39

T8

468

auto[0]

auto[1]

auto[1]

16713

1

T41

32

T8

442

T10

41

auto[1]

auto[1]

auto[0]

29079148

1

T5

1128

T6

1966

T4

16269

auto[1]

auto[1]

auto[1]

21644075

1

T5

15

T6

298

T16

1

User Defined Cross Bins for peri_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_enable_off	0	Excluded

Summary for Variable csr_enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

397748

1

T5

2

T6

2

T4

2

auto[1]

202525046

1

T5

4580

T6

7967

T4

65085

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8999

1

T5

2

T6

2

T4

2

auto[1]

202913795

1

T5

4580

T6

7967

T4

65085

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

116274694

1

T5

4511

T6

6777

T4

65077

auto[1]

86648100

1

T5

71

T6

1192

T4

10

---

Summary for Cross peri_cross

Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	6	0	6	100.00
Automatically Generated Cross Bins	6	0	6	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for peri_cross

Bins

csr_enable_cp

ip_clk_en_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

5104

1

T6

2

T1

2

T2

2

auto[0]

auto[0]

auto[1]

1268

1

T5

2

T4

2

T16

2

auto[0]

auto[1]

auto[0]

325781

1

T19

13

T41

129

T8

1630

auto[0]

auto[1]

auto[1]

65595

1

T41

127

T8

1733

T10

120

auto[1]

auto[1]

auto[0]

115941182

1

T5

4511

T6

6775

T4

65077

auto[1]

auto[1]

auto[1]

86581237

1

T5

69

T6

1192

T4

8

User Defined Cross Bins for peri_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_enable_off	0	Excluded

Summary for Variable csr_enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

233442

1

T5

2

T6

2

T4

2

auto[1]

103223056

1

T5

2289

T6

3982

T4

32544

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7428

1

T5

2

T6

2

T4

2

auto[1]

103449070

1

T5

2289

T6

3982

T4

32544

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59597436

1

T5

2256

T6

3389

T4

32541

auto[1]

43859062

1

T5

35

T6

595

T4

5

---

Summary for Cross peri_cross

Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	6	0	6	100.00
Automatically Generated Cross Bins	6	0	6	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for peri_cross

Bins

csr_enable_cp

ip_clk_en_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

5098

1

T6

2

T1

2

T2

2

auto[0]

auto[0]

auto[1]

1274

1

T5

2

T4

2

T16

2

auto[0]

auto[1]

auto[0]

195799

1

T19

6

T41

73

T8

892

auto[0]

auto[1]

auto[1]

31271

1

T41

67

T8

870

T10

71

auto[1]

auto[1]

auto[0]

59395483

1

T5

2256

T6

3387

T4

32541

auto[1]

auto[1]

auto[1]

43826517

1

T5

33

T6

595

T4

3

User Defined Cross Bins for peri_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_enable_off	0	Excluded