Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T19,T41
0	1	Covered	T41,T8,T10
1	0	Covered	T5,T6,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T41,T8
1	0	Covered	T14,T35,T36
1	1	Covered	T5,T6,T4

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	460181883	6362	0	0
GateOpen_A	460181883	12383	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460181883	6362	0	0
T3	329083	0	0	0
T8	0	146	0	0
T10	0	13	0	0
T14	9101	15	0	0
T15	11702	0	0	0
T16	3680	0	0	0
T17	4562	0	0	0
T18	89109	0	0	0
T19	10139	4	0	0
T20	11957	0	0	0
T35	0	23	0	0
T37	0	4	0	0
T38	7127	0	0	0
T41	0	35	0	0
T104	3323	0	0	0
T116	0	4	0	0
T186	0	42	0	0
T187	0	31	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460181883	12383	0	0
T1	509948	4	0	0
T2	123570	4	0	0
T3	0	4	0	0
T4	146754	0	0	0
T6	19009	4	0	0
T14	9101	19	0	0
T15	11702	4	0	0
T16	3680	0	0	0
T17	4562	4	0	0
T18	89109	0	0	0
T19	10139	8	0	0
T20	0	4	0	0
T104	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T19,T41
0	1	Covered	T41,T8,T10
1	0	Covered	T5,T6,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T41,T8
1	0	Covered	T14,T35,T36
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	50682532	1514	0	0
GateOpen_A	50682532	3018	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50682532	1514	0	0
T3	36554	0	0	0
T8	0	39	0	0
T10	0	2	0	0
T14	991	4	0	0
T15	1347	0	0	0
T16	391	0	0	0
T17	494	0	0	0
T18	9246	0	0	0
T19	1107	1	0	0
T20	1311	0	0	0
T35	0	6	0	0
T37	0	1	0	0
T38	856	0	0	0
T41	0	8	0	0
T104	362	0	0	0
T116	0	1	0	0
T186	0	10	0	0
T187	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50682532	3018	0	0
T1	56650	1	0	0
T2	13708	1	0	0
T3	0	1	0	0
T4	16293	0	0	0
T6	2284	1	0	0
T14	991	5	0	0
T15	1347	1	0	0
T16	391	0	0	0
T17	494	1	0	0
T18	9246	0	0	0
T19	1107	2	0	0
T20	0	1	0	0
T104	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T19,T41
0	1	Covered	T41,T8,T10
1	0	Covered	T5,T6,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T41,T8
1	0	Covered	T14,T35,T36
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	101365381	1614	0	0
GateOpen_A	101365381	3118	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101365381	1614	0	0
T3	73107	0	0	0
T8	0	38	0	0
T10	0	3	0	0
T14	1982	4	0	0
T15	2694	0	0	0
T16	782	0	0	0
T17	988	0	0	0
T18	18491	0	0	0
T19	2213	1	0	0
T20	2622	0	0	0
T35	0	6	0	0
T37	0	1	0	0
T38	1714	0	0	0
T41	0	10	0	0
T104	724	0	0	0
T116	0	1	0	0
T186	0	10	0	0
T187	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101365381	3118	0	0
T1	113299	1	0	0
T2	27415	1	0	0
T3	0	1	0	0
T4	32585	0	0	0
T6	4569	1	0	0
T14	1982	5	0	0
T15	2694	1	0	0
T16	782	0	0	0
T17	988	1	0	0
T18	18491	0	0	0
T19	2213	2	0	0
T20	0	1	0	0
T104	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T19,T41
0	1	Covered	T41,T8,T10
1	0	Covered	T5,T6,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T41,T8
1	0	Covered	T14,T35,T36
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	204088175	1606	0	0
GateOpen_A	204088175	3113	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204088175	1606	0	0
T3	146279	0	0	0
T8	0	34	0	0
T10	0	4	0	0
T14	4016	4	0	0
T15	5107	0	0	0
T16	1671	0	0	0
T17	2053	0	0	0
T18	37074	0	0	0
T19	4546	1	0	0
T20	5349	0	0	0
T35	0	6	0	0
T37	0	1	0	0
T38	3038	0	0	0
T41	0	9	0	0
T104	1491	0	0	0
T116	0	1	0	0
T186	0	10	0	0
T187	0	10	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204088175	3113	0	0
T1	226662	1	0	0
T2	54964	1	0	0
T3	0	1	0	0
T4	65250	0	0	0
T6	8104	1	0	0
T14	4016	5	0	0
T15	5107	1	0	0
T16	1671	0	0	0
T17	2053	1	0	0
T18	37074	0	0	0
T19	4546	2	0	0
T20	0	1	0	0
T104	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T19,T41
0	1	Covered	T41,T8,T10
1	0	Covered	T5,T6,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T41,T8
1	0	Covered	T14,T35,T36
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	104045795	1628	0	0
GateOpen_A	104045795	3134	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104045795	1628	0	0
T3	73143	0	0	0
T8	0	35	0	0
T10	0	4	0	0
T14	2112	3	0	0
T15	2554	0	0	0
T16	836	0	0	0
T17	1027	0	0	0
T18	24298	0	0	0
T19	2273	1	0	0
T20	2675	0	0	0
T35	0	5	0	0
T37	0	1	0	0
T38	1519	0	0	0
T41	0	8	0	0
T104	746	0	0	0
T116	0	1	0	0
T186	0	12	0	0
T187	0	8	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104045795	3134	0	0
T1	113337	1	0	0
T2	27483	1	0	0
T3	0	1	0	0
T4	32626	0	0	0
T6	4052	1	0	0
T14	2112	4	0	0
T15	2554	1	0	0
T16	836	0	0	0
T17	1027	1	0	0
T18	24298	0	0	0
T19	2273	2	0	0
T20	0	1	0	0
T104	0	1	0	0