Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	260996230	30095	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260996230	30095	0	0
T1	1168765	311	0	0
T2	94470	50	0	0
T3	670445	274	0	0
T7	0	99	0	0
T8	0	701	0	0
T9	0	126	0	0
T10	0	134	0	0
T11	0	179	0	0
T12	0	851	0	0
T13	0	203	0	0
T14	5235	0	0	0
T15	6380	0	0	0
T16	8695	0	0	0
T17	5020	0	0	0
T18	124020	0	0	0
T19	5205	0	0	0
T20	13925	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	52199246	4493	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52199246	4493	0	0
T1	233753	41	0	0
T2	18894	8	0	0
T3	134089	36	0	0
T7	0	16	0	0
T8	0	113	0	0
T9	0	22	0	0
T10	0	19	0	0
T11	0	23	0	0
T12	0	125	0	0
T13	0	30	0	0
T14	1047	0	0	0
T15	1276	0	0	0
T16	1739	0	0	0
T17	1004	0	0	0
T18	24804	0	0	0
T19	1041	0	0	0
T20	2785	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	52199246	4376	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52199246	4376	0	0
T1	233753	40	0	0
T2	18894	8	0	0
T3	134089	34	0	0
T7	0	15	0	0
T8	0	109	0	0
T9	0	22	0	0
T10	0	19	0	0
T11	0	22	0	0
T12	0	107	0	0
T13	0	26	0	0
T14	1047	0	0	0
T15	1276	0	0	0
T16	1739	0	0	0
T17	1004	0	0	0
T18	24804	0	0	0
T19	1041	0	0	0
T20	2785	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	52199246	6084	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52199246	6084	0	0
T1	233753	63	0	0
T2	18894	10	0	0
T3	134089	54	0	0
T7	0	21	0	0
T8	0	143	0	0
T9	0	25	0	0
T10	0	30	0	0
T11	0	37	0	0
T12	0	169	0	0
T13	0	41	0	0
T14	1047	0	0	0
T15	1276	0	0	0
T16	1739	0	0	0
T17	1004	0	0	0
T18	24804	0	0	0
T19	1041	0	0	0
T20	2785	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	52199246	6071	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52199246	6071	0	0
T1	233753	64	0	0
T2	18894	10	0	0
T3	134089	55	0	0
T7	0	20	0	0
T8	0	143	0	0
T9	0	27	0	0
T10	0	26	0	0
T11	0	38	0	0
T12	0	173	0	0
T13	0	41	0	0
T14	1047	0	0	0
T15	1276	0	0	0
T16	1739	0	0	0
T17	1004	0	0	0
T18	24804	0	0	0
T19	1041	0	0	0
T20	2785	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	52199246	9071	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52199246	9071	0	0
T1	233753	103	0	0
T2	18894	14	0	0
T3	134089	95	0	0
T7	0	27	0	0
T8	0	193	0	0
T9	0	30	0	0
T10	0	40	0	0
T11	0	59	0	0
T12	0	277	0	0
T13	0	65	0	0
T14	1047	0	0	0
T15	1276	0	0	0
T16	1739	0	0	0
T17	1004	0	0	0
T18	24804	0	0	0
T19	1041	0	0	0
T20	2785	0	0	0