Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Unreachable
1	0	Covered	T8,T10,T37

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	52199246	50012037	0	0
AllClkBypReqTrue_A	52199246	67536	0	0
IoClkBypReqFalse_A	52199246	49963589	0	2310
IoClkBypReqTrue_A	52199246	111906	0	0
LcClkBypAckFalse_A	52199246	50016010	0	0
LcClkBypAckTrue_A	52199246	63563	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52199246	50012037	0	0
T1	233753	233613	0	0
T2	18894	18838	0	0
T4	65249	65086	0	0
T5	652	620	0	0
T6	2279	2161	0	0
T14	1047	1014	0	0
T15	1276	1142	0	0
T16	1739	1498	0	0
T17	1004	895	0	0
T18	24804	24735	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52199246	67536	0	0
T1	233753	0	0	0
T2	18894	0	0	0
T4	65249	0	0	0
T6	2279	80	0	0
T8	0	1969	0	0
T10	0	118	0	0
T14	1047	0	0	0
T15	1276	82	0	0
T16	1739	0	0	0
T17	1004	9	0	0
T18	24804	0	0	0
T19	1041	0	0	0
T38	0	151	0	0
T75	0	27	0	0
T76	0	62	0	0
T91	0	288	0	0
T104	0	29	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52199246	49963589	0	2310
T1	233753	233611	0	3
T2	18894	18836	0	3
T4	65249	65084	0	3
T5	652	618	0	3
T6	2279	1589	0	3
T14	1047	1012	0	3
T15	1276	1130	0	3
T16	1739	1496	0	3
T17	1004	902	0	3
T18	24804	24733	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52199246	111906	0	0
T1	233753	0	0	0
T2	18894	0	0	0
T4	65249	0	0	0
T6	2279	650	0	0
T8	0	2130	0	0
T10	0	71	0	0
T14	1047	0	0	0
T15	1276	92	0	0
T16	1739	0	0	0
T17	1004	0	0	0
T18	24804	0	0	0
T19	1041	0	0	0
T38	0	397	0	0
T75	0	62	0	0
T76	0	57	0	0
T80	0	59	0	0
T91	0	451	0	0
T104	0	63	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52199246	50016010	0	0
T1	233753	233613	0	0
T2	18894	18838	0	0
T4	65249	65086	0	0
T5	652	620	0	0
T6	2279	1976	0	0
T14	1047	1014	0	0
T15	1276	1168	0	0
T16	1739	1498	0	0
T17	1004	904	0	0
T18	24804	24735	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52199246	63563	0	0
T1	233753	0	0	0
T2	18894	0	0	0
T4	65249	0	0	0
T6	2279	265	0	0
T8	0	1620	0	0
T10	0	30	0	0
T14	1047	0	0	0
T15	1276	56	0	0
T16	1739	0	0	0
T17	1004	0	0	0
T18	24804	0	0	0
T19	1041	0	0	0
T38	0	248	0	0
T75	0	44	0	0
T76	0	48	0	0
T80	0	27	0	0
T91	0	308	0	0
T104	0	24	0	0