Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	867232712	7607	0	0
TransStop_A	867232712	4079	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	867232712	7607	0	0
T3	609516	0	0	0
T7	966672	0	0	0
T8	420712	205	0	0
T10	0	4	0	0
T19	18944	4	0	0
T20	22288	29	0	0
T34	30936	12	0	0
T37	0	4	0	0
T38	12656	0	0	0
T41	6284	0	0	0
T78	0	16	0	0
T79	0	34	0	0
T91	11972	0	0	0
T104	6216	0	0	0
T116	0	4	0	0
T117	0	35	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	867232712	4079	0	0
T3	609516	0	0	0
T7	966672	0	0	0
T8	420712	106	0	0
T10	0	4	0	0
T19	18944	4	0	0
T20	22288	9	0	0
T28	0	5	0	0
T34	30936	8	0	0
T37	0	4	0	0
T38	12656	0	0	0
T41	6284	0	0	0
T78	0	7	0	0
T79	0	15	0	0
T91	11972	0	0	0
T104	6216	0	0	0
T116	0	4	0	0
T117	0	17	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	216808178	1918	0	0
TransStop_A	216808178	1026	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216808178	1918	0	0
T3	152379	0	0	0
T7	241668	0	0	0
T8	105178	51	0	0
T10	0	1	0	0
T19	4736	1	0	0
T20	5572	10	0	0
T34	7734	1	0	0
T37	0	1	0	0
T38	3164	0	0	0
T41	1571	0	0	0
T78	0	5	0	0
T79	0	7	0	0
T91	2993	0	0	0
T104	1554	0	0	0
T116	0	1	0	0
T117	0	10	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216808178	1026	0	0
T3	152379	0	0	0
T7	241668	0	0	0
T8	105178	26	0	0
T10	0	1	0	0
T19	4736	1	0	0
T20	5572	3	0	0
T28	0	5	0	0
T34	7734	0	0	0
T37	0	1	0	0
T38	3164	0	0	0
T41	1571	0	0	0
T78	0	1	0	0
T79	0	4	0	0
T91	2993	0	0	0
T104	1554	0	0	0
T116	0	1	0	0
T117	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	216808178	1864	0	0
TransStop_A	216808178	989	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216808178	1864	0	0
T3	152379	0	0	0
T7	241668	0	0	0
T8	105178	58	0	0
T10	0	1	0	0
T19	4736	1	0	0
T20	5572	7	0	0
T34	7734	2	0	0
T37	0	1	0	0
T38	3164	0	0	0
T41	1571	0	0	0
T78	0	3	0	0
T79	0	11	0	0
T91	2993	0	0	0
T104	1554	0	0	0
T116	0	1	0	0
T117	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216808178	989	0	0
T3	152379	0	0	0
T7	241668	0	0	0
T8	105178	29	0	0
T10	0	1	0	0
T19	4736	1	0	0
T20	5572	3	0	0
T34	7734	1	0	0
T37	0	1	0	0
T38	3164	0	0	0
T41	1571	0	0	0
T78	0	1	0	0
T79	0	5	0	0
T91	2993	0	0	0
T104	1554	0	0	0
T116	0	1	0	0
T117	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	216808178	1906	0	0
TransStop_A	216808178	1034	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216808178	1906	0	0
T3	152379	0	0	0
T7	241668	0	0	0
T8	105178	43	0	0
T10	0	1	0	0
T19	4736	1	0	0
T20	5572	6	0	0
T34	7734	3	0	0
T37	0	1	0	0
T38	3164	0	0	0
T41	1571	0	0	0
T78	0	5	0	0
T79	0	9	0	0
T91	2993	0	0	0
T104	1554	0	0	0
T116	0	1	0	0
T117	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216808178	1034	0	0
T3	152379	0	0	0
T7	241668	0	0	0
T8	105178	22	0	0
T10	0	1	0	0
T19	4736	1	0	0
T20	5572	2	0	0
T34	7734	3	0	0
T37	0	1	0	0
T38	3164	0	0	0
T41	1571	0	0	0
T78	0	3	0	0
T79	0	3	0	0
T91	2993	0	0	0
T104	1554	0	0	0
T116	0	1	0	0
T117	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	216808178	1919	0	0
TransStop_A	216808178	1030	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216808178	1919	0	0
T3	152379	0	0	0
T7	241668	0	0	0
T8	105178	53	0	0
T10	0	1	0	0
T19	4736	1	0	0
T20	5572	6	0	0
T34	7734	6	0	0
T37	0	1	0	0
T38	3164	0	0	0
T41	1571	0	0	0
T78	0	3	0	0
T79	0	7	0	0
T91	2993	0	0	0
T104	1554	0	0	0
T116	0	1	0	0
T117	0	10	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216808178	1030	0	0
T3	152379	0	0	0
T7	241668	0	0	0
T8	105178	29	0	0
T10	0	1	0	0
T19	4736	1	0	0
T20	5572	1	0	0
T34	7734	4	0	0
T37	0	1	0	0
T38	3164	0	0	0
T41	1571	0	0	0
T78	0	2	0	0
T79	0	3	0	0
T91	2993	0	0	0
T104	1554	0	0	0
T116	0	1	0	0
T117	0	4	0	0